JPH0779466B2 - Image display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention provides access to a center via a telephone network, for example.
The present invention relates to an image display device capable of receiving information such as character / graphics from the center and displaying it as a still image in a house or the like. More specifically, it relates not only to character / graphics but also to a natural image mixed with it. The present invention also relates to an image display device capable of displaying.

[Background of the Invention]

In devices that transmit and display still images using radio waves or telephone networks, in addition to transmitting and displaying simple character / graphic information such as that used in character broadcasting and captain systems, it can be used in general television broadcasting. Studies have been conducted to transmit and display natural image information that can be seen together.

For example, a natural image display as described in the paper "Digital still image home device" described on pages 159 to 171 of Research Practical Report Vol. 33, No. 8 of the Research Institute of Electrical Communication, Nippon Telegraph and Telephone Public Corporation. The function is a good example, and as an application example of such a function, a photograph is inserted in places on the newspaper surface when the still image display of character graphics is used on the newspaper surface in newspapers. However, in the same way as this, there is considered an application in which a natural image is inserted in some places on a still image display screen of character graphics to display a still image.

However, simple character / graphic information can be expressed by several bits per pixel, but natural image information requires a precision of 5 bits or more even for a single color to avoid false contours, and has a problem of requiring a large memory capacity. It was

To deal with such a problem, in the above-mentioned paper "Digital still image home device", one pixel of natural image information is decomposed into three primary colors red green blue and 5 bits are allocated to each, and it is also used as a memory for displaying character and graphic information. Then suggests a method to use.

However, in this case, although the frame memory capacity is as large as 100 kilobytes, the resolution is rough at 248 dots horizontally and 204 dots vertically, and the image quality as a natural image is still not sufficient. Nakatsuta.

Further, since a large capacity frame memory is required for displaying the natural image information, the conventional still image display device having a small memory capacity cannot have the natural image display function.

[Object of the Invention]

An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art and to enable an image display device with a limited memory capacity to display a high-quality natural image, in other words, a small memory capacity capable of displaying a natural image. It is to provide a still image display device.

[Outline of Invention]

To achieve the above object, in the present invention, in a still image display device that displays natural image information, the natural image information is stored in a state where it is encoded in a part or all of its frame memory. Further, other character / graphic information is decomposed into an image pattern and stored in the frame memory, and an identification information storage means for storing information for discriminating the difference between these storage states is also provided, and stored in the frame memory according to the identification information. By switching the reproducing means of the generated information, the natural image information and the character / graphic information can be reproduced on the same screen.

That is, the display 1 viewed in time series like the natural image information.
Pixel information that has a strong correlation with the information before the pixel is used to store it in the frame memory with high efficiency code, and if it has a weak correlation and a small number of colors, such as character and graphic information, it is decomposed into pixel patterns. The memory capacity used for the frame memory of the entire apparatus is reduced by storing the image data in the frame memory and reproducing the image.

Example of Invention

Hereinafter, the present invention will be described in detail with reference to examples. FIG. 1 is a block diagram showing an image display device as an embodiment of the present invention.

In the figure, 1 is a central arithmetic processing circuit integrated into a circuit (hereinafter abbreviated as CPU), 2 is a clock generation circuit for generating various clocks and timing signals, and 3 is a memory (hereinafter referred to as a program) in which processing procedures of the CPU 1 are stored. ROM is abbreviated. 4 is a rewritable memory of memory contents (hereinafter abbreviated as data RAM). 5 is a memory referred to when converting a character code into a character pattern to be displayed (hereinafter abbreviated as character pattern ROM). 6 is a memory. A keyboard, 7 is a keyboard interface circuit, 8 is an image information interface circuit, 9 is a switching circuit for switching between address information from the CPU 1 and read address information from the clock generation circuit 2, and 10 stores image information to be displayed. A frame memory, 11 is a color conversion circuit for converting color designation information into color information in the image information stored in the frame memory, and 12 is a frame memory. A decoding circuit for decoding the encoded image information stored in the memory, that is, the image information stored in the memory-saving information format in the form of a high-efficiency code into the original ordinary code format in preparation for display. , 13 is a switching circuit for switching and outputting each output signal of the color conversion circuit 11 and the decoding circuit 12, 14 is a D / A conversion circuit for converting a digital image signal into an analog signal, and 15 is to the still image display device. Image information input terminal for inputting image information from a telephone network (not shown), 16 is a display information output terminal for outputting display information to a display such as a cathode ray tube, and 17 is an address signal or data signal of the CPU 1. It is a bus to supply.

The basic operation of this device is as follows.

Information such as a screen number designated by the keyboard 6 is stored in the data RAM 4 via the keyboard interface circuit 7. On the other hand, the image information input from the image information input terminal 15 via the telephone network or the like is taken into the CPU 1 via the image information input interface circuit 8 and the image specified by the information stored in the data RAM 4 is specified. It is confirmed that the data is information, and when the switching circuit 9 is switched to the bus 17 side, it is written in the frame memory 10.

At this time, when it is determined that the character / graphic information is encoded, the character pattern ROM 5 is referred to, the character pattern is converted into a character pattern, and the color pattern information is written in the frame memory 10.

When it is determined that the high-efficiency-encoded natural image information is used, the high-efficiency code is directly written in the frame memory 10. These processing procedures are stored in the program ROM 3.

Further, the image information stored in the frame memory 10 is converted into color information by the color exchanging circuit 11 in the case of the color designation information such as the above character pattern, and is highly efficiently encoded in the switching circuit 13. In the case of natural image information, the decoding circuit 12 decodes the original image information in a general code format and supplies it to the switching circuit 13, and the switching circuit 13 selects one of the image signals. Are supplied to the D / A conversion circuit 14.

In the D / A conversion circuit, image information as digital information that is input is converted into analog information and output to a display device such as a cathode ray tube (not shown), so this display information should be displayed on the display information output terminal 16. Output analog information.

The above is the description of the basic operation of the image display device shown in FIG. 1. However, the image information stored in the frame memory 10 needs to be colored up to a thin line, such as character and graphic information, and the one with a large change in luminance is an image. Stored as a pattern, frame memory
Image information stored in 10 is displayed like natural image information 1
Information that has a strong correlation with the information before the pixel is stored as the high-efficiency code as described above. Can be configured.

Here, a little explanation will be added to an example of the high efficiency code.

If the natural image information is 8 bits per code, it is assumed that it is represented by an 8-bit code (general code). In general, a natural image often changes gradually in time series, and the information of the current pixel often has a strong correlation with the information of one pixel before. Therefore, as for the natural image information, when 8 bits forming one code are compared with 8 bits of the immediately preceding code in time series, if the correlation is strong, 8
Only the lower 4 bits among the bits change, and the upper 4
Bits often remain unchanged. In such a case, instead of transmitting the general code (8 bits), the lower 4
Only bits are used as a high-efficiency code and transmitted together with information indicating that (usually 1 bit).

Further, in a portion where the information content changes abruptly, such as the contour portion of the image, when comparing 8 bits forming one code of the natural image information with 8 bits of the immediately preceding code,
The change may extend to the upper 4 bits. At this time, the upper 4 bits are transmitted as a high-efficiency code together with information indicating that (usually 1 bit).

By doing so, the memory capacity can be reduced when transmitting and storing the high-efficiency code as compared with the case where the general code is transmitted and stored.

However, when displaying a natural image on the display, it is necessary to return the high efficiency code (4 bits) to the general code (8 bits) and then input it to the display (CRT). At the time of this return, if the high efficiency code of interest is the upper 4 bits,
If "0000" is unconditionally added as the lower 4 bits to return to an 8-bit code, and if the target high efficiency code is the lower 4 bits, the upper 4 bits to be added are also high before that. The upper 4 bits sent as the efficiency code are stored and added.

The operating principle of the present invention will now be understood more specifically.

Next, the decoding circuit 12 of FIG. 1 which is a main circuit of the present invention will be described in more detail.

FIG. 2 is a detailed circuit diagram of a main part including the decoding circuit 12 in FIG. 1, and FIG. 3 is an explanatory diagram for explaining the circuit operation of FIG.

In FIG. 2, the same circuit blocks as in FIG. 1 have the same symbols. Further, in the figure, 18 to 23 in the frame memory 10 are RAMs for storing image information and the like, and 24 to 29 are serial-parallel conversion circuits (hereinafter referred to as serial-parallel conversion circuits for converting parallel signals read from each RAM into serial signals).
It is abbreviated as SP conversion circuit).

Further, 30 in the color conversion circuit 11 is a multiplexer for switching the bus signal of the CPU 1 and the image signal read from the frame memory 10, and 31 is a color conversion RAM for storing color conversion information. Further, 32-34 in the switching circuit 13 are multiplexers. 35 in the decoding circuit 12 is a 4-bit latch for storing the high-order bits of the natural image information (that is, the high-order 4 bits in the high-efficiency code format), 36 is a multiplexer, 37 is an AND circuit, and 38 is a 4-bit latch. , 39 are comparators for identifying the increasing / decreasing direction of the upper bits of the natural image information.

Image information for displaying a screen including a natural image area 50 as shown in FIG. 3A is stored in RAM 18 to RAM 23 by the CPU 1.

That is, if the image information along the horizontal scanning direction indicated by line AA 'in FIG. 3 (a) is expressed as shown in FIG. 3 (b), it is output via the SP conversion circuits 24 to 29. Signal Z ₅
To Z ₀ is the information as shown in FIG. 3 (c). That is, the output signal Z ₅ read from the RAM 18 and the SP conversion circuit 24 represents information for discriminating the character graphic information from the natural image information, and when it is “1”, the natural image information (in the natural image area 50, Image information included).

When the output signal Z ₅ is “0”, it means character graphic information (image information included in the area outside the natural image area 50), and at this time, the other output signals Z _{4 to} Z ₀ are not changed. FIG. 3 shows color designation information of a figure pattern (assuming that the color is composed of two colors of black and white, it is represented by binary values M ₁ and M ₂ , so see M ₁ and M ₂ shown in FIG. 3C). .

In the case of natural image information, the output signal Z ₄ read from the RAM 19 and the SP conversion circuit 25 further identifies the meaning of the information having the other output signals Z _{3 to} Z ₀ . Ie output signal
When Z ₄ is “1”, the output signals Z _{3 to} Z ₀ are the upper 4 bits as the high efficiency code of the natural image information (H ₁ to H in FIG. 3C).
H ₃ reference, except H ₁ to H ₃ refers to certain represents the magnitude analog representation of) represented by the upper 4 bits each, the lower the high efficiency coding of natural image information at the time of "0" 4 bits (See L _{1 to} L _{4 in} Fig. 3 (c), but L ₁ to
L ₄ means an analog representation of a certain size, each represented by the lower 4 bits).

As described above, the frame memory 10 in FIG. 2 stores character graphic information and natural image information in a mixed manner. Particularly in the natural image portion, as described above, like the outline portion of the image, If the data changes drastically around that point and changes also appear in the top 4 bits, the top 4
Only the bits are stored as H _{1 to} H ₃ , and when the change of data is small and no change is seen in the upper 4 bits, such as in the flat part of the image, the lower 4 with a change.
Only the bits are stored as L _{1 to} L ₄ , and they are stored together with their identification information Z ₄ .

In the color conversion circuit 11, the CPU 1 stores the color information in advance in the color conversion RAM 31 via the multiplexer 30. For example, if the color conversion RAM 31 is a 32 × 12 bit memory, 4096
Output signal Z _{4 to} Z of the frame memory 10 from the colors (2 ¹² colors)
32 colors ( ²⁵ colors) designated by ₀ are selected and output to the switching circuit 13 as information of 4 bits for each of the three primary colors red, blue and green.

Further, in the decoding circuit 12, based on the output signal Z ₄ and the clock signal generated from the clock generation circuit 2, the register clock signal as shown in FIG.
4 bit latch 35 stores the upper 4 bits of the natural image signal from the frame memory 10 as shown in FIG. 3D, and the 4 bit latch 38 stores the upper 4 bits delayed by one.

The output signals of the 4-bit latches 35 and 38 are supplied to the comparator 39, which recognizes whether the change of the high-order 4 bits is in the increasing direction or the decreasing direction. The output signal of the comparator 39 is supplied to one input of the multiplexer 36, the output signals Z _{3 to} Z ₀ are supplied to the other input, and the output signal Z ₄ is supplied to the control input. , Fig. 3 (d)
The output as shown in the lower 4 bits of is obtained as the output of the multiplexer 36.

Therefore, as the natural image information, the originally quantized 8-bit image can be reproduced in the 5-bit frame memory. The natural image information thus decoded into 8 bits of information, which is the sum of the upper 4 bits and the lower 4 bits, is output to the switching circuit 13.

The switching circuit 13 is composed of three multiplexers 32, 33, and 34, each of which indicates the character / graphic information from the color conversion circuit 11.
The bit color information, the low-order 4 bits of the low-level L information, and the 8-bit natural image information from the decoding circuit 12 are switched by the output signal Z ₅ of the frame memory 10 and output. At this time, the multiplexers 32, 33, 34 respectively output red, blue, green image information.

The example of FIG. 2 shows an example in which a natural image is a black and white image. However, when the frame memory 10 has a 16-bit configuration as in the conventional example, it has three decoding circuits shown in FIG. An 8-bit quantized color natural image can be reproduced by assigning it to red, blue, green and decoding and supplying it to the switching circuit 13.

Next, a decoding circuit for reducing the memory capacity of the frame memory 10 to reproduce a natural color image will be described.

FIG. 4 is a block diagram showing another specific example of the decoding circuit 12 in FIG. Also, FIG. 5 is an explanatory diagram for explaining the circuit operation of FIG.

In FIG. 4, the output signals Z _{8 to} Z ₀ reproduced from the frame memory are luminance information (Y) and color difference information (R−
(Y, BY) are separated into three systems for reproduction, and finally the color difference information is converted into RGB information and supplied to the switching circuit 13. In the figure, 35 to 37 are multiplexers,
38-40, 44-46 are latches, 41-43 are adders, 52 is an OR circuit, 47-48 is a delay circuit that delays the signal by one clock, 49-
50 is an OR circuit, 51 is a bistable multivibrator circuit (hereinafter
FF circuit), 53 is a color difference RGB conversion circuit.

As is well known, in Japan, the standard television system (NTSC system) has an image signal bandwidth of 4.2 MHz, and color difference signal (I, Q signals or RY, BY signals) bandwidth. Are 1.5MHz and 0.5MHz respectively.

Therefore, in the natural image information, the luminance signal (Y) is treated as an 8-bit quantized signal and the color difference signals (RY, BY) as a 6-bit quantized signal. "1" to the output signal Z ₈ as shown, so as to reproduce the luminance signal (Y) in the output signal Z ₇ to Z _0, also at small luminance change, that is 4 bits luminance change information ( Fifth
Output signal if it can be represented by ΔY ₁ to ΔY ₈ ) in Fig. (A)
Storing image information in the frame memory 10 so as to reproduce the "0" to Z _8.

When the output signal Z ₈ is “0”, the color difference signals are recorded in the output signals Z _{3 to} Z ₀ as the image information to be reproduced in a dot-sequential manner, and the output signal Z ₈ is set to “1”. Then, the upper 4 bits of the color difference signal (C _{1R-Y to} C _3R-Y , C in FIG. 5A)
_{1B-Y to} C _2B-Y ), the color difference change information is 4 bits in the following clocks (ΔC _{1R-Y to} ΔC _2R-Y , ΔC in FIG. 5A).
_1B-Y ).

Inputting the output signals Z _{8 to} Z ₀ as shown in FIG. 5 (a), the multiplexer 37, 8 bit latch 40,
The adder 43 is responsible for decoding the luminance information. The 8-bit latch 40 holds 8 bits of the output signals Z _{7 to} Z ₀ of the frame memory 10 inputted through the multiplexer 37 when the output signal Z ₈ is "1", and thereafter, the output signal of the 8-bit latch 40 and the frame memory. Output signals Z _{7 to} Z ₄ from 10 and adder 43
Is added, and the output signal is input again by the multiplexer 37 to reproduce the luminance information.

Also, multiplexer 35, 6-bit latch 38, adder 41
The (RY) color difference signal is reproduced by the multiplexer 36, the 6-bit latch 39, and the adder 42 reproduces the (BY) color difference signal as in the case of the luminance signal.

However, the latch clock (CK input) supplied to the 6-bit latches 38 and 39 is the OR circuit 52 and the FF circuit 51 as shown in FIG.
As shown in FIG. 5, the output signal Z ₈ of the frame memory 10 and the clock signal supplied from the clock generation circuit 2 so as to match the color difference information reproduced in the dot-sequential manner are shown as Q and the output signal. It is a signal (however, only FIG. 5B shows it. Q is its inverted waveform).

Further, the control input of the multiplexer 35 is a Z ₈ delay signal shown as the output signal of the OR circuit 49 of FIG. 5B, which is formed by the delay circuit 47 and the OR circuit 49, based on the output signal Z ₈ . In addition, the control input of multiplexer 36
Signal as shown as an OR circuit 50 the output signal of FIG. 5 which is made by the delay circuit 48 and the OR circuit 50 based on Z ₈ delay signal (b) is supplied.

Furthermore, since the output signal Z ₈ is input to the latch inhibition input (E input) of the 6-bit latches 38 and 39, when the output signal Z ₈ is "1", the 8-bit quantization level of the luminance signal is Of the 6-bit quantization level of the (RY) color difference signal, "0" is given to the upper 4 bits and the lower 2 bits, and (B) to the next clock timing.
-Y) "0" can be recorded in the upper 4 bits and the lower 2 bits of the 6-bit quantization level of the color difference signal.

Further, since the difference luminance information represented by 4 bits and the difference color difference information represented by 4 bits are reproduced dot-sequentially at the subsequent clock timing, the 8-bit latch 40 and the 6-bit latch 38, 39 are respectively shown in FIG. Information as shown in c) can be reproduced as digital information.

As it is, since there is a time lag between each information,
The 6-bit latch 44 delays the (RY) color difference information by 1 clock time, and the 8-bit latches 45 and 46 delay the luminance information by 2 clock times to correct the time difference.
Input to the conversion circuit 53.

In the color difference RGB conversion circuit 53, the (RY) color difference signal and the (B−)
The (G-Y) color difference signal is synthesized from the (Y) color difference signal as shown in the following equation, and each is synthesized with the luminance signal (Y signal) to produce the 8-bit primary color signals RGB of red, green and blue, and the signals are supplied to the switching circuit 13.

G−Y = −0.51 (R−Y) −0.19 (B−Y) As described above, by using the decoding circuit 12 shown in FIG. 4, in the example of FIG. In contrast to reproducing quantized natural image information, it is possible to reproduce 8 bit quantized natural image information in 9 memory planes.
It is possible to reduce the memory capacity by about 40%.

Further, in the present invention, the quantization level of the luminance signal is not limited to 8 bits. For example, if the quantization level is 6 bits, in order to reproduce the color natural image information, the memory plane required for each primary color signal in the example of FIG. Since it becomes 4, the number of memory planes becomes 12, and in the example of FIG. 4, it becomes 7 memory planes, and the memory capacity can be greatly reduced.

Furthermore, when 6-bit quantization is performed in the example of FIG. 4, the memory capacity required is less than half that of the conventional 15-plane 5-bit quantization, so for example, with the same memory capacity, the sampling frequency is doubled. Thus, it becomes possible to display a high quality natural image.

Further, in the above example, the configuration in which the identification information of the character / graphic information and the natural image information is recorded in one memory plane is used so that the size, position and number of the natural image area can be selected freely. When there is one natural image area in one screen, four registers can be used instead of the memory plane.

Each register stores horizontal start point coordinate information, end point coordinate information, vertical start point coordinate information, end point coordinate information of the natural image area, and is generated from the clock generation circuit 2 to read the frame memory 10. It is possible to generate a signal indicating rectangular information on the screen by making a comparison with the coordinates indicated by the read address information. As described above, it is obvious that the present invention is effective even in a circuit in which one memory plane is simplified.

Further, in the example of FIG. 1, the image information is described as being supplied from a device other than the device. However, this device is used as a display unit of a device such as a small-sized computer (personal computer) or a digital television, and the device itself can display the image information. The present invention can be applied to the case where image information is encoded and stored in the frame memory.

〔The invention's effect〕

As described above, according to the present invention, it is possible to provide an image display device capable of displaying a high-quality natural image with a limited memory capacity, and it is effective in improving performance. Further, when the image quality is the same as the conventional one, it is possible to provide an image display device that can simultaneously realize a natural image display and a character / graphic display with a smaller memory capacity, which is economical.

[Brief description of drawings]

FIG. 1 is a block diagram showing an image display device as an embodiment of the present invention, FIG. 2 is a detailed circuit diagram of the main parts in FIG. 1, and FIG. 3 is a screen for explaining the operation of FIG. FIG. 4 is an explanatory diagram showing a display example, FIG. 4 is a block diagram showing another specific example of the decoding circuit shown in FIG. 1, and FIG. 5 is a display memory output signal for explaining the operation of FIG. FIG. Explanation of symbols 1 ... CPU, 2 ... clock generation circuit, 9 ... switching circuit, 10 ... frame memory, 11 ... color conversion circuit, 12 ...
Decoding circuit, 13 ... Switching circuit, 35 ... 4 bit latch,
36 …… Multiplexer, 38 …… 4 Bit-touch, 39 ……
Comparator, 35 to 37 …… Multiplexer, 38 to 40 ……
Latch, 41-43 …… Adder, 50 …… Natural image area

Claims (10)

[Claims] 1. An image display device for displaying image information by outputting image information such as character / graphic information and natural image information to a display means, wherein the character / graphic information is recorded as pattern information and the natural image information is recorded. A memory that can be recorded as high-efficiency code information, a decoding means that decodes the high-efficiency code information read from the memory into the original natural image information in real time, and a reproducing means that reproduces character / graphic information from the pattern information, The identification information storage means for storing identification information for identifying the difference in the recorded information in the memory, and the display by switching the decoded natural image information and the reproduced character / graphic information according to the identification information in the identification information storage means. An image display device characterized by comprising switching means for outputting to the means, and capable of displaying character graphic information and natural image information on the same display means. 2. The image display device according to claim 1, wherein the means for decoding the high efficiency code information is time-series among a plurality of bits constituting one pixel of the original natural image information. An image display device comprising a decoding means for decoding high-efficiency code information represented by bit information at a specific position which is relatively rich in change when compared with the immediately preceding pixel. 3. The image display device according to claim 1, wherein the means for decoding the high-efficiency code information is based on the high-efficiency code information having at least the difference luminance information and the difference color information and the original natural image. An image display device comprising a decoding means for decoding information. 4. The image display device according to claim 1, wherein the means for decoding the high efficiency code information is based on the high efficiency code information having at least the difference luminance information and the dot sequential difference color information. An image display device, which is a decoding unit that decodes the natural image information. 5. The image display device according to claim 1, wherein the means for decoding the high-efficiency code information is based on high-efficiency code information obtained by independently high-efficiency-coding red, blue, green and three primary color signals. An image display device comprising a decoding unit that decodes original natural image information. 6. The image display device according to claim 1, wherein the reproducing means for the character / graphic information is character / graphic information color-converted at least in pixel units of the pattern information read from the memory. An image display device having a color conversion unit for converting. 7. The image display device according to claim 1, wherein the identification information storage means is a part of the memory. 8. The image display device according to claim 1, wherein the identification information storage means is a register. 9. The apparatus according to claim 1, wherein the image display device further has an arithmetic processing circuit, and the memory records pattern information and high efficiency code information in the memory. An image display device characterized by the above. 10. The apparatus according to claim 1, wherein the image display device further has image information input means, and the memory has pattern information and high efficiency code input from the image information input means. An image display device in which information is recorded.