JPS6230381A - Manufacture of field effect transistor - Google Patents

Abstract

PURPOSE:To obtain the uniformity of recess etching by opening a window at every wiring portion wired so that the sources or drains of other elements formed on a semiconductor substrate than a monitor element are of the same potential, and then recess-etching. CONSTITUTION:Since the source and drain of each on are common by wiring metal 5, a monitoring current flows to that gathered from the gate width of the respective FETs. In this case, the chemical potential generated in contact with an etchant with the metal 5 is uniform for the FETs since the source and drain electrodes of the FETs are commonly connected, the recess etching amounts become uniform for the FETs, thereby accurately controlling the saturated currents Ids and the pinch-off voltages Vp of the FETs. The thus formed FETs are coupled at gate metals and wiring metals by metal, or individually separated and used as discrete devices. Thus, the chemical potentials at recess etching time become uniform.

Description

[Detailed Description of the Invention] [Summary] A method for monitoring recess etching of a gate of an electric field type J-type transistor, the source or drain of other elements formed on a semiconductor substrate other than the monitor element being at the same potential. Open a window and recess/cut/chip each wiring section so that the wires are routed. Uniformity of recess etching between the monitor element and other elements can be ensured.

[Industrial application field]

The present invention relates to a method for improving the reproducibility of gate recess etching amount, which is important in the manufacturing process of field effect transistors.

[Conventional technology]

A conventional method of recess etching the gate of a field effect transistor (FET) is shown in FIG. In the figure, (a) is an analysis view of the monitor element 1 used when performing recess etching, FIG. 6 (b) is a plan view thereof, and FIG. 6 (c) is a diagram of the element to be originally formed. FIG.

In FIG. 6, an active layer of n-G is formed on 1-GaAs2.
aAs layer 3. Source or drain electrodes 4s and 4d are formed, the gate portion 7g is patterned, and recess etching is performed. The monitor shows this recess etching
This is done for the current purpose, and when the gate pattern is formed, the source and drain of the monitor element shown in FIG. The current Tds (
The gate metal is formed after measuring the saturation current (saturation current) and confirming that it has reached a predetermined Ids.

FIG. 5 shows a planar configuration of an example in which parts 7s and 7d of the source and drain electrode metals of the conventional example are exposed, the central element is a monitor FET, and the elements on both sides are It is an FET.

[Problem that the invention seeks to solve]

However, when monitoring the saturation current rds between the monitor FET whose source and drain are exposed and the original FET to be manufactured where only the gate is exposed, it is found that the monitor FET Ids-IJ
(When the distance is 1 m, the Ids of the original FET is 12 (characteristic shown by the broken line), which is larger than the monitor FET,
As a result, the pinch-off voltage Vp of the FET has also been found to be high.

As a result of various studies conducted by the present inventor regarding this point, as shown in FIG. 6, part of the source and drain wiring metal of the monitor FET is exposed, and the etching solution may come into contact with this part. The chemical potential due to is the original F
It was found that the main reason was that it was different from ET.

[Means for Solving the Problems] In the present invention, when monitoring the recess etching of the gate of a field effect transistor, the source or drain of another element formed on the semiconductor substrate other than the monitor element is A window is opened for each wiring portion or electrode that is wired so that they have the same potential, and then recess etching is performed.

[Effect]

According to the present invention, since the source and drain of each FET are brought to the same potential in the recess etching solution, the chemical potential generated when the wiring metal comes into contact with the etching solution can be made uniform for each etching. Therefore, uniformity of recess etching between the monitor element and other elements can be ensured.

〔Example〕

Examples of the present invention
'l' is shown. The process will be explained below using the process diagram shown in FIG.

Figure A) Undoped jGa on semi-insulating GaAs substrate 1
A s 2 film J! Wl, c+m, n-Ga in active layer
As3 is epitaxially grown to a film thickness of t=0.4 μm with a carrier concentration n=In=l×10l7′.

Figure B) The source and drain electrodes 4 of the FET are formed by the lift-off method using an AZ resist.
Perform mesa etch to surround the drain and reach the substrate.

Figure C) Source and IS rain wiring (wiring metal 5Au
/ "Fi, film thickness: 3,000 layers) using the AZ lift-off method and patterning a part of the wiring to open a window.

Figure C and the plan view of the diagram are shown in Figure 1, and each FET
, the source and drain are each connected in common, and windows for contacting the etching solution are opened in portions 7s and 7d.

Using this monitoring window, recess etching is performed with a mixed solution of HF, H202, and H20 (recess etching depth ~0.2 μm) while monitoring the current flowing through the FET. Alternatively, use OMR as the resist and NaOH, H2O2, H2O as the etching solution.
Recess etching may be performed using a mixed solution of.

In this case, as shown in FIG. 1, the sources and drains of each FET are shared by the wiring metal 5, so that a monitor current equal to the gate width of each FET flows. At that time, the chemical potential generated when the wiring metal 5 comes into contact with the etching solution is
Since the source and drain electrodes of are connected in common,
Uniform for each 1” ET, therefore the recess
The amount of etching becomes uniform for each FET, and the saturation current ■ds and pinch-off voltage Vp of the FET can be controlled with high accuracy.

Figure E) Gate metal A28 using AZ lift-off method.
(film thickness: 3,000 people).

The FET formed as described above is used as a discrete device by connecting the gate metal and each wiring metal with metal, or by separating them individually.

Next, FIG. 3 shows an example in which the present invention is applied to an IC.

Figure A shows an IC chip, in which there are many FETQI
, Q2. ... is starting to be formed,
A monitor FET (M) is formed in a part of the chip. Generally, these FETs are wired in a predetermined manner. Therefore, when recessing and etching the gate,
Open a window in each of the commonly connected portions of the source and drain so that they can come in contact with the etching solution. Taking as an example the case where the wires are connected as shown in Figure 3B, 4 of a - d
All you have to do is open one window. This opening may be done using a bonding window (for example, 50 x 50 μm), but
In the present invention, since it is only necessary for the electrode metal to come into contact with the etching solution, it is sufficient to form a dedicated window that is sufficiently small (for example, about 5 x 5 μm), and even if it is formed at an arbitrary location, it will cause problems in later steps. It won't happen.

Although the embodiments have been described above, the present invention can be modified in various ways regardless of the embodiments. In short, it is sufficient if the chemical potentials of the source and drain of the monitor FET and the original FET are made uniform during recess etching. Therefore, the original F
One per ET common connection wiring, or if there is an electrode that is not connected to any other electrode, an 11[1i1] etching solution contact window may be provided at the common potential portion.

[Brief explanation of drawings]

FIG. 1 is a plan view of an embodiment of the present invention, FIGS. 2 A to E are sectional views of the manufacturing process of the embodiment of the present invention, and FIGS. 3 A and B are explanatory diagrams of other embodiments of the present invention. FIG. 4 is a monitor characteristic diagram of an FET, FIG. 5 is a plan view of a conventional example, and FIGS. 6(a) to (C) are explanatory diagrams of recess etching of a conventional FET. Main code ■...Sr (semi-insulating) Qa71. s board 2...-
1-GaAs layer 3--- n-GaAs1'5 4... Electrode (source, drain) metal 5... Wiring metal 6... AZ resist 7... Gate part 8... Gate electrode

Claims (1)

[Claims] When recessing and etching the gate of a field-effect transistor, cover the surface of the semiconductor substrate with a resist, and connect the wiring or electrodes of the sources or drains of elements other than the monitor element on the semiconductor substrate so that they have the same potential. 1. A method for manufacturing a field effect transistor, which comprises forming a window in each wiring or electrode portion, and then performing recess etching.