JPS6230342A - Semiconductor device - Google Patents

Abstract

PURPOSE:To microminiaturize a pattern by forming a plurality of bumps on the periphery and the interior of a chip, obtaining a distance between bumps capable of connecting with a conductor pattern on a thin insulating plate and forming on a thin polyimide plate a pattern except the bump connector and external connector. CONSTITUTION:A semiconductor chip 1 has a plurality of bumps, which are formed of bumps 2a existing on the periphery and bumps 2b existing in the interior. A bump connector hole 4 and an external connector hole 5 of a thin plate 3 of polyimide (insulator) are punched in advance, a copper foil is contacted closely on the plate 3, and the prescribed pattern 6 is then formed. In other words, an insulating circuit board having the gold-plated pattern exposed in the holes 4, 5 on the plate 3 is formed. The pattern projected to the hole of the thin plate and a plurality of bumps 2a, 2b on the chip are positioned at 1:1 and connected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a terminal connection technique for a semiconductor device, and more particularly to a lead terminal connection technique for a semiconductor chip having multiple terminals.

[Conventional technology]

Conventionally, this type of lead terminal connection involves forming bump electrodes on the periphery of a semiconductor chip, and connecting the bumps to a wiring pattern formed on a polyimide tape (TAB
pe Automated Bonding) technology.

[Problem that the invention seeks to solve]

In the conventional lead terminal connection technology described above, connection bumps exist only on the periphery of the semiconductor chip, making it difficult to form necessary output lead terminals in semiconductor devices that require many input/output lead terminals. There is a drawback that. That is, FIG. 2(a) is a plan view showing a conventional electrode lead drawer, and FIG. 2(b) is a sectional view. In the figure, 11 is a semiconductor chip having a bump electrode 12 on its periphery, and a gold-plated copper pattern 16 formed on a 35u wide polyimide tape 13 is connected to a bump electrode m12. The copper pattern 16 is in a cantilevered state without the support of the polyimide chip 13 at the connection portion with the semiconductor chip 11. Therefore, when the pitch of the pattern 16 is narrowed for multi-terminal connection, the width of the pattern also becomes narrow, the strength deteriorates, the accuracy of the pattern decreases, and the connection between the bumps 12 and the pattern 16 becomes difficult.

On the other hand, in a semiconductor chip that requires many input/output terminals in order to form bumps 12 around it, as shown in the plan view of FIG. 2(a), the distance between the bumps 12 becomes narrow. Therefore, it becomes difficult to realize a semiconductor chip that requires many input/output terminals, that is, many bumps 12. And vice versa,
When attempting to secure the necessary distance between bumps and form many bumps around the semiconductor chip, the size of the semiconductor chip increases, the yield decreases, and the cost increases.

[Means for solving problems]

The semiconductor device of the present invention - has a lead connected to the bump of a semiconductor chip having a plurality of bump electrodes on the surface, around the periphery, and inside the semiconductor chip; and one end of the conductor pattern is made to protrude into a hole drilled at the bang position of the tip of the 94-board board and connected to the bang, and the other end of the conductor pattern is exposed to the external connection hole and connected to the outside. Connection is established.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1(a) is a plan view of an embodiment of the present invention, and FIG. 1(b) is a plan view of an embodiment of the present invention.
is a sectional view taken along line A-A in FIG. In these figures, a semiconductor chip 1 has a plurality of bumps, and the bumps are composed of a bump 2a existing on the periphery and a bump 2b existing inside. On the other hand, polyimide (exquisite) thin plate 3
The bump connection holes 4 and the external connection holes 5 are punched out in advance, and the steel foil is tightly attached onto the polyimide thin plate 3. Thereafter, a predetermined pattern 6 is formed using well-known etching and plating techniques. That is, an insulating wiring board having a gold-plated pattern exposed in the bump connection hole 4 and the external connection hole 5 on the polyimide thin plate 3 is formed.

The conductor pattern protruding from the bump connection hole 4 of this thin wiring board and the plurality of bumps 2a, 2b on the chip are aligned one to one, and both are connected by a connection technique known in the art. In this way, a semiconductor device having many input/output lead terminals is realized.

〔Effect of the invention〕

As explained above, the present invention forms a plurality of bumps on the periphery and inside of a chip, connects them to a conductor pattern on a thin insulating plate, secures a distance between the bumps, and connects the bumps to the external connection area. By forming other patterns on a polyimide thin plate, it is possible to miniaturize the pattern, which has the effect of realizing a semiconductor device that requires many input/output lead terminals.

[Brief explanation of drawings]

1al is a plan view of a thin wiring board and a semiconductor chip connected thereto according to one embodiment of the present invention, and FIG.
Figure 2 (a) is a plan view of a conventional P3 tape and a semiconductor chip connected to it; Figure 2 (tb)
is A-A#! in figure (a). A mask with a picture. 1.11... Semiconductor chip, 2a...
Peripheral bump, 2b --- Internal bang, 3.13.
...Polyimide thin plate, 4...Bump hole,
5... External connection hole, 6゜16... Conductor pattern. 7, child; 69□, agent: Susumu Uchihara, patent attorney (ha, -1,”・(
Figure 7 (ll) rb) Figure 2

Claims (1)

[Claims] In a semiconductor device in which a conductive pattern provided on an insulating thin plate is connected to a bump electrode on a semiconductor chip and an electrode lead of the chip is drawn out, the bump electrode on the chip is also provided around and inside the chip, and , the insulating thin plate has a hole formed at the position of the bump electrode and an external connection part, the conductor pattern protrudes or is exposed in the hole, and the tip of the conductor pattern protruding into the bump position hole is connected to the bump electrode. A semiconductor device characterized by: