JPS62299080A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62299080A JPS62299080A JP14194886A JP14194886A JPS62299080A JP S62299080 A JPS62299080 A JP S62299080A JP 14194886 A JP14194886 A JP 14194886A JP 14194886 A JP14194886 A JP 14194886A JP S62299080 A JPS62299080 A JP S62299080A
- Authority
- JP
- Japan
- Prior art keywords
- glass substrate
- amorphous silicon
- silicon nitride
- tpt
- thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 10
- 239000011521 glass Substances 0.000 claims abstract description 10
- 238000010438 heat treatment Methods 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims abstract description 6
- 239000010409 thin film Substances 0.000 claims abstract description 5
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 6
- 239000010408 film Substances 0.000 abstract description 4
- 238000002161 passivation Methods 0.000 abstract description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 abstract description 2
- 229910021344 molybdenum silicide Inorganic materials 0.000 abstract description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000012212 insulator Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
Description
【発明の詳細な説明】
３、発明の詳細な説明
産業上の利用分野
本発明は液晶等と組合せて画像表示装置を構成するため
の非晶質シリコン半導体よりなる薄膜トランジスタ（以
後ＴＰＴと呼ぶ）をガラス基板上にマトリックス状に形
成した半導体装置の製造方法に関するものである。[Detailed Description of the Invention] 3. Detailed Description of the Invention Industrial Field of Application The present invention relates to a thin film transistor (hereinafter referred to as TPT) made of an amorphous silicon semiconductor for constructing an image display device in combination with a liquid crystal or the like. The present invention relates to a method of manufacturing a semiconductor device formed in a matrix on a glass substrate.
従来の技術
第３図にＴＰＴの断面構造の一例であり、液晶等と組合
せて画像表示装置を構成する半導体装置はこのＴＰＴを
マトリックス状に多数配置したものである。BACKGROUND OF THE INVENTION FIG. 3 shows an example of the cross-sectional structure of a TPT. A semiconductor device that is combined with a liquid crystal or the like to form an image display device has a large number of TPTs arranged in a matrix.
従来このような半導体装置の各場所の代表のＴＰＴ％性
〔ドレイン電流（Ｉｄ）−ゲート電圧（Ｖｇ）特性〕を
測定すると第２図に示す特性が得られた。Conventionally, when representative TPT % characteristics (drain current (Id)-gate voltage (Vg) characteristics) at each location of such a semiconductor device were measured, the characteristics shown in FIG. 2 were obtained.
この図に示されるように各場所により特性に差を生じ、
特にオフ電流（本説明ではゲート電圧がＯＶの時のドレ
イン電流を指す）が著しく異なり不均一であった。As shown in this figure, there are differences in characteristics depending on the location,
In particular, the off-state current (in this description, refers to the drain current when the gate voltage is OV) was significantly different and non-uniform.
発明が解決しようとする問題点
上述したような各ＴＰＴ特性が不均一である半導体装置
を使用して液晶画像表示装置を構成した場合、画面の輝
度むら等の画質の劣化が発生する。Problems to be Solved by the Invention When a liquid crystal image display device is constructed using semiconductor devices having non-uniform TPT characteristics as described above, deterioration of image quality such as uneven brightness of the screen occurs.
一方ＴＰＴ特性が不均一になる原因として、ＴＰＴの表
面に存在する水分等による漏れ電流。On the other hand, one of the causes of non-uniform TPT characteristics is leakage current due to moisture etc. existing on the surface of TPT.
ＴＦＴの主材料となっている半導体層と絶縁体層との界
面に不安定な不純物準位が存在することなどが考えられ
る。It is conceivable that unstable impurity levels exist at the interface between the semiconductor layer, which is the main material of the TFT, and the insulator layer.
本発明はかかる問題点に鑑みなされたもので、簡易な工
程により半導体装置の各ＴＰＴ特性を均一化することを
目的とする。The present invention was made in view of such problems, and an object of the present invention is to make each TPT characteristic of a semiconductor device uniform through a simple process.
問題点を解決するための手段
上記問題点を解決するための本発明の技術的手段はＴＦ
Ｔを形成し配線した後に１６０〜３００℃の基板温度に
加熱保持する工程を実施することである。Means for solving the problems The technical means of the present invention for solving the above problems is TF
After forming the T and wiring, a step of heating and holding the substrate at a temperature of 160 to 300° C. is carried out.
作用
本発明は上述した技術的手段により、ＴＰＴの−表面に
存在する水分等の不純物を除去し、さらに半導体層と絶
縁体層との界面に存在する不安定な不純物準位を消失せ
しめてＴＰＴのオフ電流を安定化して各ＴＰＴ特性を均
一化して、輝度むら等画質の劣化のない液晶画像表示装
置を構成できる半導体装置が得られる。Operation The present invention uses the above-mentioned technical means to remove impurities such as moisture existing on the surface of TPT, and further eliminates unstable impurity levels existing at the interface between the semiconductor layer and the insulator layer. By stabilizing the off-state current and making each TPT characteristic uniform, it is possible to obtain a semiconductor device that can constitute a liquid crystal image display device without deterioration of image quality such as uneven brightness.
実施例
以下、本発明の一実施例について第３図とともに説明す
る。EXAMPLE Hereinafter, an example of the present invention will be described with reference to FIG.
ガラス基板１上にゲート電極２を選択的に被着形成した
後、ゲート絶縁膜３となる窒化シリコン。After selectively depositing a gate electrode 2 on a glass substrate 1, silicon nitride is deposited to become a gate insulating film 3.
半導体層となる非晶質シリコン４．パッシベーション用
窒化シリコン６をプラズマＣＶＤ法により順次被着する
。次に前記パッシベーション用窒化シリコン、非晶質シ
リコンを選択的に除去した後、リンを添加した非晶質シ
リコン６ａ 、６ｂ、モリフ゛デンシリサイド了ａ、７
ｂ１アルミニウム８２Ｌ。Amorphous silicon that becomes the semiconductor layer 4. Passivation silicon nitride 6 is sequentially deposited by plasma CVD. Next, after selectively removing the passivation silicon nitride and amorphous silicon, phosphorus-doped amorphous silicon 6a, 6b, molybdenum silicide a, 7
b1 aluminum 82L.
８ｂを順次選択的に被着し、６ａ、７ａ、８ａよりなる
ソース電極、６ｂ 、７ｂ 、８ｂよりなるドレイン電
極を形成する。8b is sequentially and selectively deposited to form a source electrode consisting of 6a, 7a, and 8a, and a drain electrode consisting of 6b, 7b, and 8b.
次に前記基板を熱処理オープンを使用してたとえば基板
温度２００℃で３０分間保持する。Next, the substrate is held at a substrate temperature of 200° C. for 30 minutes using an open heat treatment.
上述のように作製したＴＰＴの特性を第１図に示す。図
に示すように、基板の各場所に形成されたＴＰＴの特性
は均一であった。The characteristics of the TPT produced as described above are shown in FIG. As shown in the figure, the characteristics of the TPT formed at each location on the substrate were uniform.
次に種々の温度で熱処理を行ないそのＴＰＴ特性を測定
した場合、上述と同様の効果が１６０°Ｃ以上で見られ
たが、３００℃以上で熱処理した場合、オフ電流が大き
くなり、かつオン電流が小さくなってＴＰＴが劣化した
。Next, when we performed heat treatment at various temperatures and measured the TPT characteristics, we found that the same effect as described above was seen at temperatures above 160°C, but when heat treated at temperatures above 300°C, the off-state current increased and the on-state current increased. became smaller and TPT deteriorated.
従って、熱処理の温度は１６０℃〜３００℃が最適であ
る。Therefore, the optimum temperature for heat treatment is 160°C to 300°C.
他の実施例について説明する。Other embodiments will be described.
前述した工程によりソース・ドレイン電極を形成した後
、液晶画像表示装置を組立てるために配向膜を塗布し、
その後１６０℃〜３００℃の温度で熱処理を行なう。こ
のような工程によっても前記第１の実施例と同様な効果
が得られた。After forming the source and drain electrodes through the steps described above, an alignment film is applied to assemble the liquid crystal image display device.
Thereafter, heat treatment is performed at a temperature of 160°C to 300°C. Even through such a process, the same effects as in the first embodiment were obtained.
発明の効果
以上述べてきたように本発明はガラス基板上に多数ＴＰ
Ｔを形成した後、１６０℃〜３００°Ｃで熱処理を行な
うことにより、そのＴＰＴ特性を均一化する効果を有し
、画質の劣化のない液晶画像表示装置を構成する半導体
装置を製造できる。Effects of the Invention As described above, the present invention provides a large number of TPs on a glass substrate.
After forming the T, heat treatment at 160° C. to 300° C. has the effect of making the TPT characteristics uniform, and it is possible to manufacture a semiconductor device constituting a liquid crystal image display device with no deterioration in image quality.
第１図は本発明の一実施例におけるＴＰＴ特性を示す図
、第２図は従来のＴＰＴ特性を示す図、第３図はＴＰＴ
の構造断面の一例を示す図である。
１・・・・・・ガラス基板、２・・・・・・ゲート電極
、３・・・・・・ゲート絶縁膜、４・・・・・・非晶質
シリコン。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
一、５１’ ０ ５ １０ １５ Ｚｔ）す（ｖ）
第２図
一δ ０ ５ １０ １５ ２θ
リ （Ｖ）
／ −−一力゛ラス１ミ反
２−−−ゲート篭不ｉ
３−−−ゲート洲乞判に膠、
４−一井西貢シリコン
第３図FIG. 1 is a diagram showing TPT characteristics in an embodiment of the present invention, FIG. 2 is a diagram showing conventional TPT characteristics, and FIG. 3 is a diagram showing TPT characteristics in an embodiment of the present invention.
It is a figure showing an example of a structural cross section of. DESCRIPTION OF SYMBOLS 1... Glass substrate, 2... Gate electrode, 3... Gate insulating film, 4... Amorphous silicon. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Fig. 1, 51' 0 5 10 15 Zt) (v) Fig. 2 - δ 0 5 10 15 2θ li (V) / --One force = 1 min. 2---Gate cage failure i 3-- -Glue at the gate, 4-Ichii Saikung Silicon Diagram 3
Claims (1)
する薄膜トランジスタを複数形成し配線した後に、前記
ガラス基板を１６０℃〜３００℃の温度に加熱保持する
工程を有する半導体装置の製造方法。A method for manufacturing a semiconductor device, comprising the steps of forming and wiring a plurality of thin film transistors whose semiconductor layers are mainly made of amorphous silicon on a glass substrate, and then heating and holding the glass substrate at a temperature of 160° C. to 300° C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61141948A JP2687959B2 (en) | 1986-06-18 | 1986-06-18 | Method for stabilizing thin film transistor characteristics |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61141948A JP2687959B2 (en) | 1986-06-18 | 1986-06-18 | Method for stabilizing thin film transistor characteristics |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62299080A true JPS62299080A (en) | 1987-12-26 |
| JP2687959B2 JP2687959B2 (en) | 1997-12-08 |
Family
ID=15303858
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61141948A Expired - Lifetime JP2687959B2 (en) | 1986-06-18 | 1986-06-18 | Method for stabilizing thin film transistor characteristics |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2687959B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01253965A (en) * | 1988-04-01 | 1989-10-11 | Toppan Printing Co Ltd | Manufacture of thin film transistor array |
| US6338874B1 (en) * | 1993-01-28 | 2002-01-15 | Applied Materials, Inc. | Method for multilayer CVD processing in a single chamber |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5968975A (en) * | 1982-10-12 | 1984-04-19 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
-
1986
- 1986-06-18 JP JP61141948A patent/JP2687959B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5968975A (en) * | 1982-10-12 | 1984-04-19 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01253965A (en) * | 1988-04-01 | 1989-10-11 | Toppan Printing Co Ltd | Manufacture of thin film transistor array |
| US6338874B1 (en) * | 1993-01-28 | 2002-01-15 | Applied Materials, Inc. | Method for multilayer CVD processing in a single chamber |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2687959B2 (en) | 1997-12-08 |
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