JPS62298115A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To shorten the time required for manufacture of a dielectric film by a method wherein the lower silicon film, the silicon nitride film and the upper silicon oxide film, which constitute a dielectric film, are formed by the same process using the same manufacturing device. CONSTITUTION:A field insulating film 2 is formed on a semiconductor substrate 1, and a p-channel stopper region 3 is formed under the film 2. The entire surface of the semiconductor substrate 1 exposed from the field insulating film 2 and the inner wall of a groove 6 are oxidized, and the silicon oxide film 7A, which is a part of the dielectric film of a capacitor, is formed. The silicon nitride film 7B, which is a part of the dielectric film, is formed on the silicon oxide film 7A. Then, the surface of the silicon nitride film 7B is oxidized in the same device, and a silicon oxide film 7C, which is a part of the dielectric film, is formed. The above-mentioned films are formed in the same process and in the same film-forming device as mentioned above without taking in ind out a wafer 1. Then, a polycrystalline silicon film 8, which becomes a capacity electrode later, is formed on the whole surface of the semiconductor substrate 1.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a thin film forming technique, and is particularly effective when applied to a technique of forming a dielectric film of a capacitive element. It is related to technology.

[Conventional technology]

The technology for constructing the dielectric film of a capacitive element by laminating a silicon oxide film, a silicon nitride film, and a silicon oxide film in order from the bottom is described in the Nikkei Electronics special issue "Micro Devices J pH" published by Nikkei McGraw-Hill on August 22, 1983.
2 to P116. The lower silicon oxide film, silicon nitride film, and upper silicon oxide film constituting the three-layer film are each formed in different steps using different manufacturing apparatuses.

[Problem that the invention seeks to solve]

As a result of studying the above technology, the inventor found the following problem.

It seems that each of the 23 layers was formed in separate processes.

The time required for film formation increases due to loading and unloading of wafers, transportation, etc.

Also, while transferring wafers from one manufacturing device to the next, C.
, Fe, Cu, etc.

An object of the present invention is to shorten the time required to manufacture a semiconductor integrated circuit device.

Another object of the present invention is to improve the reliability of a semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, each of the three-layer film or the two-layer film is formed within the same manufacturing apparatus.

[Effect]

According to the above-described means, each of the three-layer film or the two-layer film can be formed in the same process, so that the time required for manufacturing a semiconductor integrated circuit device can be shortened. Furthermore, contamination of the dielectric film can be reduced and reliability of the semiconductor integrated circuit device can be improved.

〔Example〕

1 to 10 are cross-sectional views of a memory cell in a DRAM manufacturing process.

As shown in FIG. 1, a field insulating film 2 made of a silicon oxide film is formed by oxidizing a predetermined surface of a semiconductor substrate (wafer) 1 made of p-type single crystal silicon so as to define a memory cell region. Also, a p-type channel stopper region 3 is formed under the field insulating film 2. Next, the surface of the semiconductor substrate 1 exposed from the field insulating film 2 is oxidized to form a silicon oxide film 4 as a base film for an etching mask 5 made of a silicon oxide film to be formed later. Next, a silicon oxide film is formed on the entire surface of the semiconductor substrate 1 by, for example, CVD, and this is patterned by etching using a mask made of a resist film (not shown) to form an etching mask 5 with openings in the grooves 6. do. The mask made of a resist film is removed after the etching mask 5 is formed. Next, the silicon oxide film 4 exposed through the mask 5 is removed by etching, and the surface of the semiconductor substrate 1 exposed by this etching is then subjected to reactive ion etching (RIE).
) to form grooves 6. Groove 6 is formed in a predetermined region of the main surface of semiconductor substrate 1 . ) After forming the substrate 6, the etching mask 6 made of a silicon oxide film and the silicon oxide film 4 as a base film are removed.

Next, as shown in FIG. 2, the entire surface of the semiconductor substrate 1 exposed from the field insulating film 4 and the inner wall of the trench 6 are oxidized to form a silicon oxide film that is part of the dielectric film of the capacitive element. 7A is formed.

Now, a forming apparatus for forming the silicon oxide film 7A, a silicon nitride film 7B, and a silicon oxide film 7C to be formed later will be explained with reference to FIG.

FIG. 11 is a schematic diagram of a low pressure reactor for forming the dielectric film 7.

In FIG. 11, 17 is a quartz tube, 18 is a closing lid of the quartz tube 17, 19 is an introduction tube for sending reaction gas and carrier gas into the quartz tube 17, 20 is a susceptor, 21 is a heating coil, and 22 is an exhaust gas. It's a tube. A plurality of wafers (semiconductor substrates) 1 are placed on a susceptor 20. This device is of the Hot Wall type.

To form the silicon oxide film 7A.

O12,'02 + HCl or N20 as reaction gas
The oxidation temperature is about 700 to 1000°C. N2 is used as the carrier gas.

Next, as shown in FIG. 3, the silicon oxide film 7A is
A silicon nitride film 7B, which is part of the dielectric film, is formed on A by CVD. Since the silicon nitride film 7B will later oxidize the surface of the silicon nitride film 7B to form a silicon oxide film 7C, it is formed to a thickness that allows the silicon oxide film 7C to be formed. S i Ha + N Hs is used as a reaction gas for forming the silicon nitride film 7B. The inside of the forming apparatus is kept at an atmospheric pressure of about 0.1 Toll so that the growth rate of the silicon nitride film 7B on the wafer 1 is uniform.

Next, as shown in FIG. 4, the surface of the silicon nitride film 7B is oxidized to form a part of the dielectric film in the same device used to form the silicon oxide film 7A and silicon nitride *7B. A silicon oxide film 7C is formed. Either 02.02 + HCl or H2O is used as the reaction gas, and the oxidation temperature is about 700 to 1000C.

In this way, the silicon oxide film 7A, the silicon nitride film 7B
The silicon oxide film 7C is formed in the same forming apparatus in the same process without taking the wafer 1 in and out. For this reason, from the formation of the silicon oxide film 7A to the formation of the silicon oxide film 7C.
The time required to complete the formation can be shortened.

Further, since the wafer 1 does not need to be removed from the forming apparatus during the period from the silicon oxide film 7A to the silicon oxide film 7C, the films 7A, 7B, and 7C are prevented from being contaminated by C1Fe, Cu, etc. Can be done. This improves the reliability of the dielectric breakdown voltage and the like of the dielectric film constituted by the films 7A, 7B, and 7C, so that the reliability of the semiconductor integrated circuit device can be improved.

In the following description, the silicon oxide film 7A, the silicon nitride film 7B, and the silicon nitride film 7C are illustrated as one Mfi body [7].

Next, as shown in FIG. 5, a polycrystalline silicon film 8, which will later become a capacitor electrode, is formed over the entire surface of the semiconductor substrate 1 by, for example, CVD. The inside of trench 6 is filled with polycrystalline silicon film 8 without creating a cavity. In order to lower the resistance of the capacitor electrode 8 (see FIG. 7), an N-type impurity, for example, phosphorus<P, is introduced into the polycrystalline silicon film 8 by thermal diffusion, ion implantation, or the like.

Next, as shown in FIG. 6, unnecessary polycrystalline silicon film 8 on semiconductor substrate 1 is removed by etching polycrystalline silicon film 8 from the upper surface by RIE.

Next, as shown in FIG. 7, a polycrystalline silicon film 8 is formed again on the semiconductor substrate 1 by, for example, CVD, and this polycrystalline silicon film 8 is etched using a mask made of a resist film (not shown). patterning,
A capacitor electrode 8 on the semiconductor substrate 1 is formed. The portion of the capacitor electrode 8 on the semiconductor substrate 1 is provided in the entire area except the selected MISFET area in the memory cell array area.

The capacitor electrode 8 is made up of a polycrystalline silicon film 8 provided on the semiconductor substrate 1 and a polycrystalline silicon film 8 embedded in the groove 6 .

Next, as shown in FIG. 8, the exposed surface of the capacitor electrode 8 is oxidized to form an insulating film 9 made of a silicon oxide film. Next, the dielectric film 7 exposed from the field insulating film 2 and the insulating film 9 is removed to expose the surface of the semiconductor substrate 1. The exposed surface of the semiconductor substrate 1 is oxidized again to form a gate insulating film 1o made of a silicon oxide film.Next, a polycrystalline silicon film is formed on the entire surface of the semiconductor substrate 1 by, for example, CVD, and this polycrystalline silicon film is The silicon film is patterned by etching using a mask made of a resist film to form gate electrodes 11 and word lines WL. Note that the gate electrode 11 and the word line WL are
It may be formed of a high melting point metal film such as O, W, Ta, or Ti or a silicide film thereof, or a two-layer film in which the high melting point metal film or high melting point silicide film is laminated on a polycrystalline silicon film. You can also use it as

Next, as shown in FIG. 9, using the gate electrode 11 as a mask for ion implantation, an N-type impurity such as phosphorus (P) is introduced into the surface of the semiconductor substrate l to form an n-type impurity that is part of the source and drain regions. Forming the semiconductor region 12 Next, a silicon oxide layer is formed on the entire surface of the semiconductor substrate 1 by, for example, CVD, and this silicon oxide film is etched by RIE to expose the surface of the semiconductor substrate 1.
A side wall spacer 14 is formed. In addition, the above R
Since the gate insulating film 10 is removed during IE and the semiconductor substrate 1 is exposed, the surface of the semiconductor substrate 1 is oxidized and a silicon oxide film 10 is formed on the exposed surface. next,
Gate? ? Using the poles 11 and sidewall spacers 14 as masks, N-type impurities such as arsenic (As) are introduced into the surface of the semiconductor substrate 1 by ion implantation to form sources,
An n-type semiconductor region 13, which is a part of the drain region, is formed.

Next, as shown in FIG. 10, phosphosilicate glass (P S
G) Form an insulating film 15 made of a film.

Next, the insulating film 15 on the n-type semiconductor region 13, which is a part of the drain region during reading of the memory cell, is selectively removed to form a contact hole 16.

Next, an aluminum film is formed on the entire surface of the semiconductor substrate 1 by sputtering, for example, and this aluminum film is patterned by etching using a mask made of a resist film to form data lines DL. Thereafter, although not shown, a PSG film is formed as a protective film by, for example, CVD, and a silicon nitride film is further laminated by, for example, by plasma CVD, thereby completing the manufacturing process of this embodiment.

[Example ■]

FIG. 12 is a schematic diagram of a high-pressure reactor for forming the silicon oxide film 7A, silicon nitride film 7B, and silicon oxide film 7C that constitute the dielectric film 7.

In Example 2, the silicon oxide film 7A is formed by oxidizing the surface of the semiconductor substrate 1, and the silicon nitride film 7B is formed by direct nitriding of the surface of the silicon oxide film 7A.
The silicon film 7C is formed by oxidizing the surface of the silicon nitride film 7B.

By forming the respective films 7A, 7B, and 7C at high pressure in this way, the formation time of the dielectric film 7 can be shortened,
More silicon nitride I! We are trying to reduce pinholes in j17B.

In FIG. 12, 23 is an outer frame container in which a quartz tube 17 is provided. 24 is a pressurizing gas introduction pipe, through which N2, which is pressurizing gas, is introduced into the outer frame container 2.
It will be introduced within 3. 25 is a closing lid of the outer frame container 23, and 26 is a cold trap. 19A is the quartz tube 1 for the reaction gas.
An introduction pipe 19B is used to introduce the carrier gas into the carrier gas.

The silicon oxide film 6 shown in FIG. 2 is formed using either the reaction gas 4:02.02+HC1 or N20 as in Example I, and for example, N2 is introduced as a carrier gas. The pressure inside the quartz tube 17 and the pressure inside the outer frame container 23 are between 4 and 8.
Adjust to atmospheric pressure (ATM).

The temperature inside the furnace 17 is set to about 700 to 1000°C.

By oxidizing the surface of the semiconductor substrate l under high pressure in this manner, the growth rate of the silicon oxide film 6 can be increased. The silicon oxide film 7A is later directly nitrided to form a silicon nitride film 7B.
Since a part of the silicon oxide film 7C is oxidized,
The film thickness is formed so that the silicon nitride film 7B and silicon oxide film 7C can be formed.

The silicon nitride film 7B is made of NH3 or N2 in the furnace 17.
The silicon oxide film 7A is formed by directly nitriding the surface of the silicon oxide film 7A. The temperature inside the furnace 17 is 1000-1200℃
exposed to high temperatures.

In forming the silicon nitride film 7B by direct nitriding, a reaction always occurs on the surface of the silicon oxide film 7A. That is, a new silicon nitride film 7B is formed while being covered with the already formed silicon nitride film 7B. Therefore, contaminants in the silicon nitride film 7B can be reduced, and the dielectric breakdown voltage of the dielectric film 7 can be improved. Further, the silicon nitride film 7B formed by direct nitridation is denser than the silicon nitride film 7B formed by deposition, and pinholes are reduced. Therefore, the dielectric strength voltage of the dielectric film 7 can be further improved.

The silicon oxide film 7C shown in FIG. 4 is formed by oxidizing at a temperature of about 700 to 1000° C. with the pressure in the furnace 17 at 4 to 8 &t rrt.

By forming by high pressure oxidation, the time required to form the silicon oxide film 7C can be reduced.

[Example ■]

FIG. 13 is a schematic diagram of a cold wall type reactor used for forming the dielectric film 7 of Example (2).

In FIG. 13, 27 is an infrared lamp, and this lamp 27 heats the wafer 1 to a temperature necessary for forming the films 7A, 7B, and 7C. The method of forming these films 7A, 7B, and 7C is the same as the method of Example 1, so the explanation will be omitted.

By using infrared heating, the quartz container 17 is not heated, so generation of gas from the furnace 17 can be prevented. Thereby, contaminants in the silicon oxide film 7A, the silicon nitride film 7B, and the silicon oxide film 7C can be reduced. Therefore, the reliability of the dielectric film 7 can be improved.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

For example, the silicon oxide film 7A is omitted and the dielectric film 7 is
It may be a two-layered film consisting of a silicon nitride film 7B formed on the surface of the substrate 1 by CVD or direct nitridation of the substrate 1, and a silicon oxide film 7C formed by oxidizing the silicon nitride film 7B.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, by forming the lower silicon oxide film, silicon nitride film, and upper silicon oxide film that make up the dielectric film in the same process in the same manufacturing equipment, the time required to manufacture the dielectric film can be reduced. can do.

Furthermore, since each film can be formed without removing the wafer from the manufacturing equipment, contaminants on the dielectric film can be reduced, and the reliability of the semiconductor integrated circuit device can therefore be improved.

[Brief explanation of the drawing]

1 to 10 are cross-sectional views of a memory cell in a DRAM manufacturing process. FIG. 11 is a schematic diagram of the reactor used to form the dielectric film of Example I, FIG. 12 is a schematic diagram of the reactor used to form the dielectric film of Example FIG. 2 is a schematic diagram of a reaction furnace used for forming a dielectric film in Example (2). l...Semiconductor substrate, 2...Field Me film, 3.
...Channel stopper region, 4... Base silicon oxide film, 5... Etching mask (SiO2), 6... Groove, 7A, 7C... Silicon oxide film, 7B... Silicon nitride film, 7... ...Dielectric film, 8... Capacitive electrode, 9.
14.15... Insulating film, 10... Gate insulating film, 1
1. Gate? ! ! pole, 12.13... semiconductor region,
16... Connection hole, WL... Word line, DL... Data line, 17... Quartz tube. 18...Closing lid, 19.19A, 19B...Introduction pipe,
20... Susceptor, 21... Heating coil, 22...
...Exhaust pipe, 23...Outer frame container, 24...Introduction pipe for pressurization, 25...Outer frame lid, 26...Cold trap, 27...Infrared lamp. Agent Patent Attorney Katsuma Ogawa Figure 2 Figure 5 Figure 6 Figure 7 Figure 8 Figure 12 Figure 2C

Claims (1)

[Scope of Claims] 1. A method for manufacturing a semiconductor integrated circuit device, characterized in that each of a three-layer film or a two-layer film constituting a dielectric film of a capacitive element is formed in the same manufacturing apparatus. 2. The three-layer film includes a silicon oxide film formed by oxidizing the surface of a semiconductor substrate, and a silicon nitride film formed by directly nitriding a part of the silicon oxide film, or on the silicon oxide film. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, comprising a deposited silicon nitride film and a silicon oxide film formed by oxidizing the surface of the silicon nitride film. 3. A patent characterized in that the two-layer film consists of a silicon nitride film deposited on a semiconductor substrate or a polycrystalline silicon film, and a silicon oxide film formed by oxidizing the surface of the silicon nitride film. A method for manufacturing a semiconductor integrated circuit device according to claim 1. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the capacitive element is a capacitive element of a memory cell of a dynamic random access memory.