JPS62298096A - Eeprom device - Google Patents

Abstract

PURPOSE:To set an optimum elimination and writing time in accordance with the process variance of a memory element by making variable a reference time which comes to be the reference of a deleting action and a writing action. CONSTITUTION:From NOR gate circuits G1-G5 to which reference frequencies F1-F4 frequency-divided by a frequency dividing circuit DV are supplied, a reference time signal F is outputted. The signal F is counted by a counter circuit CT and the output signal is supplied to a timing generating circuit TG. The generating circuit TG generates various types of the control signal in accordance with respective action modes. Here, by changing a frequency dividing ratio at the frequency dividing circuit DV, the reference time signal outputted from a counter circuit CT can be made variable. Consequently, the optimum deleting and writing time in accordance with the process variance of a memory element to form the memory array can be set.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Field of Industrial Application] This invention relates to an EEPROM (Electrically Erasable Programmable Read-Only) device. , a first write mode in which the information of the selected memory cell is once read out and held in the latch circuit, and the data to be written is supplied to the latch circuit, and then the memory cell is erased and held in the latch circuit. The present invention relates to a technique that is effective for use in eleven EEPROM devices having a second write mode in which data is written into a memory cell using a written write signal.

[Conventional technology]

Semiconductor non-volatile memory elements, such as MNOS (Metal Nitride Oxide Semiconductor), in which data can be written and erased electrically, consist of a relatively thin silicon oxide film and a relatively thick silicon nitride film formed thereon. Insulated gate field effect transistors (hereinafter referred to as MNOS in cars) have a two-layer gate insulating film structure with
(referred to as a transistor), and can electrically perform not only writing but also erasing of stored information. The MNOS technology is described in, for example, Japanese Patent Application Laid-Open No. 56-156370.

In an erased state or in a state in which no stored information is written, the threshold voltage of the N-channel type MNOS transistor is a negative voltage. In order to write or erase stored information, a high electric field is applied to the gate insulating film so that carrier injection occurs due to a tunneling phenomenon.

According to the above publication, the MNOS (MNOS) transistor is formed in a P-type well region formed in an N-type semiconductor substrate. Furthermore, MOSFETs constituting the peripheral circuit are formed in a well region that is independent of the well region for the MNOS transistor.

In a write operation, for example, O, which is the ground potential of the \' circuit, is applied to the well region serving as the base gate of the MNOS transistor, and a high voltage for writing is applied to the gate. In the source region and drain region,
Depending on the information to be written, a low voltage of vQ■ or a high voltage of the write level is applied. At this time, a channel is induced in the channel forming region of the MNOS transistor, that is, in the surface of the silicon region between the source region and the drain region, in response to the positive high voltage of the gate. The potential of this channel becomes equal to the potential of the source and drain regions. When a voltage of 0 is applied to the source region and the drain region as described above, a high electric field corresponding to the high voltage of the gate acts on the gate insulating film. As a result, electrons as carriers are injected from the channel into the gate insulating film due to a tunneling phenomenon. This allows M.N.O.
The threshold voltage of S changes, for example, from a negative voltage to a positive voltage.

When a high voltage at a write level is applied to the source region and the drain region, the potential difference between the gate and the channel is reduced to a small value. Such a small voltage difference is insufficient to cause electron injection by tunneling. Therefore, the threshold voltage of MNOS does not change.

In addition, in the case of erasing, a positive high voltage is applied to the well region serving as the substrate gate while applying O to the gate of the MNOS transistor to cause a tunneling phenomenon in the reverse direction and transfer electrons as carriers to the substrate. This is done by returning it to the gate.

[Point J while the invention is trying to solve]

Prior to this invention, the present inventors discovered that EEPROM
In order to simplify rewriting, when the write mode is instructed, the memory information of the selected memory cell is read out and loaded into the latch circuit, the data to be rewritten is supplied to the latch circuit, and the erase operation of the memory cell is performed. We have developed an automatic writing method that performs writing according to the information held in the latch circuit. Each such sequence of operating steps is managed by a time signal formed by a timer circuit receiving a reference time signal.

However, the time required for erasing and writing operations of MNO3I-transistors has relatively large process variations. Therefore, setting a fixed time will stop memory cells from being under-erased or under-written. Yield will be poor. Therefore, if a sufficient time is set assuming the above worst case, the operation speed will be slowed down and an excessively high voltage for erase or write operation will be applied to the MNOS transistor. A bottom occurs which deteriorates the device characteristics.

SUMMARY OF THE INVENTION An object of the present invention is to provide an EEPROM device in which erasing and writing times can be set optimally depending on process variations.

The above and other objects and novel features of this invention include:
This light! It will become clear from the description of Book II and the attached drawings.

[Means for solving problems]

A brief summary of representative inventions disclosed in Book +1 is as follows.

That is, when the write mode is signaled, the first step is to read the memory information of the selected memory cell and hold it in the latch circuit, the second step is to supply the rewritten data to the latch circuit, and the second step is to read the stored information of the selected memory cell and hold it in the latch circuit. An EEPROM device that performs a third step of performing an erasing operation and an eleventh step of writing rewritten data held in the latch circuit into a memory cell in a chronological manner, in which the times of the erasing step and the writing step are made variable. It is.

[For production]

According to the above-described means, it is possible to set the optimum erase time and write time according to the process variation of the memory element.

〔Example〕

FIG. 3 shows a circuit diagram of a main part of an embodiment of the Snake EFROM device according to the present invention.

The EEFROM device of this embodiment includes an address buffer (not shown), an X decoder X-DCR, and a Y decoder Y-D.
An address selection circuit consisting of a CR, a circuit for forming voltages for write/erase operations in response to output signals and control signals of this address selection circuit, and the above-mentioned system. It includes a control circuit C0NT that forms the II signal.

EEPROM=ff is not particularly limited, but may be a relatively low power supply voltage V such as +5■ supplied from the outside.
cc and a high negative voltage -Vl)I) such as -12■. The X address decoder X-DCR and the like constituting the selection circuit are constituted by a CMO5 circuit. The 0M03 circuit operates by being supplied with a relatively low voltage Vcc such as +5v.

Therefore, address decoders X-DCR and Y-DC
The level of the selection/non-selection signal formed by R is V
The low level is O of the ground potential of the V circuit.
■ be made into.

Although the element structure itself constituting the illustrated EEPROM device is not shown because it is not directly related to the present invention, its outline is as follows.

That is, the entire illustrated device is formed on a semiconductor substrate, such as one made of N-type single crystal silicon.

The M N OS transistor is of an N-channel type, and is formed on a P-type well region or a P-type nest three body region formed on the surface of the semiconductor substrate. The N-channel MOSFET is similarly formed on P-type semiconductor 9M clay.

A P-channel type MOS FET is formed on the semiconductor substrate.

One memory cell can be one MN, although it is not particularly limited.
OS transistor and two MOs connected in series with it
It is composed of SFE'l'. In one memory cell, one MNOS) transistor and two MOSFE
T is the gate ia of the transistor, e.g.
This is a so-called stacked gate construction in which a part of the gate electrode of each of the two MOSFETs is oversubbed for each of the two MOSFETs i. As a result, the size of the memory cell is reduced because one MNOS transistor and two MOS FETs constituting the memory cell are substantially integrated into one structure.

Although not particularly limited, each memory cell is formed in a common well region. 0M like X decoder, Y decoder
The N-channel MOSFET for configuring the 03 circuit is formed in a P-type well region that is independent from a common P-type well region for each memory cell.

In this structure, the N-type semiconductor substrate constitutes a round base gate for a plurality of P-channel MOS FETs formed thereon, and is set to the power supply voltage Vcc level of the circuit. N channel M for configuring 0M03 circuit
The well region as the body gate of the OSFET is maintained at circuit ground potential O volts.

In FIG. 3, memory array M-ARY includes a plurality of memory cells arranged in a matrix. One memory cell consists of an MNOS transistor Q2, its drain and a data line (focus gland or digit, J)D.
MO3FET QI for address selection provided between
Although not specifically mentioned, the isolation MNO3FET Q3 is provided between the source of the transistor Q2 and the common source line. Note that when the stacked gate structure as described above is adopted, the MNO
MO3FE is placed in the channel formation region of S transistor Q2.
The channel forming regions of TQI and Q3 are directly adjacent to each other. Therefore, M N03I transistor Q
It should be understood that the drain and source of 2 are terms of convenience.

The gates of the address selection MO3FETQ1, etc. of the memory cells arranged in the same row are connected to the first word line W.
The gates of the MNOS transistors Q2 and the like that are commonly connected to the second word line W12 are commonly connected to the second word line W12. Similarly, the gates of the memory cell address selection MO3FET and MNOS transistors arranged in the same row are connected to the first word line W21. 'rV
22 in common.

MO for selecting addresses of memory cells arranged in the same column
The drains of the 3FETQ1 and the like are commonly connected to the data line D1. Similarly, the drains of the address selection MO3FETs of other memory cells arranged in the same column are commonly connected to the data line D2.

Isolation MOS FET Q in each memory cell
The sources of No. 3 are shared and constitute a common source line C8.

The memory array M-ARY of this embodiment is operated by the following potential.

First, in a read operation, the potential Vw of the well region WELL is set to a low level equal to the ground potential O volts of the circuit. The common source line C8 is set to a low level substantially equal to the ground potential by MO3FF for 0 isolation, TQ
The control line connected to the gate of 3 is connected to these MO3F
The beam t source voltage Vc is set so that ETQ3 is turned on.
is set to a high level equal to c. Each M.N.O.
The second word lines W12 to W22 coupled to the gate electrodes of the S transistors are at a potential equal to the ground potential, i.e., a voltage between the high and low threshold voltages of the MNOS transistors. It is said that The word line to be selected from among the first word lines Wll to W21 is set to a selection level equal to the power supply voltage Vcc or to a high level, and the remaining word lines, that is, unselected word lines are grounded. It is set to a non-select level or low level equal to the potential. Data IDI or D2
A sense current is supplied to the data line to be selected. If the MNOS transistor in the memory cell selected by the first word line has a low threshold voltage, that memory cell forms a current path to the data line to which it is coupled. If the M N OS transistor in a selected memory cell has a high threshold voltage, that memory cell forms substantially no current path, and therefore reading data in the memory cell is done by sensing the sense current. It's done.

In the write operation, the well region WELL is V-
A negative high voltage equal to Vpp is applied to the isolation MO3.
The control lines coupled to the gate electrodes of FETs Q3 are brought to a high negative potential to turn those MO3FETs Q3 off. The first words KILL to W21 are set to a non-selection level or low level equal to the ground potential.

One of the second word lines W12 to W22 is brought to a selection level such that y' is equal to the power supply voltage Vcc, and the remaining second word lines are brought to a high negative voltage close to the voltage -VPI). be done. The data line is set to a high level equal to the power supply voltage Vcc or to a low level with a high negative voltage close to the negative voltage -vpp, depending on the data to be written into the memory cell.

In the erase operation, the well region WELL and the common source line C8 are set to an erase level equal to the power supply voltage Vcc or to a high level. The first word lines Wll to W21 and the second word lines W12 to W22 are
For erasing, basically each circuit's power supply voltage Vc
c is equal to 1' and is at a level substantially equal to the voltage -vpp. However, according to this embodiment, the levels of the first and second word lines are determined so that erasing of memory cells in each memory row is possible, although this is not particularly limited. Among the first words vAW11 to W21, the first word line corresponding to the memory row that requires erasing is set to an erase level equal to the power supply voltage Vcc, and the first word line corresponding to the memory row that does not require erasing is set to the erase level equal to the power supply voltage Vcc. The first
The word line is brought to a non-erasing level, such as y' circuit ground potential. Of the second word lines W12 to W22, the second word line corresponding to the first word line set to the erase level is set to the erase level equal to the negative voltage -vpp, and is set to the non-erase level. The second word line corresponding to the first word line is set to a non-erasing level equal to the power supply voltage Vcc.

According to this embodiment, the power supply voltage Vcc is applied to the well region (ie, MNOS) transistor substrate gate as described above.
A configuration is adopted in which the information stored in each MNO3) transistor is erased by applying this voltage.

On the other hand, the N-channel MO3FE that constitutes the CMO3 circuit
The body gate of T is required to be brought to a potential, such as 0 ports, independently of the body gate of the MNOS transistor. Therefore, as mentioned above, the base gate of each memory cell, i.e., memory array M −,a,
The semi-quadramid head area WELL where RY is formed is an X decoder,
N-channel MOS that constitutes peripheral circuits such as Y decoder
It is electrically isolated from the inter-semiconductor region (well region) where the FET is formed.

If you want to enable partial erasure of the memory array M-ARY, you can form each memory cell in an independent well region, or form memory cells arranged in the same row or column in a common well region. You can do it. In this embodiment, the entirety of the memory cells, ie, the memory array M-ARY, is formed in one common well area WELL, as described above.

The first and second words 'g, W11 to W21 and W
12 to W22 are respectively decoded by the X-decoder X-0CR. Although not particularly limited, the X-decoder X-DCR consists of a plurality of unit decoder circuits in one-to-one correspondence with the memory rows of the memory array M-ARY. One unit decoder circuit is composed of, for example, a NOR gate circuit N0R1 that receives an address signal, a gate circuit G, and a level conversion circuit LVC as shown in the figure.

At least during the read operation, the gate circuit G
The output of the corresponding NOR gate circuit is
The first word line is transmitted to the word line, and the first word line is made to have a level substantially equal to the ground potential of the circuit in a write operation, regardless of the output of the corresponding NOR gate circuit. According to this embodiment, in order to enable the selective erase operation described above, the gate circuit G connects the output of the corresponding NOR gate circuit to the corresponding first word line during the read operation as well as during the erase operation. configured to transmit.

During a write operation, if the output of the corresponding NOR gate circuit is at a high selection level, the level conversion circuit LVC changes the second word line to a selection level equal to the power supply voltage Vcc in response to the output of the NOR gate circuit. If it is a low non-selection level, the second word line is accordingly set to a non-selection level equal to the negative voltage -VGIP. During the erase operation, the level conversion circuit LVC also changes the second word line to an erase selection level equal to negative voltage -VpI, if the output of the corresponding NOR gate circuit is at a high selection level; If the output of the NOR gate circuit is at a low non-selection level, the second word line is accordingly set to an erase non-selection level equal to the power supply voltage Vcc.

The gates of the isolation MO3FETQ3 etc. are controlled by the control voltage generation circuit Vig-G. It is commonly coupled to the control line to which the II voltage ■ig is supplied. These separation M
The sources of O3FETQ3 and the like are each shared to form a common source 'gAcs.

Control voltage Vi supplied to the separation MO5FETQ3
In the write operation to the MNOS transistor, which will be described later, the word line connected to the memory cell to be selected among the second word lines W21 and W22 is set to a high level (5■), and g is used as a base gate. When the well region WELL is set to about -12 µ and the data line, for example, Dl is set to about -10 µ, the MO3FET
A low potential, such as about -10V, is applied to turn Q3 off. As a result, even if the data line D2 is +5y
Even if the data line D2 is set to a high level, current is prevented from flowing from the data line D2 to the memory cell to which the above writing is to be performed.

The common source line CS is coupled to an output terminal of a common source line drive circuit DVR.

Basically, the drive circuit DVR can drive the common source line C8 to the power supply voltage Vcc level during the erase operation, and can drive the common source line Cs to the level of the power supply voltage Vcc during the read operation.
“It is sufficient to have an output characteristic that can be driven to the ground potential of the circuit.As a result, when the well region WELL is brought to the power supply voltage Vcc level in the erase operation,
It is possible to prevent the junction between the electrode coupled to the common source line C3 of MO5FETQ3 and the well region WELL from being biased in the forward direction. Furthermore, a current path required for a read operation can be formed between the common source line C8 and the ground point of the circuit.

The drive circuit DVR is not particularly limited, but as shown in FIG. MOS connected in parallel between
It consists of FET Q7 and QB, and a CMOS inverter circuit IV.

MO3FETQ above? , Q8 has a control signal e
r is supplied, and the control signal er is inverted by an inverter circuit IV and supplied to the gate of MO3FETQ6. As a result, the above MO3FETQ7. Q8 and QB are turned on/off in a complementary manner depending on the level of the control signal er. The control signal er is basically:
In order to turn on the MO3FET Q6 and turn on the MOSFET Q7 and QB during the erase operation, the voltage is set to a high level equal to the voltage VCC, and during the read and write operations. , is set to a low level equal to so 0 port. According to this embodiment, the control signal er is the well region W
In order to prevent the PN junction formed by the MOS FET etc. formed in the E L from being put into a forward bias state, its output timing is controlled in accordance with the timing of change in the potential of the well region. .

According to this embodiment, the second word vAW12. MO3FETQ is connected between W22 and the common source %IC3, respectively.
, 1. Q5 is provided. These MOS F
E T Q 4 and Q 5 are control signals e r /
It is switch controlled by w e. Although not particularly limited, the control signal er/'we may have a high level of y°.
The voltage nB is set to a level equal to the voltage VCC, and its low level is set to a level equal to the ground potential.

MO3FETQ4. Q5 is the second word line W12°W2
It is made into a P-channel type so that it can be turned off well even when a negative potential is applied to 2.

Switch 2-chi MO3FETQ4. During a read operation, transistors Q5 and the like are turned on so as to short-circuit the gates of the MNOS transistors Q2 and the common source line CS so that they are at the same potential. These switches MO3FETQ4. Q
5 is provided between each second word line and the common source line C8 for the following reason.

That is, MO3FETQ in the drive circuit DVR? ,
QB is turned on by setting the control signal er to a low level equal to QQ volts during a read operation. In this case, MO3FETQ7. The QBs have a non-negligible on-resistance even though they are connected in parallel as shown. As a result, the common source line C8 is
The electric current that flows through it during reading causes its potential to rise. Especially MO3FETQ? , QB consists of P-channel type, these MO3FETQ? .

Since QB does not have the driving ability to change the common source line C8 to the ground potential of the circuit, the common source line vA
The amount of rise in the potential of cs becomes large (that is, M
O3FETQ? , Q8 is the common source line C in it
A current transfer electrode coupled to memory array M-AR
Since it acts as a source electrode for the positive potential applied via Y and the common source line C3, when the common source line C8 reaches a potential equal to or lower than the respective threshold voltages, it is substantially turned off. . Such a rise in the potential of the common source line C8 causes an increase in the effective threshold voltage of the MNOS transistor due to the substrate effect 7, and reduces the conductance of the MNOS transistor, which should have a low threshold voltage.

In other words, the read current flowing through the MNOS transistor with a low threshold voltage is reduced. The above shorted MO3FETQ4. Q5 is connected to each second
Word VAW12. The potential of W22 is made substantially equal to the potential of the common source gcs, thereby making the potential of MNOS (MNOS)
This prevents an increase in the effective threshold 4iff voltage of the transistor.

Well region W where the memory array M-ARY is formed
A control voltage Vw-G generated by a control voltage generation circuit Vw-G is supplied to ELL.

This voltage Vw is set to a negative high voltage of about -12 .quadrature. during a write operation, to a potential of about +5 .mu. during an erase operation, and to about 0.degree. at other times.

In this embodiment, in order to speed up the read operation,
Each data mD1 and D2 of memory array M-ARY has
Connect data lines DI and D2 to column switch MO3FETQ9
．． N-channel/l/MOS electrically isolated from QIO
FETQ 11 and Q 12 are provided. That is, each of the data lines Di, D2, etc. and the common data line CD
Between the above MO3FETQI 1. Ql 2 etc. and N-channel MO3FET QQ9 as Y gate (column switch) circuit C-5W. QIO, etc. are provided in series. MO3FET for the above data line separation
Q11 and Ql2 are the same P as the above MNO3) transistor.
It is formed in the well region WELL of the mold. These MO3
FETQI 1. A control voltage Vc generated by a control voltage generation circuit Vc-G is supplied to the gate of Ql2. This system'aT! The X voltage Vc is set to a negative high voltage such as -12V only in the write operation state, and in other read and erase operation states, the tRT1 voltage V
It is set to a high level like CC. As a result, the MO3FETs Qll and Q12 are turned off during the write operation state. In addition, the above MO3FETQI
1°Ql2 is the well region WE in the erase operation state.
It is turned off by setting LL to a high level such as tBTL pressure Vcc. Therefore, the above MO3FE
TQI 1. Ql 2 is turned on only during read operation conditions. As a result, during the write operation, the MO3FE'l'Q11°Ql2, etc. are turned off, so even if the potential of the data line is set to a negative high voltage, the column switches MO3FETQ9. The connection point with QIO is placed in a floating state. This causes the switch MO3FETQ9. to be coupled to the interconnection point.
It is possible to prevent the source and drain of Q10 and the well region in which they are formed from being forward biased.

MO3FE constituting the above column switch circuit C-5W
TQ9. The output signal of the Y-decoder Y-DCR is supplied to the gate of QIO. During a read operation, each output of the Y-decoder Y-DCR is set to a selection level equal to the y't'a voltage Vcc or a non-selection level equal to QQ volts.

The common data line CD is connected to the output terminal of the data input circuit DIB constituting the input/output circuit 10B and the sense amplifier SA.
and an output sofa circuit OBC.
It is coupled to the input terminal of OB. This input output circuit 1
The input terminal of the data input circuit and the output terminal of the data output circuit constituting 0B are coupled to the external terminal I10.

According to this embodiment, each data line D1. D2 is provided with a latch circuit FF for holding previous memory information +V prior to erasing/writing, and selectively changes the potential of the data line to a negative high level according to the stored information of the latch circuit FF during write operation. A level converter circuit LVC is provided to change the voltage to -Vl). These enable an automatic rewriting operation as described below and simultaneous writing of data into a plurality of memory cells coupled to one selected word line.

Chip enable signal, write enable signal, output enable signal and external terminal vp supplied to E
Various operation modes are determined by receiving the write voltage supplied to the gate circuit G, the level conversion circuit LVC1, the control voltage generation circuit Vig-G, and the drive circuit DV.
It outputs various control signals for controlling the operations of circuits such as R, data input circuit DIB, and data output circuit DOB.

Although not particularly limited, read operation modes include CE, W
The standby operation mode is indicated by the high level of the signal CE. The first write operation mode for writing data into the latch circuit FF shown in FIG. ,
It is indicated by the low level, low level, high level, and high level of OE and Vpp.

The erase operation mode is instructed for a predetermined period when the second write operation mode is instructed.

According to this embodiment, various control signals outputted from the 1tIII control circuit C0NT are outputted in time series. The oscillator circuit OSC of FIG. 1 is operated by a power supply voltage Vcc, such as +5 volts, applied between the external terminal Vcc of the EEPROM device and GND. In addition, the oscillation circuit O
3C may be controlled, for example, to be activated only when a write voltage is applied to terminal vpp, if necessary for low power consumption of the circuit.

Next, the second write operation mode of this embodiment circuit will be explained according to the timing diagram shown in the second depression.

When rewriting data, a first write mode (not shown) is performed prior to the second write mode.

That is, in the first write mode, the stored information of all the memory cells coupled to the word line designated by the address is once read out and held in each latch circuit FF shown in FIG. 1. Then, the data signal supplied from the external terminal is taken into the latch circuit corresponding to the data line of the memory cell to be written. For example, when replacing all bits of a memory cell connected to a word line, Y
By sequentially switching the addresses, write signals made up of a plurality of bits supplied from external terminals are sequentially taken into the corresponding latch circuits.

After this, the second write mode as shown in the figure is implemented. An erase operation of the M N OS transistor coupled to the word line is performed, after which the latch circuit F
A write operation similar to that of a static RAM can be performed from the outside by 0 or more operations in which a write operation is simultaneously performed on one word line of memory cells according to the information of F.

In the second write mode indicated by the low level, low level, high level, and high level of , the control signal EW is changed from low level to high level. Each internal signal 7rXert, erts changes from high level to low level with a predetermined time difference from the rise of signal EW to high level. Due to the low level of the internal signal Or (high/high level of er),
Since MO3F and ETQ6 in the drive circuit DVR of FIG. 1 are turned on, the common source line C3 of the memory array M-ARY is set to a high level such as +5. Due to the time difference between the internal signals er and art, the reset signal cr is temporarily set to a low level from +5■ to -4■. As a result, the output terminals (word line W12, etc.) of the level conversion circuit LVC are reset to the grounded state, and then set to a low level (0■) in a floating state.
Further, due to the time difference between the internal signals er and erts, the reset signal cu is temporarily set to a low level from +5V to -4V. As a result, the same centrifugal operation as described above is performed for a load having a relatively large parasitic capacity such as a well WELL or an isolation MOS FET.

The low level of the internal signal ert causes the X decoder X-DCR to start its level changing operation. for example,
The selected second word line, in other words, the MNO3F transistor to be erased, the gate potential of the transistor is lowered to a negative high voltage such as about -IOV, as described above. Note that the word line to be unselected, in other words, the gate voltage of the MNOS (MNOS) Ranjisk whose erase operation is prohibited, is set to a high level such as +5■, although not shown, as is clear from the above operation description. .

Thereafter, the control voltage generating circuit Vw-G, which forms the drive voltage for the base gate of the memory array M-ARY, in other words, the well region WELL, uses the low level of the internal signal arts to raise the voltage Vw to a high level such as +5■. level.

This allows the MNOS to be coupled to the selected word line.
) As a result of supplying a negative high voltage between the gate of the transistor and the base gate, the information charge taken into the floating gate is returned to the base gate by the tunnel effect caused by the high electric field. Note that since the gate of the MNOS transistor connected to the unselected word line and the base gate are set to the same potential, their erasure is not performed, and at the end of the erasure, the internal signals erts, ert, and er are In this way, in the reverse order of the start of erasing, each level is changed from a low level to a high level with a time difference. Accordingly, the well region WELL, the second word line, and the data line are restored to their original states in this order. Further, reset signals cr, cu, and cw are formed by the internal signals. In the above operation timing, the P-type well region WELL is raised to a high level such as the power supply voltage Vcc at the end at the start of erasing, and is lowered first at the end of the erasure.
Address selection MO formed in the well region WELL
The PN junction between the N-type drain and source of the 3FET or isolation MO3FET and the well region WELL can be maintained in a reverse bias state.

A write operation is subsequently performed after the above erase operation.

The internal signals we' and wets are sequentially changed from high level to low level with a time difference.

Due to the low level of the internal signal .tau., the control voltage generating circuit Vw-G makes the voltage Vw a negative high voltage such as -12.times.-Vpl). As a result, first, the well region WELL where the memory 7 array M-ARY is formed is lowered to a negative high voltage -vpp. In synchronization with this, the control voltage generation circuit Vig-G also changes its voltage Vig to about -12
Make it a negative high voltage such as V. As a result, each isolation MO3FET of the memory cell is turned off. Similarly, the voltage Vc is also set to a negative high voltage such as -12V as mentioned above. As a result, the data line separation switch M
O3FET QI 1, Q12, etc. are turned off. Furthermore, due to the low level of the internal signal we', the gate circuit G of the X decoder
and unselected word lines are brought to the ground potential (OV) of the circuit (not shown).

Next, in synchronization with the low level of the internal signal V/e ts, the X-decoder X-DCR sets the selected second word line to high level (+5 V) and sets the non-selected word line to low level. . In response to the high level and low level, the level conversion circuit LVC changes the second word line to a high level such as +5■ if the selection signal is at a high level, and changes the second word line to a high level such as +5■ if the selection signal is at a low level (not shown). Set the word line to a negative high voltage such as -10V. In addition, the low-bell conversion circuit L V C coupled to each data line is activated, and according to the stored information of the corresponding latch circuit FF, if it falls down, the logic “lo” is written.
A negative high voltage such as ■ is applied, and those to which logic “0°” is written (write prohibited) are made to a high level such as approximately +5■. Therefore, M to which logic “1” is written
The gate voltage of the transistor (NOS) is approximately +5■, and the voltage of its base gate (well region WELLL) is approximately -
12V, and the drain (data 15) voltage is approximately -10V
Therefore, a high electric field of about 15 V acts between the channel and the gate electrode in the base gate, and electrons are injected by the tunnel effect. On the other hand, in the MNOS transistor to which the logic "0" is written, the drain voltage is set to approximately +5.degree., so that no high voltage is applied between the gate and the channel, so that the electrons are not injected.

At the end of the write operation, each internal signal; e t
Like s and we', they are changed from low level to high level with a time difference in the reverse order from the start. Accordingly, the data line, second word gland, and well region are restored to their original state in this order. Further, reset signals cr, cu, and cw are formed by the internal signals. In the above operation timing, at the start, the P-type well region WELL is first lowered to a negative high voltage, and at the end, the voltage is lowered to 10 at the end. MO3FET for address selection and MO3FET for isolation formed in the WELL
The PN junction between the N-type train and source of S FET and the well region WELL can be maintained in a reverse bias state.

Each M above? The fll signal is formed by the following circuits.

FIG. 1 shows a circuit diagram of an embodiment of the control circuit CONT, which is provided with the function of making the erase/write time variable.

The frequency of the haze output addressed to the oscillation circuit oscOD is divided by the frequency dividing circuit DV. In this embodiment, in order to be able to set the erasing and writing times to optimal times according to process variations in the memory element, the frequency dividing circuit DV provides
Four reference frequency (time) signals F1 to F4 having different frequencies (dividing ratios) are output. These four reference time signals F1 to F4 are respectively supplied to one input of NOR gate circuits G1 to G4 forming a multiplexer circuit.

The other input of these NOR gate circuits G1 to G4 is connected to a control signal CI generated by the next program circuit.
or C4 is supplied. In the figure, the control signal C1
A specific circuit of the program (memory circuit) Ml forming the is exemplarily shown.

In this embodiment, an MNOS transistor Qm is used as a storage element for the above time setting.

That is, the drain of the MNO3i-transistor Qm is coupled to the voltage iP1 via the resistor R2.

The electrode pi is coupled to a power supply voltage cc via a resistor R1. The gate of the M N OS ) transistor Qm is coupled to the voltage iP2, and the source is given the ground potential of the circuit. The gate is supplied with the ground potential of the circuit as a read bias voltage via a high resistance R3. The drain of the M N OS transistor Qm is coupled to the input terminal of the inverter circuit Nl, and the control signal C1 is output from its output terminal.

The other program circuits M2 to M4 are also constructed of circuits similar to the circuit M1 described above. The electrode PI is provided in common to each of the circuits M2 to M4. Further, gates P3 to P5 are provided at the gates of the MNOS transistors of each of the circuits M2 to M4, respectively.

As a result of the EEPROM probing test, when setting the reference time signal F1, a high voltage is supplied to the electrode P1 from the probe. A similar high voltage is supplied to the electrode P2, and the other electrodes P3 to P5 are set to a low level such as the ground potential of the circuit, or are set to a floating state. As a result, the channel of the MNOS transistor Qm of the program circuit M1 is induced in response to the high voltage being supplied to its gate. The potential of this channel becomes equal to the potential of the source and drain regions. When a voltage of O2 is applied to the source region and the drain region as described above, a high electric field corresponding to the high voltage of the gate acts on the gate insulating film.

As a result, electrons as carriers are injected from the channel into the gate insulating film due to a tunneling phenomenon. As a result, the threshold voltage of the MNOS transistor Qm is
For example, the voltage changes from a negative voltage to a positive voltage. The MNOS transistors of the other program circuits M2 to M4 are maintained at negative threshold voltages because no high voltage is applied to their gates.

In a normal operating state, the terminals P1 and R2 to R5 are supplied with the electric B voltage Vcc and the circuit ground potential via resistors R1 and R2, respectively. As a result, the ground potential of the circuit is applied to the gates of the MNOS transistors in each of the program circuits M1 to M4, and as a result, transistors with a positive threshold voltage are turned off, and those with a negative threshold voltage are turned off. Things are turned on. As a result, the drain voltage of the MNOS transistor which is turned off becomes a high level corresponding to the power supply voltage Vcc, and the drain voltage of the MNOS transistor which is turned on
The drain voltage of the OS transistor is set to a low level like the ground potential of the circuit.

Therefore, the signal C1 becomes low level (logic "0"),
No. i C2 to C4 are set to high level (logic "1"), and as a result, only the NOR gate circuit G1 opens its gate and transmits its input signal F1 to its output. The output signal of this NOR gate circuit G1 is outputted via the NOR gate circuit G5 because the output signals of the other NOR gate circuits G2 to G4 are fixed at a low level compared to the high level of the control signals C2 to C4.

When selecting another reference frequency signal F2, R3, or R4, it can be similarly realized by performing the above-mentioned write operation to the corresponding MNOS transistor.

The reference time signal F passed through the multiplexer circuit consisting of the NOR gate circuits G1 to G5 as described above is supplied to the counter circuit CT. The counter circuit counts the time signal F and sends the output signal to the timing generation circuit TG.
supply to.

The timing generation circuit TG identifies the operation mode out of the count output and generates various control signals corresponding to the operation mode according to the count output of the counter circuit CT, or in other words, the time signal, as described above. It is generated in chronological order.

In this embodiment, the time signal output from the counter circuit CT can be made variable by making it possible to change the substantial frequency division ratio in the frequency divider circuit DV that forms the reference time signal. As a result, memory array M-AR
Raw erasing and writing operations can be performed at the optimum time depending on the process variations of Y MNOS transistors.

The effects obtained from the above examples are as follows. That is, (1) In an EEPROM device in which erasing and writing operations are performed in time series according to the counting output of a reference time signal, by making the reference time variable, the erasing time and writing time can be made variable. Can be done. This provides the effect that it becomes possible to set the optimum erase time and write time according to the process variations of the MNOS transistor.

(2) According to (1) above, the occurrence of defects due to insufficient erasing and writing can be significantly reduced, resulting in the effect that product yield can be significantly improved.

(3) Due to (1) above, it is not necessary to perform erasing and writing with a time margin that takes into account process variations, so operation speed can be increased and deterioration of device characteristics due to excessive erasing and writing can be prevented. You can get the effect that you can.

(4) As the write operation mode, there is a first write mode in which reading is performed, the stored information before writing is held in the latch circuit, and rewrite information is set in the latch circuit, and By providing a second write mode in which the MNOS) transistor is erased and the MNOS) transistor is written for one word according to the information stored in the latch circuit, externally it looks like a RAM. The advantage is that the write operation can be performed under control.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the oscillation frequency of the oscillation circuit may be made variable to make the erase time and write time variable. Furthermore, a multiplexer circuit may be provided at the output of the counter circuit to make the output count value variable, thereby changing the timing of the control signal that defines the erase time and write time. The program circuit that forms the control signal for the multiplexer (gate circuit) that receives the oscillation frequency, the output signal of the frequency divider circuit, and the counter circuit as described above is performed by selectively cutting fuse means using a polysilicon layer, etc. It may be.

Further, the EEPROM device may be such that the first write operation and the second write operation are performed continuously and automatically by an appropriate sequence circuit provided in the control circuit C0NT, and each memory M for cell separation
The OS FET Q 3 may be omitted and the source of the MNOS transistor may be connected to the reference potential line. In this case, the reference potential line is placed in a floating state during write operations, and is applied with the ground potential of the circuit during read and erase operations.

Further, the electrically writable/erasable memory element may be of the FLOTOX (floating gate tunnel oxide) type.

When using such a memory element, its writing/
A control voltage corresponding to the erase operation is supplied.

The present invention is applicable to various EEPROMs, provided that the erase operation and the write operation are performed in a time-series manner by a control signal formed based on an internal time signal.
A wide range of equipment is available.

〔Effect of the invention〕

A brief explanation of the effects obtained by representative inventions among the inventions disclosed in this application is as follows. That is, an EEPROM in which erasing and writing operations are performed chronologically according to the counting output of the base wall time signal.
In the device, by making the reference time variable, the erasing time and writing time can be made variable, and it is possible to set the optimal erasing time and writing time according to the process variations of MNOS transistors. .

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of a control circuit in an EEPROM device according to the present invention, FIG. 2 is a timing diagram showing an example of erasing and writing operations thereof, and FIG. 3 is a circuit diagram showing an example of the control circuit in an EEPROM device according to the present invention. FIG. 2 is a circuit diagram of an embodiment of the main part of the device.

Claims (2)

[Claims] 1. A memory array including a semiconductor non-volatile memory element that can be electrically written and erased, a first step of reading storage information of a selected memory cell and holding it in a latch circuit, and supplying rewritten data to the latch circuit. The first write mode consists of a second step, the third step performs an erase operation on the selected memory cell, and the second write mode consists of a fourth step in which the rewritten data held in the latch circuit is written into the memory cell. An EEPROM device characterized in that the erasing step and writing step times are made variable. 2. The circuit that makes the time of the above operation step variable consists of a frequency divider circuit that divides the oscillation output of the oscillation circuit to form a plurality of reference time signals, and a frequency divider circuit that divides the oscillation output of the oscillation circuit to form a plurality of reference time signals, and a frequency divider circuit that divides the oscillation output of the oscillation circuit to form a plurality of reference time signals. It is characterized by comprising a multiplexer that outputs one of the plurality of reference time signals, and a timer circuit that counts the reference time signals supplied through the multiplexer and sets the time of each of the operation steps. EE described in claim 1
PROM device.