JPH08212792A - Semiconductor memory device - Google Patents

Abstract

PURPOSE: To obtain an EEPROM whose write time does not become longer even when the frequency of an oscillator drops due to a low voltage by providing the EEPROM with an oscillation circuit which supplies a clock to a timing generation circuit generating two or more kinds of erase/write timings according to an output signal from a power-supply voltage level detection circuit. CONSTITUTION: A power-supply voltage level detection circuit 11 outputs a signal CTL according to a power-supply voltage VCC. A timer 12, to which the signal CTL and an output OSC from an oscillation circuit 10 are input, frequency-divides the OSC so as to generate the write time IWT according to the CLT. Thereby, even when the frequency of the circuit 10 drops due to the change in power-supply voltage VCC, it is possible to prevent the write time IWT from becoming longer than required.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to an electrically erasable / writable nonvolatile semiconductor memory device (EEPROM).

[0002]

2. Description of the Related Art In an EEPROM, one cycle time for erasing / writing data to a memory cell (hereinafter referred to as "writing time IWT" or simply "IWT") is 10 m.
s is required. The EEPROM has a built-in oscillation circuit and a timer to automatically generate the IWT. The output OSC of the oscillation circuit is supplied to the timer, which causes the IWT to be generated.

FIG. 6 is a block diagram showing a conventional example of an EEPROM. In the conventional example, as shown in FIG.
And a timer-12, and this timer-12 is
Counter section (Counter-13) and IWT generation circuit section (IW
It is composed of a T generation circuit 14). And the oscillator circuit 1
The output OSC of 0 is divided by the counter -13 and supplied to the IWT generation circuit 14.

The IWT generation will be described by taking the EEPROM and .mu.PD6255 having the structure shown in FIG. 6 as an example. The timing chart shown in FIG. These are various timings required for erasing / writing. All of these timings are the output OSC of the oscillator circuit 10 and this OSC.
Since the clock is divided from the divided clock, the IWT becomes longer if the clock width of the output OSC of the oscillation circuit 10 increases.

[0005]

By the way, the frequency of the ring oscillator, which is generally used in the configuration of the oscillation circuit, is highly dependent on the power supply voltage and is not suitable for low voltage operation. A discharge type with a low current is used for the configuration of the oscillator circuit for obtaining a more stable frequency even at a low voltage.

However, even in the low current type oscillating circuit, when the power supply voltage VCC approaches the Vt sum of the configuration Tr, the switching speed decreases and the frequency decreases. Writing time I
Since WT divides the output OSC of the oscillation circuit and creates it,
Even a slight frequency change is amplified and lengthened.

A specific description will be given below by taking a μPD6255 which is a low voltage EEPROM using a low current type oscillation circuit as an example. FIG. 8 shows the "power supply voltage dependency of IWT" when the output OSC of the oscillation circuit is divided by 14 stages to form the IWT. As is clear from the figure, from a certain power supply voltage level V1 to the IWT. Is rising rapidly.

This V1 fluctuates in proportion to the sum of Vt and is usually about 1.8V, but becomes higher when the sum of Vt is higher. However, even if the power supply voltage is lower than V1 and the IWT is doubled, according to the performance of the EEPROM, normal erasing / writing is possible in the same time as the IWT when the power supply voltage is higher than V1.

That is, assuming that the IWT is 10 msec when the power supply voltage is higher than V1, the power supply voltage is below V1 and I
When the WT reaches 20 msec, it means that an extra waiting time of 10 msec is created. Therefore, when the power supply voltage is lower than V1, the amount of data rewritten in the same time is V
There is a problem that it becomes half of that when it is higher than 1.

The present invention has been made in view of the above problems. An object of the present invention is, firstly, that the write time IWT is unnecessarily increased even if the frequency of the oscillator is lowered by a low voltage. Non-volatile semiconductor memory device (EEP)
ROM) and secondly the EEPROM
Non-volatile semiconductor memory device capable of preventing "longer erase / write time" when the frequency of the oscillation circuit is lowered due to the low voltage operation and rewriting more data in the same time (EEPROM).

[0011]

A nonvolatile semiconductor memory device according to the present invention has a power supply voltage level detection circuit and a signal of the power supply voltage level detection circuit in order to solve the above problems and achieve the above object. Timing generation circuit for generating two or more types of erase / write timings according to
(Timer), and an oscillation circuit for supplying a clock to the timing generation circuit (timer).

[0012]

Embodiments 1 to 3 of a nonvolatile semiconductor memory device according to the present invention will be described below in detail with reference to FIGS.

(Embodiment 1) FIG. 1 is a configuration diagram showing Embodiment 1 of a nonvolatile semiconductor memory device according to the present invention. As shown in the figure, the first embodiment is composed of an oscillation circuit 10, a power supply voltage level detection circuit 11, and a timer-12 that switches the erase / write timing according to the output of the power supply voltage level detection circuit 10. .

To explain the operation of the first embodiment, the power supply voltage level detection circuit 11 outputs Q0 when VCC≤V1,
When V1≤VCC≤V2, Q1 is output and Vn≤VCC≤Vn +
At 1, Qn is output. The output CTL of the power supply voltage level detection circuit 11 and the output OSC of the oscillation circuit 10 are supplied to the timer-12 as shown in FIG.

The timer-12 divides the output OSC of the oscillation circuit 10 and outputs the output of the power supply voltage level detection circuit 11 CTL = Q.
When 0, the write time IWT = T0, when CTL = Q1 IWT = T1, and when CTL = Qn IWT = T
generate n. In this way, the timer-12 generates the write time IWT according to the level of VCC, so that it is possible to prevent the IWT from becoming longer than necessary even if the frequency of the oscillation circuit is lowered due to the fluctuation of the power supply voltage. .

(Embodiment 2) This embodiment 2 is the same as the embodiment 1
As shown in FIG. 1, the oscillator circuit 10, the power supply voltage level detection circuit 11, and the timer for switching the erase / write timing according to the output of the power supply voltage level detection circuit 11 as shown in FIG.
It consists of 12. However, the second embodiment is different from the first embodiment in the operation point.

To explain the operation of the second embodiment, the power supply voltage level detection circuit 11 outputs the level Q when VCC> V1 and outputs the level Q- when VCC≤V1. This "V1" is the V at which the frequency of the oscillation circuit 10 drops sharply.
It is the value of CC. Output CT of power supply voltage level detection circuit 11
L and the output OSC of the oscillation circuit 10 are the same as those in the first embodiment.
It is supplied to the timer-12 as shown in FIG.

In the second embodiment, the timer-12 divides the output OSC of the oscillating circuit 10 into a power supply voltage level detecting circuit.
When 11 outputs CTL = Q, write time IWT = T1
And when CTL = Q-, IWT = T2 is generated.
Thus, when the timer is VCC> V1, the write time I
WT = T1, write time IWT = T when VCC ≦ V1
By generating 2, it is possible to prevent the IWT from being unnecessarily long even if the frequency of the oscillation circuit is lowered due to the fluctuation of the power supply voltage.

(Embodiment 3) FIG. 2 is a block diagram showing Embodiment 3 of the nonvolatile semiconductor memory device according to the present invention. As shown in FIG. 2, the third embodiment includes an oscillation circuit 10, a power supply voltage level detection circuit 11, and a timer-12 that switches the erase / write timing according to the output of the power supply voltage level detection circuit 11. . The timer-12 includes a counter section (counter-13) and an IWT generating circuit section (IWT).
It is composed of a generation circuit 14).

To explain the operation of the third embodiment, the power supply voltage level detection circuit 11 outputs an L level when VCC> V1 and an H level when VCC≤V1. This "V
1 "means a VCC at which the frequency of the oscillator circuit 10 drops sharply.
Is the value of. The output CTL of the power supply voltage level detection circuit 11 and the output OSC of the oscillation circuit 10 are supplied to a counter -13 of a timer -12, as shown in FIG. The counter-13 of the timer-12 divides the output OSC of the oscillation circuit 10 by n stages.

In the third embodiment, the power supply voltage level detection circuit
When 11 output CTL = L, output OSC of oscillation circuit 10
Is divided by "n stages", and when OSC = H, a signal obtained by dividing the OSC by "n-1 stages" is supplied to the IWT generating circuit 14 of the timer-12.

FIG. 3 is a diagram for explaining a power supply voltage level detection circuit according to the third embodiment. In the figure, p1 and n1 are long gate width transistors, n2 is a long gate length transistor, n3 is a long gate length depletion transistor, and n4 is a normal n-type transistor.

In FIG. 3, when the power supply voltage is high, p
Although 1, n1 and n2 are ON, in this case, the resistance of n2 is large, so point a becomes H level. Then, since n2 is turned on, the point b becomes L level, and the output CTL of the power supply voltage level detection circuit outputs H level. On the other hand, when the power supply voltage drops and p1 and n1 turn off, point a becomes L level,
n4 turns on. In this case, since the point b becomes H level, the output CTL of the power supply voltage level detection circuit outputs L level.

FIG. 4 is a diagram showing the counter-13 (see FIG. 2) of the timer-12 in the third embodiment. In the third embodiment, as shown in FIG. 4, when the output CTL of the power supply voltage level detection circuit becomes L level, the counter -13 is skipped by one stage.

In the third embodiment, as described above, the timer-
The counter 13 of 12 outputs the output OSC of the oscillation circuit to VCC>
Divide by "n stages" for V1 and "n-1 stages" for VCC≤V1
By dividing the frequency, it is possible to prevent the IWT from being unnecessarily long even if the frequency of the oscillation circuit 10 is lowered due to the fluctuation of the power supply voltage.

FIG. 5 is shown in FIG.
9 is a diagram corresponding to "the power supply voltage dependency of WT") and showing the "IWT power supply voltage dependency" in the third embodiment. In the conventional example, as shown in FIG. The IWT rises sharply from a certain power supply voltage level V1. Therefore, the write time IWT becomes long at a low voltage, but in the third embodiment, as shown in FIG. 5, "a sharp rise of IWT from V1" occurs. Therefore, even if the power supply voltage drops and the frequency of the oscillation circuit drops, the IWT can be prevented from becoming longer than necessary.

[0027]

As described in detail above, the nonvolatile semiconductor memory device according to the present invention includes a power supply voltage level detection circuit,
A timing generation circuit (timer) for generating two or more kinds of erasing / writing timings according to the signal of the power supply voltage level detection circuit; and the timing generation circuit.
By including an oscillation circuit that supplies a clock to the (timer), it is possible to prevent "erasing / writing time becomes longer than necessary" even if the frequency of the oscillator is lowered by a low voltage. The effect occurs.

Such "longer time for erasing / writing" is an unnecessary time in the performance of the nonvolatile semiconductor memory device, and by eliminating this, the next operation can be started without waiting for a wasteful time. It has the advantage that Further, in the nonvolatile semiconductor memory device according to the present invention, as described above, it is possible to prevent the erasing / writing time from becoming long, so that there is an effect that more data can be rewritten in the same time.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a nonvolatile semiconductor memory device according to first and second embodiments of the present invention.

FIG. 2 is a configuration diagram of a nonvolatile semiconductor memory device according to a third embodiment of the present invention.

FIG. 3 is a diagram illustrating a power supply voltage level detection circuit according to a third embodiment.

FIG. 4 is a diagram showing a counter section of a timer according to the third embodiment.

FIG. 5 is a diagram showing “IWT power supply voltage dependency” in Example 3;

FIG. 6 is a configuration diagram of a conventional nonvolatile semiconductor memory device.

FIG. 7 is a timing chart of a conventional example.

FIG. 8 is a diagram showing “IWT power supply voltage dependency” in a conventional example.

[Explanation of symbols]

 10 Oscillation Circuit 11 Power Supply Voltage Level Detection Circuit 12 Timer-13 Counter-14 IWT Generation Circuit

Claims (2)

[Claims] 1. A power supply voltage level detection circuit, a timing generation circuit for generating two or more kinds of erase / write timings according to an output signal of the power supply voltage level detection circuit, and a clock supplied to the timing generation circuit. And a non-volatile semiconductor memory device. 2. A power supply voltage level detecting circuit and two or more types of erasing / erasing by switching the frequency of dividing the clock according to the output signal of the power supply voltage level detecting circuit.
A timing generation circuit for generating write timing,
A non-volatile semiconductor memory device comprising: an oscillation circuit that supplies a clock to the timing generation circuit.