JPH11297089A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory wherein the power source voltage dependence and process dependence can be reduced, a high voltage generator circuit operation is easy to control, and the cost-down can be realized. SOLUTION: In the semiconductor memory, booster control circuits 106, 107 select and feed either an external clock signal or internal clock generated by a contained oscillator circuit to charge pumps 103, 104 which boost according to the fed clock signal to generate high voltages different from a power source voltage. According to the operating condition of the semiconductor memory, the high voltages can be generated based on the selected either clock signal, hence the power source voltage dependence and process dependence can be reduced and stable high voltages can be fed always.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a built-in booster circuit for generating a voltage different from a power supply voltage, and writing, reading and erasing data with the voltage supplied by the booster circuit. .

[0002]

2. Description of the Related Art In a semiconductor memory device, for example, a flash memory constituted by a nonvolatile memory, several kinds of voltages different from a power supply voltage are required at the time of writing, reading and erasing. In general, a method in which a booster circuit is incorporated in a semiconductor memory device and a required voltage is generated by the booster circuit has been adopted.

An ordinary booster circuit is provided with an oscillation circuit for generating an oscillation signal (clock signal) having a predetermined frequency, and generates a predetermined voltage according to the clock signal generated by the oscillation circuit. As an example, a clock signal is generated using a ring oscillator, and a predetermined voltage is generated using a charge pump in accordance with the clock signal generated by the ring oscillator.

FIG. 5 shows an example of the configuration of a semiconductor memory device. As shown in the figure, in the semiconductor memory device of the present example, a high voltage generating circuit 100 is provided to generate a plurality of high voltages V1, V2, and V3 different from the power supply voltage V _CC, and a row address decoder 80 and a memory cell array 90 are respectively provided. And output to the sense amplifier 150. The row address decoder 80, the memory cell array 90 and the sense amplifier 150 control the memory cell array 90 according to the voltages V1, V2 and V3 generated by the high voltage generation circuit 100.
, Read, and erase data.

FIG. 6 shows a circuit diagram of the high voltage generation circuit 100 shown in FIG.
2 shows a specific configuration example. As shown in the figure, the high-voltage generation circuit 100 of this example includes oscillation circuits 101 and 102,
Charge pumps 103 and 104 and voltage conversion circuit 10
5.

The oscillation circuits 101 and 102 are, for example,
It is composed of a ring oscillator. By these oscillation circuits, clock signals CK1 and CK2 each having a predetermined frequency are generated. Charge pump 103
Is the clock signal CK generated by the oscillation circuit 101.
1, the charge pump 104 generates a predetermined voltage VP2 according to the clock signal CK2 generated by the oscillation circuit 102. Voltages VP1 and VP2 are input to voltage conversion circuit 105.

The voltage conversion circuit 105 includes the charge pump 1
For example, n voltages V1 to Vn having different levels are generated in accordance with the voltages VP1 and VP2 supplied by the transistors 03 and 104, respectively, and supplied to predetermined functional circuits. For example, as shown in FIG. 5, the voltage V1 is supplied to the row address decoder 80, the voltage V2 is supplied to the memory cell array 90, and the voltage V3 is supplied to the sense amplifier 14.
0 is supplied.

As described above, by incorporating a high voltage generating circuit in a semiconductor memory device, a plurality of voltages having a level different from the power supply voltage can be generated in a chip, and a plurality of power supply voltages are externally supplied. The required operating voltage can be obtained without the need for a simple circuit configuration, and the cost of the device can be reduced.

[0009]

[SUMMARY OF THE INVENTION Incidentally, in the conventional semiconductor memory device described above, the oscillation circuit in the high voltage generating circuit is operated with a supply voltage V _CC, a large power supply voltage dependency of the generated clock signal . Further, the current capability output by the booster circuit constituted by a charge pump or the like depends on the frequency of the clock signal. As a result, the output voltage and current of the charge pump depend on the power supply voltage V _CC . 2. Description of the Related Art In recent years, the voltage and power consumption of semiconductor devices including a semiconductor memory device have been reduced, the power supply voltage supplied to a chip has been reduced, and a different power supply voltage may be supplied depending on an operation state and the like. . For this reason, the voltage generated by the built-in high-voltage generation circuit of the semiconductor memory device greatly changes, and the performance of the semiconductor memory device may be significantly reduced.

Further, the frequency of the clock signal generated by the oscillation circuit constituted by a ring oscillator or the like has a property depending on the process. For example, the frequency of a clock signal generated by a process variation may change significantly. For this reason, there is a method of providing an adjustment circuit with a resistance element, a capacitance element, and the like in order to reduce the influence due to process variation.However, this increases the layout area of the circuit, and further requires an adjustment circuit. However, there is a disadvantage that the throughput at the time of assembling is reduced and the cost is increased.

The present invention has been made in view of the above circumstances, and an object of the present invention is to reduce the dependency of internally generated high voltage on the power supply voltage and the process, and to easily control the operation of the high voltage generating circuit. Another object of the present invention is to provide a semiconductor memory device that can realize cost reduction.

[0012]

In order to achieve the above object, a semiconductor memory device according to the present invention generates a voltage different from a power supply voltage, and performs writing, reading and erasing with the generated voltage. A boosting circuit that performs a boosting operation in response to a clock signal input from an external input terminal and generates a boosted voltage different from a power supply voltage.

Further, in the semiconductor memory device according to the present invention, an oscillating circuit for generating an oscillating signal having a predetermined frequency, a clock signal input from an external input terminal, or an oscillating signal generated by the oscillating circuit may be used. And a boosting circuit that performs a boosting operation in accordance with the signal selected by the selecting circuit and generates a boosted voltage different from the power supply voltage.

In the present invention, preferably, the booster circuit is constituted by, for example, a charge pump, and a control circuit for controlling the selection circuit includes an oscillation signal from the oscillation circuit in accordance with a change in power supply voltage. Alternatively, any one of the clocks input from the external input terminal is selected. For example, when the power supply voltage falls below a predetermined level, the control circuit causes the selection circuit to select the clock signal input from an external input terminal.

Further, the present invention preferably has a frequency dividing circuit for dividing the frequency of the clock signal selected by the selecting circuit and supplying the frequency-divided signal to the boosting circuit.

According to the present invention, a voltage supply circuit such as a booster circuit in a semiconductor memory device requiring a voltage different from a power supply voltage at the time of writing, reading and erasing operations, for example, a flash memory composed of nonvolatile memory cells To generate a high voltage or a negative voltage having a predetermined level. The voltage supply circuit includes, for example, a charge pump circuit that generates a voltage having a predetermined level in response to a clock signal, and operates in accordance with conditions such as the operating environment of the semiconductor memory device and a power supply voltage supplied from the outside. Either a clock or an internal clock generated by an oscillation circuit built in the chip is selected and supplied to a charge pump or the like. Thereby, the power supply voltage dependency and the process dependency of the voltage generated by the voltage supply circuit can be reduced, the operation of the high voltage generation circuit can be easily controlled, and the cost can be reduced.

[0017]

FIG. 1 is a circuit diagram showing an embodiment of a semiconductor memory device with a built-in high voltage generating circuit according to the present invention. The semiconductor memory device of the present embodiment includes an input / output control circuit 10, an operation logic control circuit 20a,
Status register 30, address register 40, command register 50, control circuit 60a, row address buffer 70, row address decoder 80, memory cell array 90, high voltage generation circuit 100a, R / B (Ready
/ Busy) circuit 110, a column buffer 120, a column decoder 130, a column register 140, and a sense amplifier 150.

The input / output control circuit 10 controls input and output operations of addresses, data, commands and status signals indicating the states of the memory. For example, based on the control of the input / output control circuit 10, a row address and a column address are input via an address input terminal, and input to the row address buffer 70 and the column buffer 120 via the address register 40, respectively. Further, at the time of writing, write data is input via the data input / output terminal and stored in the data register 140, and at the time of reading, the data read by the sense amplifier 150 is held in the data register 140. Under the control of the control circuit 10, the data of the data register 140 is output to the data input / output terminal.

The operation logic control circuit 20a includes:
The input / output control circuit 10 is controlled according to an external operation control signal. As an external operation control signal,
A chip enable signal / CE, a command latch enable signal CLE, an address latch enable signal ALE,
There are a write enable signal / WE, a read enable signal / RE, and a write inhibit signal / WP. Further, as shown in FIG. 1, the operation logic control circuit 20a receives the clock signal CLK input from the outside, and outputs the clock signal CLK to the high-voltage generation circuit 100.
Input to a.

The status register 30 includes a control circuit 60
Holds the status signal indicating the operation state output by the input / output control circuit 1
0 to output to the outside. Address register 40
Holds the row address and the column address input via the input / output control circuit 10, outputs the held row address to the row address buffer 70, and outputs the column address to the column buffer 120.

The command register 50 holds a command input via the input / output control circuit 10, and outputs the held command to the control circuit 60a. The control circuit 60a receives the status register 30, the column decoder 130, the data register 140, and the sense amplifier 1 according to the command input from the command register 50.
A control signal for controlling the operation of F.50 is output. Further, control circuit 60a outputs a control signal to R / B circuit 110 and high voltage generation circuit 100a, respectively.

The row address buffer 70 holds the row address from the address register 40 and outputs the row address to the row address decoder 80. Row address decoder 80
Selects a specified word line among a plurality of word lines of the memory cell array 90 in accordance with an input row address, and applies an activation voltage to the selected word line. The activation voltage applied to the selected word line is, for example, a voltage generated by the high voltage generation circuit 100a.

The memory cell array 90 is composed of a plurality of memory cells arranged in a matrix. The memory cells in each row are connected to the same word line, and the memory cells in each column are connected to the same bit line. Further, the word lines are connected to the row address decoder 80, and the bit lines are connected to the sense amplifier 150.

The column buffer 120 holds the column address from the address register 40 and outputs it to the column decoder 130. The column decoder 130 selects a designated bit line from a plurality of bit lines according to the input column address.

The data register 140 holds the write data input via the input / output control circuit 10 at the time of writing, and inputs the write data to the sense amplifier 150. At the time of reading, the data read by the sense amplifier 150 is held and output to the outside via the input / output control circuit 10.

The sense amplifier 150 reads data stored in the selected memory cell according to the potential of the bit line selected at the time of reading, and outputs the data to the data register 140.
At the time of writing, the potential of the selected bit line is set in accordance with the write data held in the data register 140, and the write data is stored in the selected memory cell.

In the semiconductor memory device configured as described above, a command input via the input / output control circuit 10 is temporarily stored in the command register 50 and then sent to the control circuit 60a. The control circuit 60a generates a control signal for controlling the operation specified by the command, and outputs the generated control signal to a predetermined partial circuit. For example, the control signal SC is output to the high voltage generation circuit 100a. The high voltage generating circuit 100a generates voltages V1, V2, and V3 having different levels from the power supply voltage V _CC in accordance with the control signal SC, and supplies the generated voltages V1, V2, and V3 to the row address decoder 80, the memory cell array 90, and the sense amplifier 150, respectively. .

FIG. 2 is a circuit diagram showing a specific configuration of high voltage generating circuit 100a. Hereinafter, with reference to FIG.
The operation of the high voltage generation circuit 100a according to the present embodiment will be described. As shown, the high voltage generation circuit 100a
Are the boost control circuits 106 and 107, the charge pump 10
3 and 104 and a voltage conversion circuit 105.

The boost control circuit 106 controls the control signals SC1,
In response to the clock signal CLK and the voltage VP1 fed back from the charge pump 103, the clock signal CK1 is output to the charge pump 103. Charge pump 103 receives clock signal CK1 from boost control circuit 106, performs a boost operation in response thereto, and outputs voltage VP1 different from power supply voltage V _CC .

In substantially the same manner as described above, the boost control circuit 107
Receives the control signal SC2, the clock signal CLK, and the voltage VP2 fed back from the charge pump 104, and outputs a clock signal CK2 to the charge pump 104. The charge pump 104 includes the boost control circuit 10
7 receives the clock signal CK2, performs a boosting operation in response thereto, and outputs a voltage VP2 different from the power supply voltage V _CC .

The voltage conversion circuit 105 includes the charge pump 1
Receiving the voltages VP1 and VP2 from the circuits 03 and 104,
A plurality of different voltages V1 to Vn are generated and supplied to the outside.

The high voltage generating circuit 100a is not limited to the configuration shown in FIG. 2, but may be provided with a circuit set including a plurality of boost control circuits and a charge pump.
The above voltage can be generated and supplied to the voltage conversion circuit 105.

FIG. 3 shows an example of the configuration of the boosting control circuit. The boost control circuits 106 and 107 shown in FIG.
For example, it has the configuration shown in this booster control circuit example. As shown, the boost control circuit includes an AND gate AND1, a comparator CMP1, a reference voltage source, and voltage dividing resistance elements R1 and R2.

The voltage VP1 fed back from the charge pump is divided by the resistance elements R1 and R2, and the divided voltage Vr is input to the inverting input terminal "-" of the comparator CMP1. The reference voltage _Vref generated by the reference voltage source is input to the non-inverting input terminal “+” of the comparator CMP1. The signal S _E output from the comparator CMP1 is input to the AND gate AND1. The AND gate AND1 has three input terminals,
The control signal SC1 and the clock signal CLK input from the outside are input to two input terminals among them.

[0035] In thus constituted boost control circuit, the output clock signal CK1 is controlled in response to the signal S _E from the control signals SC1 and the comparator CMP1. When the control signal SC1 is at the low level, the output terminal of the AND gate AND1 is held at the low level, so that there is no output of the clock signal CK1 and the charge pump does not operate. That is, in this state, the voltage VP1 is not output.

On the other hand, when the control signal SC1 is at high level, in response to the signal S _E from the comparator CMP1, the output clock signal CK1 is controlled. For example, the divided voltage Vr of the output voltage VP1 of the charge pump is equal to the reference voltage Vr.
is higher than the _ref, the output signal S _E of the comparator CMP1 is held at the low level. At this time, the output terminal of the AND gate AND1 is kept at the low level, and the clock signal CK1 is not output. Conversely, the divided voltage Vr in the output voltage VP1 of the charge pump is lower than the reference voltage V _ref, the output signal S _E of the comparator CMP1 is held at the high level. At this time, the AND gate AND1
Is output to its output terminal. That is, the clock signal CLK input from the outside
Is supplied to the charge pump as CK1. In response, the charge pump operates, and voltage VP1 is output.

As described above, the control signal SC1 functions as an enable signal for controlling the boosting operation, and the control signal SC1
The boosting operation is turned on / off according to the level of C1, and controls the supply of voltage. During the boost operation, the comparator CMP
The outputted signal S _E by 1, the step-up operation is adjusted. As a result, a boosted voltage VP1 having a stable level is output by the charge pump. Note that the voltage V
The voltage value of P1 is set by the reference voltage _Vref and the resistance values of the voltage dividing resistance elements R1 and R2.

FIG. 4 shows another example of the configuration of the boosting control circuit. As shown in the figure, the boosting control circuit of the present example has an AND
Gate AND2, selection circuit SEL1, oscillation circuit OSC
1, a comparator CMP1, a reference voltage source, and voltage dividing resistance elements R1 and R2.

The boosting control circuit of this embodiment is different from the boosting control circuit shown in FIG.
L1 has been added. The clock signal CLK0 is generated by the oscillation circuit OSC1, and the clock signal CLK or the oscillation circuit O input from the outside is selected by the selection circuit SEL1.
One of the clock signals CLK0 generated by SC1 is selected, and the selected clock signal is supplied to the charge pump as a clock CK1. Note that the comparator CMP1, the reference voltage source and the voltage dividing resistance elements R1 and R2
Has substantially the same configuration as that of the booster control circuit shown in FIG.

The oscillation circuit OSC1 includes a comparator CMP
A clock signal CLK0 having a predetermined frequency is output in response to the signal S _E from S1. The clock signal CLK inputted from the outside is input to one input terminal of the AND gate AND2, the other input terminal of the AND gate AND2 is signal S _E from the comparator CMP1 is inputted. Therefore, the selection signal S controlled clock signal CLK by _E is the AND gate AND2 circuit SEL1
Is input to

The selection circuit SEL1 receives an external clock signal CLK (AND gate A) according to the control signal SC1.
ND2) or the clock signal CLK0 generated by the oscillation circuit OSC1 is selected and supplied to the charge pump.

As described above, in the boosting control circuit of this embodiment, the control signal SC1 functions as a selection signal for selecting the external clock signal CLK or the internal clock signal CLK0. That is, according to the level of the control signal SC1, either the clock signal CLK input from the outside or the clock signal CLK0 generated by the oscillation circuit OSC1 built in the chip is selected and supplied to the charge pump. Even when any of the clock signal is selected by the signal output S _E by the comparator CMP1, the step-up operation is adjusted. As a result, a boosted voltage VP1 having a stable level is output by the charge pump.

In the example of the boosting control circuit shown in FIG. 4, another control signal is taken in as an enable signal for controlling the boosting operation, and the output of the selection circuit is turned on / off in response to the control signal. Needless to say, the charge pump can be set to the operating or stopped state.

In the boosting control circuit of FIG. 4, an external clock signal or an internal clock signal generated by a built-in oscillation circuit can be selected and supplied to a charge pump in accordance with a control signal. Therefore, for example, a stable high voltage can be supplied by selecting an appropriate clock signal according to the operating conditions of the semiconductor memory device. As an example, for example, a built-in oscillation circuit is connected to a power supply voltage V
_As a countermeasure to eliminate the so-called power supply voltage dependency in which the operation state changes according to the _CC , when the supplied power supply voltage is above a certain level, an internal clock signal is selected and a high voltage is generated. Conversely, when the power supply voltage drops and falls below a certain level, the oscillation frequency of the oscillation circuit built into the chip becomes unstable. A stable high voltage can be supplied.

As described above, according to the present embodiment, the boosting control circuit selects either the external clock signal or the internal clock signal generated by the built-in oscillation circuit and supplies it to the charge pump. . The charge pump performs a boosting operation in accordance with the supplied clock signal, and generates a high voltage different from the power supply voltage. As a result, any one of the clock signals can be selected according to the operating conditions and a high voltage can be generated in accordance with the selected clock signal. Therefore, the power supply voltage dependency can be reduced, and a stable high voltage can always be supplied.

[0046]

As described above, according to the semiconductor memory device of the present invention, either the external clock signal or the internal clock signal generated by the built-in chip type generating circuit is selected according to the operating conditions. By generating a high voltage accordingly, the dependency on the power supply voltage or the process is reduced, and a stable high voltage can be supplied. In addition, when a high voltage is generated using an external clock signal, the operation of the high voltage generation circuit can be easily controlled, and further, an adjustment circuit for dealing with process dependency is not required, and the cost of the circuit can be reduced. There are advantages.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a circuit diagram showing a configuration of a high voltage generation circuit of the semiconductor memory device shown in FIG.

FIG. 3 is a circuit diagram illustrating an example of a boost control circuit.

FIG. 4 is a circuit diagram showing another example of the boost control circuit.

FIG. 5 is a circuit diagram showing a configuration of a conventional semiconductor memory device with a built-in high voltage generation circuit.

FIG. 6 is a circuit diagram showing a configuration of a conventional built-in high voltage generation circuit.

[Explanation of symbols]

10: input / output control circuit, 20, 20a: operation logic control circuit, 30: status register,
40 ... address register, 50 ... command register, 6
0, 60a: control circuit, 70: row address buffer,
80: row address decoder, 90: memory cell array, 100, 100a: high voltage generation circuit, 101, 10
2: Oscillation circuit, 103, 104: Charge pump, 10
5: voltage conversion circuit, 106, 107: boost control circuit, 1
10 R / B circuit, 120 column buffer, 130
Column decoder, 140 column register, 150 sense amplifier 150, CMP1 comparator, AND
1, AND2 ... AND gate, R1, R2 ... resistance element,
V _ref ... Reference voltage.

Claims (5)

[Claims] 1. A semiconductor memory device that generates a voltage different from a power supply voltage and performs writing, reading, and erasing according to the generated voltage, and performs a boosting operation according to a clock signal input from an external input terminal. And a booster circuit for generating a boosted voltage different from a power supply voltage. 2. A semiconductor memory device that generates a voltage different from a power supply voltage and performs writing, reading and erasing according to the generated voltage, comprising: an oscillation circuit that generates an oscillation signal having a predetermined frequency; A selection circuit for selecting one of a clock signal input from an input terminal and an oscillation signal generated by the oscillation circuit; a boosting operation performed in accordance with the signal selected by the selection circuit; Semiconductor memory device having a booster circuit for generating a voltage. 3. A semiconductor device according to claim 2, further comprising a control circuit for causing said selection circuit to select either an oscillation signal from said oscillation circuit or said clock signal input from an external input terminal in response to a change in power supply voltage. Storage device. 4. The control circuit causes the selection circuit to select the clock signal input from an external input terminal when the power supply voltage falls below a predetermined level.
The semiconductor memory device according to claim 1. 5. The semiconductor memory device according to claim 2, further comprising a frequency dividing circuit for dividing a signal selected by said selecting circuit and supplying the divided signal to said boosting circuit.