JPS62297955A - Cache memory device - Google Patents

Abstract

PURPOSE:To prevent the malfunctions of a cache memory device by invalidating the cache hit which shows that no access is given as long as the state signal received from a CPU shown a user state and also the state signal in a protection memory shown a user state. CONSTITUTION:When a cache hit state is secured, a protection check circuit 31 decides the presence or absence a state, i.e., a protection state that receives no access as long as the state signal received from a CPU shows a use state and also the state signal in a protection memory 4 corresponding to the data to be read out shows a user state. When the protection state is confirmed, the circuit 31 produces a cache hit invalidating signal to send it to a cache controller 38. Thus the controller 38 proceeds to a cache writing action, e.g., an action to be carried out in a cache mistake mode. As a result, the wrong memory reference is avoided.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention (Field of Industrial Application) The present invention relates to an information processing device equipped with a cache memory, and particularly to a cache memory device that takes memory cA protection into consideration.

(Prior art) Conventionally, in order to improve the processing speed of information processing equipment, C
A memory that has a small capacity but a long operating speed, that is, a cache memory, is arranged between the PU and the main storage device.

There are various system configurations for cache memory devices, but the system to which the present invention is applied is as shown in FIG. A memory management unit (6) (hereinafter referred to as MMU) that converts the data into a physical address is provided, and the cache memory (2) is referred to by a logical address.

The MMU (6) and the main storage device (7) are connected via a system bus (13). Also, CPU (1)
, MMU (6), and cache memory (2) are connected by a local bus (51) consisting of a logical address line, a data line, and a control line.
The U (6) and the system bus (13) are connected by a local bus (52) consisting of physical address lines, input lines, data lines, and control lines.

In this type of information processing device, if the cache hit continues without causing a cache miss, the CPU can continue executing the program by referring only to the cache memory; Therefore, there is no need to convert a logical address into a physical address when reading data from the cache memory (2).

As a result, extremely high-speed access becomes possible.

Note that the operation of the cache memory (2) is controlled by a well-known cache controller (38).

The MMU (6) has a so-called memory protection function in addition to the address change tA function.

For example, when a program containing an error is executed, there is a risk that the program will run out of control if the program accidentally jumps to the data area. Furthermore, there is a risk of writing to the program area, and if the OS area is destroyed, the system will go down. These defects are
This is particularly serious in time-sharing systems and multi-user systems.

Therefore, conventionally, the MMU (6) is provided with a memory protection function to prevent the above-mentioned problem from occurring. That is, the storage area of the main storage device (7) is provided with a user area that can be freely accessed by the user and a supervisor area that is prohibited from being freely accessed by the user.Normally, the user area and the supervisor area are partially separated from each other. overlap, and a shared area exists.

On the other hand, the CPU (1) creates a state signal indicating whether its operating mode is a higher privileged state (supervisor state) or a lower privileged state (user state), and
), MMtJ (6) creates a segment violation signal for memory protection based on the status signal, and sends it to the CPU (
1). As a result, when the operating mode of CPU (1) is the supervisor state, access to the supervisor area is allowed, but when the operating mode of CPU (1) is the user state, access to the supervisor area is prohibited. Ru.

Furthermore, since it is necessary to similarly protect the cache memory (2), the storage area of the cache memory (2) is divided into a supervisor area and a user area. However, in this case another problem arises due to the fact that both head regions are completely separated from each other.

(Problem to be Solved) In a cache memory device that is referenced by a logical address, since data is read from the cache memory (2) without going through the MMU (6), the data in the shared area When accessing, the following problem occurs.

That is, when data X1 stored at a predetermined address A in the cache memory 2) is first read in the user state, data X2 is written to the same address A in the supervisor state, and then address A is read out in the user state. Originally, the final read data should be X2, but it becomes Xl, which causes a malfunction.

Normally, setting up the shared space is essential, so conventionally the following measures have been taken.

A program is set in the MMU (6) that prohibits writing (loading) of shared area data to the 11-like cache memory.

When writing data in the shared area to the Sho Iuta cache memory, the entire cache memory (2) is cleared (invalidated) at the same time.

However, all of these measures require changes to the software (programs), which not only goes against the O8 standardization, but also, especially when using measure (2), there is a problem in which the hit rate of the cache memory decreases significantly. Invite.

(Means for solving the problem) In the cache memory device according to the present invention, the cache memory (2) has a state corresponding to each of a plurality of storage area blocks provided in the cache memory. A protection memory (4) having a plurality of data storage units (40) for storing signals is linked.

Furthermore, the protection memory (4) and the cache memory (2) are equipped with a control circuit (3) consisting of a hardware circuit.

The control circuit (3) has a cache controller (38) that directly controls the operation of the cache memory (2), and when data is written to a storage area block of the cache memory (2), a control circuit that corresponds to the block. Protected memory (4)
a writing means for writing a status signal into a data storage section (40) in the CPU (1), and a writing means for writing a status signal into a data storage section (40) in the CPU (1); A protection means is provided for generating and sending a cash hit invalidation signal to the cache controller (38) when the status signal in the corresponding protection memory (4) indicates that it is not being accessed in the user state.

(Operation) When the storage device is accessed by the CPU (1), the cache controller (38) determines whether the command to the storage device is for reading or writing data based on the read/write control signal from the CPU (1). Detect.

When the command is to annotate data, the cache controller (38) detects whether the cache memory (2) has been hit.

In the case of a cache miss, data is read from the specified address in the storage device, and the data is sent to the CPU (1) and moved to the cache memory (2).

At the same time, the protected memory (4) corresponding to the read address
A status signal (supervisor status or user status) sent from the CPU (1) is written in the data storage section in the CPU (1).

If the cache is hit, the protection measure is to
) indicates the user state, and it is determined whether the state signal in the protected memory (4) corresponding to the data to be read is in the user state and not accessed - the protected state.

The protected state here means that data written in the supervisor state is stored in the data storage section (40) of the cache memory (2) to be read, and the data is to be read out in the user state. means the state. Therefore, when referring to the cache memory in the protected state,
As mentioned above, this will cause malfunction.

However, in the cache memory device of the present invention, in the protected state, the protection means creates a cache invalidation signal and sends it to the cache controller (38).
As a result, the cache controller (38) moves to a cache write operation (cache load), which is an operation in case of a cache miss. Therefore, no erroneous memory references occur.

If not, the cache hit is enabled and the cache controller (38) proceeds to normal cache read operations.

As long as the instruction to the storage device is to read data or a program, the above operation is repeated, and the cache memory (
2) is referred to by the CPU (1) while being rewritten as appropriate, thereby shortening the access time.

When the command from the CPU (1) is to write data, a predetermined cache modification operation (cache modification) set in the cache controller (38) is performed only when the address of the write command exists in the cache memory. will be carried out.

(Effects of the Invention) In the cache memory device according to the present invention, the protection memory (4) can be formed by a small capacity memory (for example, a 16-bit static RAM), and the control circuit (3) can be formed by a small capacity memory (for example, a 16-bit static RAM). Since the MMU can be configured with simple hardware consisting of logic circuit elements, etc., the MMU does not require any special functions, nor does it require software to prevent malfunctions associated with memory protection.

However, the hit rate is improved compared to conventional cache memory devices. In other words, the hit rate does not decrease compared to the conventional device that took the above measure (2), and compared to the conventional device that took the measure (2), the number of times the entire cache memory is cleared decreases, so the hit rate decreases. will improve.

(Example) As shown in FIG. 1, the system configuration of the information processing apparatus according to the present invention is such that a logical address line connecting CPU (1) and ~M U (6) is connected to a control circuit 3) that is controlled by A cache memory (2) and a protection memory (4) are connected to each other.

In addition to the main storage device (7), the system bus (5) also has
A secondary storage device (not shown) such as a magnetic disk device is connected as necessary.

Figure 2 shows cache memory (2) and protection memory (4).
and the specific circuit configuration of the control circuit (3), both memories (2) and (4) are each configured by static RAM, and the control circuit (3) is a simple circuit consisting of logic circuit elements, etc. as shown in the figure. It is composed of hardware.

As shown in Figure 3, the cache memory (2) stores management information l in which a flag ■ for determining the validity of data is stored.
(21), an address tag i (20) in which the upper bit part T of the logical address is stored, and a data column (22) in which the data D in the storage device is stored. Contains area blocks.

The protection memory (4) includes a large number (N) of data storage units (40) corresponding to each storage area block of the cache memory (2). Each data storage section (40) includes
Protected data P is stored which is 1" when the data stored in the cache memory (2) is data in the user area, and is 0 when it is data in the supervisor area.

The cache memory (2) and the protection memory (4) are
As shown in the figure, logical address line A (Al~An) (
54), the lower address lines AL(A, ~Ak)(
55).

The control circuit (3) includes a cache controller (38) having substantially the same configuration as that installed in a conventional device, a protection check circuit (31) serving as a protection means, and a C.
The status signal FC from the PU is sent to the protection memory (
4) is connected to the I10 port to constitute an entry means.

In addition, when the status signal FC is “1”, it is the user status, and “0” is the user status.
When , it indicates the supervisor state, and becomes the protected data P by being written to the protected memory (4).

Logical address line A (54) and data line (5
3) is connected to the cache memory (2) and the protection memory (4) via the cache controller (38).

Also, based on the status signal from the CPU, M M U (6
) The segment violation signal ER generated by the cache memory (2) is transmitted via the cache controller (38) to the cache memory (2
) is connected to the management information column (21). The violation signal ER takes a value of "0" when an illegal access is detected by the MMU (6).

Furthermore, a read/write control signal WR and a bus cycle end confirmation signal DT from the CPU are input to the cache controller (38). Signal WR indicates a read cycle when it is "1", and indicates a write cycle when it is "0". Signal DT indicates that the bus cycle has ended when it is "1".

The protection check circuit (31) receives the state π signal F from the CPU.
C is “1” (user state) and protected memory (4)
When the protected data P output from .

A cash hit is detected by a comparator (30) connected between the upper address line (56) and the tag field (20) of the cache memory (2). The output signal of the comparator (30) and the signal from the management information n (21) of the cache memory (2) are
) is converted into a hit signal H, and then the hit signal H is converted into a hit signal H.
is the read/write control signal WR and protection check circuit (
31) is input to a Nant gate (33) and converted into a hit signal H' indicating a valid hit.

The read/write control signal ER and the bus cycle end confirmation signal DT are inputted to the AND gates (34) and (35) together with the hit signal H and the like as shown in the figure.

When the output signal L0 of the AND gate (34) is "1", it indicates that the cache write operation should be started, and when the output signal M0 of the AND gate (35) is "1", it indicates that the shift should be made to the cache modification operation. show.

The hit signal H' and the output signal of the NOR gate (36) are connected to an input/output control section (37), which controls writing and reading of data to and from the data column (22) of the cache memory (2).

Hereinafter, the circuit operation of the control circuit (3) shown in FIG. 2 will be explained based on the flowchart of FIG. 4. However, the control circuit (3) is a hardware circuit, and the flowchart is only used for convenience in explaining circuit operations, and the order of operations on the flowchart does not indicate the actual order of circuit operations.

The f-fork 1 read/write control signal WR is set to "1",
As a result, the cache controller (38) detects that the command to the main storage device (7) is to read data ((8) in FIG. 4).

A comparator (3o) checks whether the content T (address) of the tag column (20) of the cache memory (2) specified by the address line (54) matches the value of the upper address line A H (56). (Fig. 4 (81)).

In the case of a cache miss in which the two addresses do not match, a cache write operation (FIG. 4 (91)), which will be described later, is executed.

Both addresses match and the output of the comparator (30) becomes “
0” and management information 1f of cache memory (2)
When the output (flag -) of i (21) is "1", the output signal H of the AND gate (32) becomes "1" representing a cash hit (FIG. 4 (82)).

The status signal FC from the CPU is “0” (Fig. 4 (8)).
3)), or when the protection data P in the protection memory (4) is "1" (Fig. 4 (84)), the output of the protection check circuit (31) becomes 1". As a result, the output of the protection check circuit (31) becomes 1". When all the input signals to 33) become "1", the output H' of the Nant gate (33) becomes "0", and the input/output control section (37) interposed in the data line (53)
is sent as a data read command.

Note that the output signal L0 of the AND gate (34) and the output signal B0 of the AND gate (35) both indicate "0", and the output signal of the NOR gate (36) becomes "1".

As a result, the gate of the input/output control unit (3) in the direction toward the CPU is opened, and the data in the cache memory (2) is opened! The data in (22) is sent to the CPU via the data line (53) ((9) in FIG. 4).

When the status signal FC from the CPU is "1" and the protected data P in the protected memory (4) is "0", the cache write operation (FIG. 4 (91) ).

In the cache write operation, Antogame) (3
The output signal L0 of 4) is "1", and the output signal B of the AND gate (35). indicates "0", and the output signal of the NOR gate (36) becomes "0".

As a result, the input/output control unit (37) has a cache memory (
2) is opened, and the data sent from the main memory via the data line (53) is written to the specified address in the data field (22), and the data specified by the address line A L (55) is written. A status signal FC is written into the data storage section 40) in the protected memory (4). At the same time, data sent from the main memory is transferred to the CPU.

For example, regarding the example of malfunction associated with memory protection cited above (problems to be solved), the device of the present invention prevents malfunction as described below.

That is, when data in the shared area written in the supervisor state is read out in the user state, the state signal FC from the CPU indicates "l" representing the user state, and the protection memory (4
) The protected data P is “0” indicating the supervisor status.
Therefore, the output of the protection check circuit (31) becomes "0'°, the cache hit is invalidated, and a transition is made to the cache write operation in the case of a cache miss."

Therefore, malfunctions associated with memory protection do not occur.

When the read/write signal WR is "0" and the data at the address specified for writing exists in the cache memory (2), the data from the CPU is written to the main memory at the same time. , the cache memory (2) is modified (cache modified) based on the data, and the protected memory (4) is modified (cache modified) based on the data.
) is also corrected at the same time (FIG. 4 (92)).

Data at write address is cache memory (2)
If the cache memory (2) does not exist, there is no change in the cache memory (2).

In the above cache memory device, the cache memory (2) and the protection memory (4) can be formed by high-speed, small-capacity RAM, and the control circuit (3) is mainly composed of logic circuit elements. Also, both memories (2) and (4) are referenced by logical addresses, and MM is used for data read operations.
Address conversion by U is not involved, therefore, processing associated with writing and reading data is performed at extremely high speed.
The performance of the cache memory is fully demonstrated. However, in the configuration of the present invention, there is no need to change the program for normal memory protection, and standard O8 porting is easy.

Note that the configuration of each part of the present invention is not limited to the above-mentioned embodiments, and various modifications can be made within the technical scope of the claims.

For example, in the above embodiment, each data storage section (40) of the protection memory (4) is composed of one bit, but it goes without saying that it may be composed of a plurality of bits. For example, in the case of 2 bits, the user area and supervisor area can be further divided into a data area and a program area, thereby making it possible to control various modes.

[Brief explanation of drawings]

FIG. 1 is a system configuration diagram of an information processing device equipped with a cache memory device according to the present invention, FIG. 2 is a circuit configuration diagram of the cache memory device, FIG. 3 is an explanatory diagram of the memory structure, and FIG. 4 is a control circuit. Flowchart explaining the operation of
The figure is a system configuration diagram of a conventional device.

Claims (1)

[Claims] [1] Between the CPU (1) and the storage device, the CPU (1)
A memory management unit (6) is provided which performs memory protection based on a status signal indicating whether the operating mode of the CPU is a higher privileged state (supervisor state) or a lower privileged state (user state). The logical address line connecting (1) and memory management unit (6) includes
In an information processing device connected to a cache memory (2) controlled by a cache controller (38),
The cache memory (2) includes a plurality of data storage units (40) for storing the status signals corresponding to each of the plurality of storage area blocks provided in the cache memory.
A control circuit (3) is connected to the protection memory (4) and the cache memory (2).
), and the control circuit (3) includes the cache controller (38) and the cache memory (2).
) When data is written to the storage area block of the data storage section (4) in the protected memory (4) corresponding to the block
writing means for writing a status signal into the protected memory (4), in which the status signal from the CPU (1) indicates the user status and corresponds to the data to be read when the cache is hit in a data read operation; ) A cache memory device characterized by comprising a protection means for generating a cache hit invalidation signal and sending it to the cache controller (38) when the status signal in the user status indicates that the cache hit invalidation signal is not being accessed in the user status. .