JPS62295446A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enhance the density of a semiconductor integrated circuit device and to integrate it in a large scale by connecting one conductivity type polycrystalline silicon conductor with the first and second peripheries of an emitter region to extend them on an insulating film perpendicularly to one direction. CONSTITUTION:A P-type single crystal region 12 and a silicon nitride film 14 are formed on a silicon P-type single crystal substrate 11, an N-type impurity element is implanted to form an N-type single crystal region 15, and a silicon polycrystalline film 16, a silicon oxide film 17 and a photoresist 18 are provided. Then, the film 16 is partly converted to a silicon oxide 20 to form a coupler of silicon polycrystalline film, and high density N-type impurity element is implanted to the desired part of the coupler. The region 15 is used as a collector region, a P-type single crystal region 21 is used as a base region, and a high density N-type single crystal region 22 is used as an emitter region, a metal silicide 24 is formed, it is covered with an insulating film 25, connected with the metal silicide in the hole, a metal film extended perpendicularly on the film 25 is formed to form a desired electrode wiring terminal 101...

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention The present invention relates to a high-density integrated circuit device having bipolar transistors, and particularly relates to a high-density bipolar transistor type semiconductor integrated circuit device using a polycrystalline silicon layer. .

has been configured. Here, the connection of the circuit element to the metal wiring path was made through a contact hole, that is, an opening provided in an insulating film covering the surface of the circuit element.

However, with this conventional configuration method, when aiming for high-density and large-scale integration of integrated circuit devices, it is necessary to provide a large number of fine contact holes, which is difficult to achieve. This required extremely advanced fine processing technology.

An object of the present invention is to provide a new bipolar transistor integrated circuit device structure suitable for high-density and large-scale integration.

A feature of the present invention is that one main surface of the conductive substrate is exposed in a planar shape to form a rectangular shape extending in one direction, and is surrounded by an insulating film embedded in the conductive substrate. A conductive collector region is provided with its entire circumference surrounded by the insulating film, a base region of the opposite conductivity type of the transistor is provided, and two ivy regions of one conductivity type of the transistor are provided with the first and second ivy regions of the transistor. The sides of the insulating film are in contact with the long sides of the rectangle, and the remaining third and fourth
a polycrystalline silicon conductor is provided in the base region with a side thereof exposed to the one main surface, and a polycrystalline silicon conductor of a conductive layer is connected between the first and second sides of the emitter region to form a conductor in one direction. and a conductor integrated circuit device extending on the insulating film in a direction perpendicular to the conductor. Further, a plurality of bipolar transistors having such a configuration can be arranged on a conductor substrate, and the emitter regions of each bipolar transistor can be commonly connected by the polycrystalline silicon conductor.

Next, in order to better understand the present invention, examples will be given and explained.

First, a first embodiment of the present invention will be described with reference to FIGS. 1 to 8.

Transistor element l, shown in the electrical equivalent circuit in Figure 1,
Examples of the resistor element 2.3 and the diode element 4#5 will be explained with reference to FIGS. 2 to 8. First, a P-type single-crystal region 12 for the channel stock horn f with a high degree of impurity impregnation is formed in a ring shape around the area where the transistor is to be formed, using a well-known selective diffusion method using a silicon oxide film as a mask.
A silicon nitride film 14 is formed on the surface of the area where the transistor is to be formed.
Using this as a mask, a selective oxidation method is applied to form a silicon oxide film 13 having a thickness of approximately 2 nm and embedding it in the non-element forming portion of the conductor substrate 11. At this time, as is well known, the silicon oxide film 13 also advances in the lateral direction, so that the silicon oxide film 13 is formed by penetrating from the lateral direction into the transistor area covered with the silicon nitride film 14. . Therefore, the area 15' of the silicon single crystal exposed region obtained by later removing the silicon nitride film 14 is the same as the original area 15'!
The area of Sknorrin has also been reduced. In the case of this embodiment, since the penetration is about 1i microns, if a slid lean of 4f microns is used, an exposed area of the single crystal of about 2 microns can be obtained. Next, an N-type single crystal region 15 is formed in the area where the resistor is to be formed as shown in FIG. In the case of this example, the implantation energy was 200 K@V and the dose was 4×l.
After injecting phosphorus with O, 1
It is preferable to perform the heat treatment for 0 hours. This treatment forms an N-type single crystal region with a layer resistance of about 300 Ω and a depth of about 5 microns.

Next, as shown in FIG. 4, after removing the silicon nitride film 14 to expose the surface 15' of the N-type single crystal region 15,
A silicon polycrystalline film 16 with a thickness of 0.5 microns is formed on the entire surface, the surface is thermally oxidized and covered with a silicon oxide film 17 of approximately 0.05 microns, and a photoresist 18 is placed on top of it.
These elements are selectively introduced into the silicon polycrystalline film 11 in a portion of the N region 15 intended for the collector surface region and the silicon polycrystalline film 16 by ion implantation. At this time, implant boron at an energy of 100@V and a dose of lXl0.
It is preferable to inject at Next, the photoresist film 18
After removing the silicon nitride film, a silicon nitride film having a thickness of 0.2i chrome/thickness is formed over the entire surface of the substrate. The silicon nitride film is selectively etched using photoresist, and the silicon nitride film 19 is left to cover the portion of the silicon polycrystalline film 16 where the connecting body is to be formed, as shown in FIG. 5, and the substrate is thermally oxidized. The exposed portion of the silicon polycrystalline film 16 is selectively converted into silicon oxide 20 to form a connected body (in this embodiment, a circuit element,
In this example, it is preferable to perform heat treatment in an oxygen atmosphere at 1000° C. for 6 hours. At this time, the boron selectively implanted into the silicon polycrystal is activated and the layer resistance value of the silicon polycrystal film is approximately 4 KQ/6. 21 is formed.

In addition, as mentioned above, due to the phenomenon of reduction in the area of the ring that occurs during selective oxidation, the width of the nine turns of the resulting interconnected body made of polycrystalline silicon film is approximately smaller than the width of the middle turn of the original mask. I
It decreases by about t chron.

Next, as shown in FIG. 6, the silicon nitride film 19t covering the surface of the N shadow area (in this example, the transistor emitter and collector electrode wiring areas and the diode forming area) of the connector is selectively removed. Then, using the remaining silicon nitride film as a mask, a high concentration of N-type impurity element X is introduced into a desired portion of the connector. In this example, it is preferable to diffuse and introduce phosphorus at 950° C. for 20 minutes by a well-known thermal diffusion method. At this time, phosphorus is introduced into the silicon polycrystalline film in the area intended for N-type, giving it the characteristics of an N-type semiconductor with a layer resistance value of about 20 yen. , in the portion bonded to each planned portion of the collector contact, a lid region is formed in the single crystal region, a base region is the P type single crystal region 21, and an emitter region is the highly doped N type single crystal region 22. A linkage of polycrystalline silicon having P-type or N-type semiconductor properties was formed connecting the regions. Next, unnecessary parts of the PNm junction formed in the connector are short-circuited, and the parts constituting the resistor in the connector, the anode and cand of the diode, and the PN'fiI! In order to increase the electrical conductivity of the electrode/wiring parts other than the parts that constitute the joint, the metallization process described below is performed.
9, leave the desired parts, that is, the parts that maintain the required resistance elements and PN junctions, and remove the insulation coating of other parts to expose the top surface of the connector, and cover the entire surface of the substrate with a metal thin film. A connecting side layer was formed by applying heat treatment. After the heat treatment, the remaining platinum is removed by immersing the substrate in aqua regia to form platinum silicide having a layer resistance of about 544 on the exposed portion of the connector. Finally, as shown in Fig. 8, an insulating film 25t is deposited on the entire surface of the substrate, and openings reaching the metal silicide are formed in desired areas, and connections are made to the metal silicide within these openings. Insulating film 2
5 to form a metal film extending over the desired electrode wiring terminal 101.
~105. At this time, insulators 20 are placed on both sides of the connecting body.
Because of this, the openings can be made outside the width of the connecting body or wider than the width of the connecting body, and therefore a loose margin for alignment of the openings can be provided. Also, the metal film 101
~105 may be used as an external lead terminal or as wiring with other circuit elements, or may be replaced with a connecting body using polycrystalline silicon similar to the first layer connecting body. .

(Diode-1') 4,5.6 is metal crystal 4 layer 24
101.10 connected by a metal film.
2,103,104,105) are extracted to complete the gate circuit shown in FIG.

Next, a second embodiment of the present invention will be described with reference to FIGS. 9 to 11.

This embodiment realizes a CML gate circuit with a Niotta 7 follower as shown in FIG. 9 in a high-density integrated circuit structure.
A portion 20G including transistors la to If in the circuit, and a portion 20G including a resistor R8.degree. R*
a Resistors R8 to R1 including R@ and wiring terminals 201 to
208 (power terminals 201, 202, input terminals 203-2
05, reference voltage terminal 206, output terminal 207.208)
etc. are arranged appropriately and correspond to each other in consideration of connection with other circuits, and parts that are functionally equivalent to each part in the first embodiment are indicated by the same reference numerals as in the first embodiment. There is. The device of this embodiment is manufactured in the same manner as the first embodiment, and each circuit confection, that is, transistors l&~If, is formed on the second side of the P-type monolithic substrate 11.

The portions where the resistors R, , R, are to be formed are covered with a silicon nitride film, and the substrate surface is selectively oxidized, and the oxide film 13 buried on the surface is formed over the portions where each circuit element is to be formed. . Although it is preferable to previously provide a P+ type channel stock/f region 12 on the surface of the substrate surrounding the portion where each circuit element is to be formed, it may be omitted depending on the case. Next, N-type impurity ions are implanted to form an Nff1 region 15 in a portion where an element is to be formed. In order to form the N-type region 15, a thermal diffusion method may be used instead of ion implantation, or
Alternatively, the N-type region 15 in the intended element portion may be formed.

(the surface of the N-type region 15) is exposed over the entire substrate surface, that is, all the exposed single crystal regions and the insulator 1.
A polycrystalline silicon layer 16 is provided covering the surface of 3, and predetermined portions of the polycrystalline silicon layer 16 are doped with Pffi impurities. This doped portion is a polycrystalline silicon portion that is in contact with at least the intended base portions of the transistors la to If and the intended resistive element regions of the resistors R, , R, but the portion in contact with the latter is partially (later oxidized). It is better to reduce the amount of doping (in the parts that are to be converted into products), but it is of course possible to dope parts that will not interfere with later processes. The polycrystalline silicon layer 16 is thermally oxidized except for oxides 20 and 20'.
At the same time, P-type impurities are doped from the polycrystalline layer to the N-temperature single crystal region 15, and in the area where the transistor is planned, a part of the crystalline silicon in the resistance part is also formed into an oxide 20'.
is converted to

Next, a predetermined portion of the remaining polycrystalline silicon layer! After washing and exposing the other parts, N-type impurities are introduced into the polycrystalline silicon layer and the single crystal region surrounding it.

What is exposed here is the polycrystalline cricket portion which is in contact with the portion of transistor 1axlf that is intended to be a bivoltaic wire and the portion that is intended to be a collector contact. As a result, an N-type transistor region 22 is formed in the base region 21 of each transistor, and the collector 1
N+ type=rector contact regions 23 are formed in the narrow area of 5, respectively. 0 then unnecessary PN junctions 31, 32, 33 formed in the connector 16 - Neglected to obtain an open circuit connection between the elements. A layer 24 of a highly conductive material such as metal silicide is then provided on the surface of the polycrystalline silicon layer. This layer 24 may be provided only in the vicinity of unnecessary PN junctions, or may not be provided in connected bodies without unnecessary PN junctions, but in order to reduce signal loss in the connected body, it is necessary to A layer may be provided over the entire required portion, or an insulating film having holes may be provided on the surface as in the first embodiment and the necessary electrical connections may be made through the entire hole, or a second layer may be formed. A wiring layer may also be provided.

In the structure of FIG. 1θ and FIG. 11 formed in this manner, four transistors 11 to ld whose emitters are commonly connected are arranged in parallel, and a polycrystalline conductor linkage serving as a common emitter wiring is connected to each transistor. q! rllll! An emitter 22 is formed at the intersection of the exit plane regions (see also @l 1 Figure A).
. Furthermore, emitter 7 lower transistors l, e1, and f are arranged in parallel with these transistors l&~ld, and the connected body serving as the common collector output terminal of the dirt transistors 1m-1e is connected to each surface exposed region p of the gate transistor. and extends across the exposed surface areas of the output transistors 1 and 1, shorting out the unnecessary PN junctions 32 resulting from the dirt transistors and allowing an ohmic connection of the common collector output to the output transistor base. The same applies to the connection between the collector of the reference transistor ld and the base of the output transistor 1f. (
(See also FIG. 11B above), as a result, each transistor l
The dimensions and spacing of a to 1f are extremely reduced, making it possible to realize high-density integrated circuit structures. In FIG. 10, the connections of each part including the connections of input terminals 203 to 205 are made as in FIG. 9.

In the second embodiment, the resistor R8 included as an example has a width defined by the buried oxide film 13, a length defined by the selective oxide film 20' (in other words, the polycrystalline silicon connections at both ends), and a depth defined by the buried oxide film 13. is a conductor single crystal resistor whose width and depth are defined by the depth of Pfi impurity doped into the Nff1 region 15, and the resistance R1 is defined by the width and depth of the Pfi impurity doped into the Nff1 region 15. Although the lengths are defined by the polycrystalline silicon connectors at both ends, the resistor R1 shown in FIG.

Although the embodiments have been described above, the main part of the present invention is that circuit elements are connected to each other using a connecting body made of polycrystalline silicon as a medium. By eliminating contact holes and incorporating the self-shrinking effect of the pattern, the area of the circuit elements themselves can be reduced and high-density integration can be achieved.

[Brief explanation of the drawing]

Figure WI1 is an electrical equivalent circuit diagram of the circuit to be realized in the first embodiment of the present invention, and Figures 2 to 8 are diagrams showing the structure at each step of the manufacturing method according to the first embodiment of the present invention. ,#
! Figure 3 is a sectional view, Atsushi Figure 2 B and Figures 4 to 8 B.
is a plan view, second factor A and w, A in FIGS. 4 to 8 is a sectional view taken along the line A-A' of B in each figure 0w, and FIG. 9 is a second embodiment of the present invention. FIG. 10 is a sectional view taken along a line of an integrated circuit device according to a second embodiment of the present invention. Main symbols 1, 1 a to 1 f -) transistors in the diagram, 2+3+R
1-R8...Resistance, 4-6...Diode, 11.
...P type child conductor substrate, 12...P°1 channel stopper region, 13...buried oxide film, 15...N type region, 16...polycrystalline silicon layer, 20... Selective oxide film, 20'...Selective oxide film after Pffi doping, 21
... P type region, 22 ... Nff1 emitter region, 2
3...N collector contact region, 24...metal silicide layer. (L)

Claims (2)

[Claims] (1) One main surface of a semiconductor substrate is exposed in a planar shape to form a rectangular shape extending in one direction, and is surrounded by an insulating film buried in the semiconductor substrate, and is a collector region of one conductivity type of a bipolar transistor. is provided so that its entire circumference is surrounded by the insulating film, and the base region of the opposite conductivity type of the transistor is in contact with the insulating film on three sides and the remaining one side is exposed on the one principal surface. an emitter region of one conductivity type of the transistor provided inside the region, the first and second sides of which are in contact with the portion of the insulating film that is in contact with the long side of the rectangle, and the remaining third and fourth sides is provided in the base region in such a manner that it is exposed on the one main surface, and a polycrystalline silicon conductor of one conductivity type is connected between the first and second sides of the emitter region, and is connected to the one direction. A semiconductor integrated circuit device, characterized in that the device extends on the insulating film in a right angle direction. (2) A semiconductor substrate is provided with a plurality of bipolar transistors, the emitter regions of each bipolar transistor are commonly connected by the polycrystalline silicon conductor, and each bipolar transistor is configured according to the aspect described in claim (1). A semiconductor integrated circuit device according to claim (1), characterized in that: