JPS6169149A - Manufacture of integrated circuit device - Google Patents

Abstract

PURPOSE:To increase density and integrate the titled device in a large scale by using a polycrystalline silicon wiring path formed through selective oxidation as a circuit-element connecting body, adding an impurity element through the connecting body and shaping a desired circuit element into a semiconductor substrate. CONSTITUTION:An silicon p type single crystal substrate 11 is thermally oxidized and treated, and the exposed sections of an silicon polycrystalline film 16 are converted selectively into silicon oxides 20 to form connecting bodies consisting of mutually isolated silicon polycrystalline films. Silicon nitride films 19 on the surfaces of n type region prearranged sections in the connecting body are removed selectively, and an n type impurity element in high concentration is introduced to the desired sections of the connecting bodies while using the residual silicon nitride films as masks. Phosphorus is introduced to the silicon polycrystalline film to shape high-concentration n type single crystal regions 22 and 23. Accordingly, contact-holes are removed, and the self-reduction effect of a pattern is adopted, thus reducing the area of circuit element itself, then enabling high-density integration.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a high-density integrated circuit device, and more particularly to a method for manufacturing a high-density semicircular integrated circuit device using a polycrystalline silicon layer.

As is well known, integrated circuit devices have conventionally been constructed by connecting a plurality of circuit elements, each of which is insulated and separated within a semiconductor substrate, with metal wiring paths provided on the surface of the semiconductor substrate. . Here, the connection of the circuit element to the metal wiring path is made through a contact hole, that is, an opening provided in an insulating layer covering the surface of the circuit element.

However, with this conventional fraud method, when aiming for high-density and large-scale integration of integrated circuit devices, it is necessary to create a huge number of minute contact holes, which makes it difficult to realize this. This required extremely advanced fine pattern processing technology.

The goal is to provide a way to send money.

A feature of the present invention is that a polycrystalline silicon wiring path formed by selective oxidation is used as a circuit element connection body, and an impurity element is added through this connection body to form a desired circuit element in a semiconductor substrate. is. Further, at this time, circuit elements can also be formed within the polycrystalline silicon layer. A layer of high conductivity material is provided on the polycrystalline silicon layer formed by the selective oxidation of the present invention. This allows formation of circuit elements defined by the selective oxidation oxide and the layer of high conductivity material in the polycrystalline silicon layer.

Therefore, according to the present invention, the conventional contact
No holes are required and the total number of patterns needed to form the device can be significantly reduced.

Further, according to the present invention, since the pattern self-reduction phenomenon can be applied, a high-density integrated circuit device can be easily obtained without using advanced fine pattern processing technology.

Next, in order to better understand the present invention, examples will be explained below.

A transistor element 1, shown in an electrical equivalent circuit in FIG.
Embodiments in which the present invention is applied to realize a gate circuit configured by connecting a resistor element 2.3 and a diode element 4.5.6 in an integrated circuit structure. I will explain. First, referring to Figure 2, silicon P with a specific resistivity of lO ohm sennameter
A P-type single-crystal region 12 for a channel stopper with a high impurity Q degree is provided in a desired region of a single-crystal substrate 11 in a ring shape surrounding the area where a transistor is to be formed, using a well-known rapid selective diffusion method using a silicon oxide film as a mask. A silicon nitride film 14f is provided on the surface of the area where a transistor is to be formed, a selective oxidation method is applied using this as a mask, and a silicon oxide film 13'' of about 2 micrometers/thick is embedded in the non-element forming area of the semiconductor substrate 11. At this time, as is well known, oxidation of silicon also progresses in the lateral direction, so the silicon oxide film 13 is formed by slightly penetrating into the transistor area covered with the silicon nitride film 14 from the lateral direction. Therefore, the area 15/ of the silicon single crystal exposed region obtained by later removing the silicon nitride film 14 is smaller than the area of the original mask pattern.
Since the penetration is microns, using a 4 micron wide slit pattern will result in a single crystal exposed area about 2 microns wide. Next, as shown in FIG. 3, an N-type impurity element is implanted over the entire surface of the substrate by ion implantation, and heat treatment is performed to form a KIN-type single crystal region in the intended transistor area.
form. In the case of this example, in which a silicon nitride film with a thickness of 0.1 microns was used to form a silicon oxide film with a thickness of approximately 2 microns, the implantation energy was 200 I (eV').

After injecting phosphorus at a dose of t4 x 10ts, 11
It is preferable to perform the heat treatment in a nitrogen atmosphere at 50° C. for 10 hours. This process forms an N-type single crystal region with a layer resistance of about 3000/hole and a depth of about 5 microns.

Next, as shown in FIG. 4, the silicon nitride film 14 is removed to expose a portion of the surface of the N-type single crystal region 15.
A 5 micron thick silicon polycrystalline film 16 is formed on the entire surface,
The surface is thermally oxidized to approximately 0.05 micron silicon oxide II! I bought it for ¥17 and put photoresist 18N on top of it.
The portion where the collector surface region of the shadow region 15 is planned and the portion where the collector lead wiring of the silicon polycrystalline urns is planned are selectively provided in the shape of G, and using the photoresist 18 as a mask, a P-type impurity element is ion-implanted into the silicon polycrystalline film. 16
selectively introduced within. At this time, implant boron with an energy of 100K15V and a dose of fk 1 x 101
It is preferred to inject at 4. Next, photoresist film 1
After removing 8, a silicon nitride film with a thickness of 0.2 microns is formed over the entire surface of the substrate. Perform selective etching of the silicon nitride film using photoresist, and
As shown in the figure, the silicon nitride film 19 is left so as to cover the portion of the silicon polycrystalline film 16 where the connecting body is to be formed, and the substrate is thermally oxidized to selectively oxidize the exposed portion of the silicon polycrystalline film 46. A connected body (including circuit elements, electrodes to the elements, and wiring in this embodiment) made of silicon polycrystalline films separated from each other is formed. In this example, 611 telol in an oxygen atmosphere at 1000°C:
It is preferable to do a hedori U. At this time, the boron that had been selectively implanted into the silicon polycrystal is activated, giving the silicon polycrystalline film the electrical characteristics of a P-type semiconductor with a layer resistance of approximately 4 KQ/s. N-type single crystal region 15
A P-type semiconductor region 21 with a depth of about 0.4 microns is formed by boron diffusion at the bonded portion. Furthermore, as mentioned above, due to the pattern area reduction phenomenon that occurs during selective oxidation, the pattern width of the resulting quintuplet made of silicon polycrystalline films is reduced by about 1 micron compared to the original mask pattern width. do. Next, as shown in FIG. 6, the N shadow area planned portion of the connector (in this example, the transistor emitter and collector electrode wiring planned portion and the diode formation portion)
The silicon nitride film 19 covering the surface of the silicon nitride film 19 is selectively removed, and a high concentration N-type impurity element is introduced into a desired portion of the connector using the remaining silicon nitride film as a mask. In this example, it is preferable to diffuse and introduce phosphorus at 950° C. for 20 minutes by a well-known thermal diffusion method.

At this time, phosphorus is introduced into the silicon polycrystalline film in the N-type portion to give it the characteristics of an N-type semiconductor with a layer resistance value of about 20Ω/hole, and at the same time, this N-type portion becomes the emitter of the single crystal region of the substrate. Phosphorus is also diffused into the single crystal region at the portions bonded to the respective planned portions of the collector contact, forming high concentration N-type single crystal regions 22 and 23 with a depth of approximately 0.4 microns. Through the above manufacturing process, N type single crystal region 15 is used as a golector region, P type single crystal region 21 is used as a base region, and high concentration N type single crystal region 22 is used as an emitter region.
A link body consisting of a PN) transistor and a polycrystalline silicon having P-type or N-type semiconductor properties connected to each region of the transistor was formed. Next, short-circuit unnecessary parts of the PN junctions formed in the connecting body, and short-circuit the parts of the connecting body other than the parts forming the resistor, the anode and cathode of the diode, and the parts forming the PNN junction-S. ! In order to increase the electrical conductivity of the pole/arrangement portion, the metalization process described below is performed. That is, as shown in Figure 7,
Of the insulation coating 19 remaining on the surface of the connector, a desired portion, that is, a portion that retains the necessary resistance element and PN junction, is left, and the insulation coating of the other portions is removed to expose the surface of the connector. A thin metal film is coated over the entire surface of the connector and heat-treated to form metal silicide 24 on the exposed surface of the connector, and then the remaining metal thin film is removed. In this example, a 0.1 micron thick platinum film was deposited and heat treated at 600° C. for 30 minutes in a nitrogen atmosphere to form a platinum silicide layer. After heat treatment, the board is immersed in aqua regia to remove the remaining platinum, and the exposed part of the connector has a layer resistance of about 5r).
10 platinum silicides are formed. Finally, as shown in FIG. 8, an insulating film 25 is applied to the entire surface of the substrate, and openings reaching the metal silicide are formed in desired areas, and connections are made to the metal silicide within these openings. A metal film extending over the insulation PA2i) is formed to form desired electrode wiring terminals 101 to 105.

At this time, since there are insulators 20 on both sides of the connecting body, the openings may be outside the width of the connecting body or may be wider than the width of the connecting body. Therefore, it is possible to provide a loose alignment margin for the openings. Further, the metal films 101 to 105 may be used as external terminals or as arrangement with other circuit elements, or may be replaced with a connecting body using polycrystalline silicon similar to the connecting body in the first layer. Good too. Through the above manufacturing process, a resistive element 2.3 and a PN junction (diode) 4.5 are formed in the single silicon thin film region of the substrate.
．． 6 are connected by a metal silicide layer 24, and each electrode terminal 101, 102, 103, 104, 10 is connected by a metal film.
5 is removed to complete the gate circuit shown in FIG.

As described above with reference to the embodiments, the effect of the present invention is to reduce the area of the circuit element itself by eliminating the conventional contact hole for connecting circuit elements and incorporating the self-shrinking effect of the pattern. The point is that it enables high-density integration.

Therefore, the technical scope of this invention is not limited to the above embodiments, and the rights of this invention extend to all manufacturing methods shown in the claims.

[Brief explanation of the drawing]

FIG. 1 is an electrical equivalent circuit diagram to be realized as an integrated circuit structure according to an embodiment of the present invention, and FIGS. 2 to 8 show ( This is a diagram showing Yuzo, Figure 2: Person, and Figures 4 to 8.
A in the figure is a cross section taken along the line A-A' of B in each figure] A1 No. 3
The figure is a sectional view, and B in FIGS. 2-11 and 4-8 is a plan view. In the figure, 1・・・・・・・・・・・・・・・・・・・・・
Transistor 2.3 ・・・・・・・・・・・・・・・
・Resistance 4.5.6・・・・・・Diode 11・
...... Semiconductor substrate 13.20 ...... Age compound 16...
・・・・・・・・・・・・・・・・・・Polycrystalline silicon layer plate) Agent: Patent attorney Hiro Uchihara. , -1・'th /Ta μ N-J 已 4th figure 5th figure 60

Claims (1)

[Claims] a step of depositing a polycrystalline silicon thin film on one main surface of a semiconductor substrate in which a single crystal region is partially exposed and selectively converting the polycrystalline silicon thin film into an oxide to form a connecting body; A method for manufacturing an integrated circuit device, comprising the steps of: adding an impurity element to the single crystal region through the polycrystalline silicon thin film after forming the polycrystalline silicon thin film; and forming a metal silicide layer on the surface of the connector.