JPS62293963A - Controller for continuously connected power converter - Google Patents

Abstract

PURPOSE:To prevent overvoltage from being applied to one converter only and prevent a rectifying device from being damaged, by feeding gate pulse signal and gate blook siginal to continuously connected power converters, in common. CONSTITUTION:In a phase control section 5, a pulse circuit 5e and a gate blook circuit 5f are arranged. Input to the pulse circuit 5e is fed from gate pulse output sections 5a, 8a, and the output is fed to pulse control sections 5g and 8g in common. Input to the gate block circuit 5f is fed from gate block command 5d, 8d, and the output is directed to the pulse control sections 5g, 8g for input in common. By the gate pulse circuit 5e, gate pulse output for a converter 2a and gate pulse output for a converter 2b are combined with each other, and the output of its logical sum is generated.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention (Object of the Invention) (Industrial Application Field) The present invention relates to a control 211 device that controls the firing angle of two or more cascaded power converters. .

(Prior art) When controlling the firing angle by cascading three-phase Graetz-connected power converters in multiple stages, if some power converters are on and some are off, the power converter may be turned off. Excessive voltage may be applied to the power converter, damaging the built-in control rectifier.

In particular, when two or more stages of converters are connected in series, the output voltage of the converter is generally high, and this voltage is applied to other converters, leading to overvoltage destruction of the controlled rectifying element.

FIG. 4 shows two stages of cascade-connected cycloconverters and their control sections. The main circuit is transformer 1,
It is composed of an anti-parallel converter 2 connected in a three-phase Graetz connection and a load 3 such as a motor. AC power is supplied to the converter 2 via the transformer 1.

The anti-parallel converters 2 are connected in two stages in cascade, and three sets of these are connected to the load 3. The control section includes a current control section 4, a phase control section 5 driven by the output thereof, a 3/2 phase conversion section 6 that detects the output current of the converter 2 and converts it into two phases, and a 3/2 phase conversion section 6 that responds to a frequency reference. The frequency phase conversion section 7 operates in accordance with the above-described structure.

In the current control section 4, the voltage amplitude reference I. r and the current feedback signal I given via the 3/2 phase converter 6
BK is input, proportional-integral control is performed, and a voltage amplitude reference is output.

The current feedback signal I is obtained by separating the current of each phase detected from the contact BK of the load 3 into amplitude components via the 3/2 phase converter 6. The voltage amplitude reference output from the current control section 4 is input to the phase control section 5.

The phase control section 5 inputs this voltage amplitude reference and the voltage phase obtained from the frequency phase conversion section 7, calculates a voltage reference (instantaneous value), converts it into a firing angle signal of Cyrisk, and calculates each voltage reference (instantaneous value). Output to converter 2.

FIG. 5 is a block diagram showing a detailed configuration of the phase control section 5 shown in FIG. 4, one of which is provided for each converter 2. Therefore, in the example of FIG. 4, three phase control sections are provided. The phase control unit 5 includes a gate pulse output unit 5a that outputs a gate pulse at a phase angle according to an input voltage reference, a thyristor selection unit 5b that determines the thyristor risk to be fired in synchronization with the main circuit power supply, and a thyristor selection unit 5b that determines the thyristor risk to be fired in synchronization with the main circuit power supply. a 120° conduction period section 5C that determines the conduction period of
a. Cyrisk selection section 5b.

120° conduction period section 5C and gate block command section 5
The pulse control section 5g inputs the signal from the converter d and outputs a gate pulse to each element of the converter 2a.

Note that similar circuits 8a, 8b, 8C, 8d and 8g are also provided for the other cascade-connected converter 2b.

The converters 2a and 2b are cascade-connected and are equivalently connected to the DC power supply 2.
The configuration is such that C is supplied. The timing of the gate pulses supplied to converters 2a and 2b is pulse controlled.
They do not match because they are each controlled separately by sections 5Q and 8Q.

Therefore, in a state where the current is intermittent, one converter may be turned off while the other converters are conducting. In addition, due to the chronicity of the output current, when switching between forward and reverse control rectifiers,
- When blocking, if the gate blocking circuit of one converter, for example 2a, is ready, the second converter 2b may not yet enter the gate blocking state. In this case, the output j voltage of the converter 2b and the load voltage 2C are applied only to the converter 2a.
will be added and applied.

(Problem to be Solved by the Invention) As described above, since the timings of the gate pulse output (A) and the gate block cannot be precisely matched, an overvoltage occurs in the converter on one side and the converter is configured. There was a problem in that the control rectifier elements such as the Cyrisk were damaged.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a control device for cascade-connected power converters that can prevent damage to control rectifier elements constituting the converters due to the application of overvoltage. shall be.

[Structure of the invention]

(Means for solving the problem) The present invention is included in a phase control means that supplies a gate pulse signal to a power converter, and commonly inputs the outputs of the gate pulse output section that determines the output timing of the gate pulse, A pulse circuit that outputs the logical sum and is included in each of the phase control means and prohibits the output of gate pulses.
The outputs of the gate block command section are connected to each other and the %21!1! It is characterized in that it is provided with a gate block circuit that outputs II.

(Function) By using the OR output of the pulse circuit thus provided and the OR output of the gate block circuit as a common gate pulse signal for the cascade-connected power converters, the gates are always gated at the same timing. If a pulse is output and a gate block signal is output that prohibits gate pulse output to any one converter, gate pulses to all converters will be prohibited. Therefore, it is possible to prevent overvoltage from being applied to one converter.

(Embodiment) The present invention will be described in detail below based on an illustrated embodiment. FIG. Only the corresponding parts are shown.

The same parts as shown in FIG. 5 are denoted by the same reference numerals, and the explanation thereof will be omitted. The control device according to this embodiment differs from conventional devices in that a pulse circuit 5e and a gate block circuit 5f are provided within the phase control section 5. The input of the pulse circuit 5e is given from the gate pulse output sections 5a, 8a,
Its output is commonly supplied to pulse control sections 5g and 8Q.

The input section of the gate block circuit 5f is similarly given from the gate block command sections 5d and 8d, and its output is commonly input to the pulse control sections 50 and 8Q. The gate pulse circuit 5e has a gate pulse output for the converter 2a and a gate pulse output for the converter 2b.
The circuit configuration is such that it synthesizes the gate pulse outputs of the two and outputs the logical sum thereof.

As a result, gate pulse signals are applied to both converters 2a and 2b at the same timing, and it is possible to prevent overvoltage from being applied to one converter due to a shift in pulse output timing.

The gate block circuit 5f also has a configuration that combines the gate block command signal for the converter 2a and the gate block command signal for the converter 2b and outputs the logical sum of the two.

Therefore, when converter 2a enters Goo 1~ block, something strange! ! ! ! If the gate block command signal of the converter 2b is determined and the converter 2b is outputting a gate block command, the converter 2a will gate block, and conversely, if the converter 2b is in gate shift i, the converter 28 will gate block. It will not block and will wait in the same state.

The same is true when conversion "1A2b enters the gate block signal, and such an operation is performed by the gate block circuit 5f. Therefore, the gate block is applied at the same time without the converter 2a advancing or delaying the converter 2b. Therefore, it is possible to prevent overvoltage from being applied to one converter.

FIG. 2 is a waveform diagram for explaining the operation of the pulse circuit 5e. In response to the outputs from the pulse output sections 5a and 8a, the output is output from the pulse circuit 5e without indicating the logical sum thereof. Asymmetric control is used at the timing indicated by A, and the pulse output timings of the converters 2a and 2b are shifted. At the timing of J3 in the 8th section, converters 2a and 2b
Pulses with the same phase angle are given to both, and the reason why the output pulses from the pulse output sections 5a and 8a are slightly shifted is due to the difference in calculation speed J3 and timing of the phase control means of each main converter section. .

FIG. 3 is a waveform diagram for explaining the operation of the gate block circuit 5f. Even if the output signals from the gate block command units 5d and 8d are shifted, the gate block circuit 5f supplies the gate block signals to both converters 2a and 2b at the same timing.

In this way, since gate blocking and gate-released goo 1-pulse output can be performed simultaneously for both converters 2a and 2b, abnormal voltage application to the converters can be prevented.

In the embodiment described above, three-phase Graetz connection power converters are connected in cascade in two stages, but even in the case of converters connected in cascade in three or more stages, the pulse circuit and the It is possible to construct the block 9 circuit in a similar manner by inputting common inputs from the outputs of the gate pulse output section and the gate block command section included in each phase control means.

(Effects of the Invention) As described above in detail based on the embodiments, the present invention includes a pulse circuit and a gate block circuit that commonly supply gate pulse signals and gate block signals to cascade-connected power converters. Because of this provision, pulse output is performed at the same timing, and pulse output is also prohibited.

Therefore, overvoltage is not applied to only one converter. For this reason, it is possible to prevent destruction of the rectifying elements constituting the converter.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the circuit configuration of the current control section of an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation of the pulse circuit of the embodiment, and FIG. 3 is a waveform diagram of the same embodiment. A waveform diagram for explaining the operation of the gate block circuit, FIG. 4 is a block diagram showing the configuration of a general cycle converter and its control device, and FIG. 5 is a detailed diagram of the phase control section of the conventional control device.
FIG. 3 is a block diagram showing the IIIMA configuration. 2.2a, 2b... converter, 5... phase control section, 5
a, 8a...gate pulse output section, 5b, 8b...
Cyrisk selection section, 5c, 8c...1200 Conduction section, 5d, 8d... Gate block command section, 50°8
g...Pulse control section, 5e...Pulse circuit, 5''.
...Gate block circuit. Applicant's agent Sato - Left the party 1 Figure 2 Figure 3

Claims (1)

[Claims] A cascade-connected power converter that controls the firing angle of cascade-connected three-phase Graetz-connected power converters through phase control means configured to output desired gate pulse signals based on a current reference and a frequency reference, respectively. In the control device, a pulse circuit included in each of the phase control means and configured to commonly input the outputs of the gate pulse output section that determines the output timing of the gate pulse and output the logical sum thereof; A gate block circuit is provided which commonly inputs the outputs of the gate block command sections that are included in the gate block and prohibits the output of gate pulses, and outputs the logical sum of the outputs, and the logical sum output of the pulse circuit is combined with the logical sum of the gate block circuit. A control device for cascade-connected power converters, characterized in that the output is used as a common gate pulse signal for the cascade-connected power converters.