JPS62293785A - Manufacture of thin film semiconductor element - Google Patents
Manufacture of thin film semiconductor elementInfo
- Publication number
- JPS62293785A JPS62293785A JP61137522A JP13752286A JPS62293785A JP S62293785 A JPS62293785 A JP S62293785A JP 61137522 A JP61137522 A JP 61137522A JP 13752286 A JP13752286 A JP 13752286A JP S62293785 A JPS62293785 A JP S62293785A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- thin film
- lower electrode
- ito
- semiconductor thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 239000010409 thin film Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 238000005530 etching Methods 0.000 claims abstract description 14
- 230000007547 defect Effects 0.000 claims abstract description 11
- 239000004020 conductor Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 6
- 239000003795 chemical substances by application Substances 0.000 claims description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 8
- 239000011521 glass Substances 0.000 abstract description 3
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 abstract description 2
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 7
- 230000002950 deficient Effects 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000000428 dust Substances 0.000 description 2
- 101150082201 ASIP gene Proteins 0.000 description 1
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000000859 sublimation Methods 0.000 description 1
- 230000008022 sublimation Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
- H01L31/208—Particular post-treatment of the devices, e.g. annealing, short-circuit elimination
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Light Receiving Elements (AREA)
- Electrodes Of Semiconductors (AREA)
- Photovoltaic Devices (AREA)
Abstract
Description
３、発明の詳細な説明 3. Detailed description of the invention
本発明は、アモルファスシリコンなどからなる半導体薄
膜の両面にＭ、極を備えた薄膜半導体素子の製造方法に
関する。The present invention relates to a method for manufacturing a thin film semiconductor element having M and poles on both sides of a semiconductor thin film made of amorphous silicon or the like.
上述のようなＦｉｌ膜半偲体素子において、一方の電極
層上に、例えばプラズマＣＶＤ法により成膜されるアモ
ルファスシリコン（以下ａ −Ｓｉと記す）の薄膜にと
ンホールが存在すると、半導体薄膜上に被着されて他方
の電極層の導体がそのピンホールに侵入して両電極が短
絡してしまう、第３図はそのような状態を示し、ガラス
基板１の上部に形成された下部電極２と上部型ｐｉ６の
間にａ −５ｉＯｐ層３＋ ５Ｊｉ４．ｎ層５を有し
、下部電極２ ニａ−Ｓｉ破壊層７を介して接続される
子端子１１と上部電極６に接続される一端子１２とから
光起電力が取り出される素子において、ａ−３ｉｌｌ！
のピンホール８が上部電極６のＭなどの材料で埋められ
ることにより上、下電極が短絡されている。このような
ピンホール８は、半導体ｙＩＭの成膜室内に発生する粉
塵に起因することが多い、粉塵の発生を防ぐには成膜装
置の保守管理を厳密に行わねばならないが、成膜装置の
保守管理を強化すれば、それだけ成膜装置の操業効率が
低下するという欠点があった。また別の方法として、両
電極層を形成後両電極間に逆バイアスを印加し、欠陥部
分に過剰な電流を流すことにより、欠陥部分の導体を昇
華させて短絡状態を取り除く方法が知られている。とこ
ろがこの方法を実施するには多大の手数を要し、欠陥部
分の大小により昇華させる電流値を変えなければ、半導
体薄膜の正常な部分までも破壊して素子を破損するとい
う欠点があった。In the Fil film semi-solid device as described above, if a hole exists in the thin film of amorphous silicon (hereinafter referred to as a-Si) formed by, for example, plasma CVD on one electrode layer, it will cause damage on the semiconductor thin film. FIG. 3 shows such a situation, where the conductor of the other electrode layer enters the pinhole and short-circuits the two electrodes. and upper mold pi6 between a-5iOp layer 3+ 5Ji4. In an element having an n-layer 5 and in which a photovoltaic force is taken out from a child terminal 11 connected to a lower electrode 2 via a near-Si breakdown layer 7 and one terminal 12 connected to an upper electrode 6, a- 3ill!
The upper and lower electrodes are short-circuited by filling the pinhole 8 with a material such as M of the upper electrode 6. Such pinholes 8 are often caused by dust generated in the film deposition chamber of the semiconductor yIM. To prevent the generation of dust, the film deposition equipment must be maintained and managed strictly. There is a drawback that the more maintenance management is strengthened, the more the operational efficiency of the film forming apparatus decreases. Another known method is to apply a reverse bias between both electrodes after forming both electrode layers, and to flow an excessive current to the defective part, thereby sublimating the conductor in the defective part and removing the short circuit state. There is. However, implementing this method requires a great deal of effort, and unless the value of the sublimation current is varied depending on the size of the defective area, it has the disadvantage that even normal areas of the semiconductor thin film will be destroyed, resulting in damage to the device.
本発明は、上述の欠点を除き、半導体薄膜にピンホール
のような欠陥が生じても両電極間の短絡現象を容易に回
避することのできる薄膜半導体素子の製造方法を提供す
ることを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a thin film semiconductor device that can eliminate the above-mentioned drawbacks and easily avoid short-circuiting between both electrodes even if defects such as pinholes occur in the semiconductor thin film. do.
本発明は、絶縁基板上に下部！極を形成し、その上に半
導体薄膜を積層後、半導体薄膜上より下部電極導体を腐
食するエツチング剤を用いてエツチングを行って、半導
体薄膜に下部電極に達する欠陥が存在するとき欠陥下部
およびその周辺部の下部電極導体層を除去するもので、
欠陥を通ってのエツチング剤によるエツチングによって
欠陥下部およびその周辺部に導体層がなくなるため、上
部電極を形成した際に上部電極導体が欠陥を埋めても下
部電極に接触することがなく、短絡現象が阻止され、上
述の目的が達成される。The present invention has a lower part on an insulating substrate! After forming a pole and laminating a semiconductor thin film thereon, etching is performed using an etching agent that corrodes the lower electrode conductor from above the semiconductor thin film. This removes the lower electrode conductor layer at the periphery.
Etching with the etching agent through the defect eliminates the conductor layer under the defect and its surrounding area, so when the upper electrode is formed, even if the upper electrode conductor fills the defect, it will not contact the lower electrode, resulting in short circuit phenomenon. is prevented and the above objectives are achieved.
以下図を引用して本発明の実施例について説明する。各
図の第３図と共通の部分には同一の符号が付されている
。第１図において、ガラス基板ｌの上にＩＴＯ（インジ
ウムすず酸化物）により透明の下部電極２が形成され、
その上にａ−Ｓｉの９層３，４層４．ｎ層５が順次積層
されている。このような構成において、ａ−３ｉ層にピ
ンホール８が発生した場合、ａ−５ｉｊ！ｉをマスクと
してＩＴＯのエツチング液（塩酸＋塩化第二鉄溶液）に
よりエツチングし、ピンホール８の形状よりやや大きい
部分９が除去されるようにサイドエツチングさせる。
第２図は、この上にＭの蒸着により上部電極６を形成し
、下部電極２とレーザあるいは超音波により破壊された
ａ−３ｉＪｉｉ７を介して端子１１を、上部電極６と端
子１２を接続した状態を示す、このときピンホール８の
下部にはＩＴＯ除去部９が存在するため、ＭとＩＴＯが
接触することなく、短絡が回避できる。この結果ａ
Ｓｉ光電変換素子の良品率が向上する。なお、下部電極
２の上に全面にａ−５ｉ層を成膜し、バターニングする
際表面に被着したレジスト膜は、ａ−ＳｉＦｉのピンホ
ール８の上には存在しないので、レジスト膜が残った状
態でピンホールを通してのＩＴＯのエツチングを行って
もよい。
この方法では、ａ−ｓｔａで覆われた下部電極はほとん
どエツチングされないので、下部１Ｊｉ極の必要部分は
そのまま残り、エツチングによる特性の低下はない。Embodiments of the present invention will be described below with reference to the drawings. The same parts in each figure as in FIG. 3 are given the same reference numerals. In FIG. 1, a transparent lower electrode 2 is formed on a glass substrate l using ITO (indium tin oxide),
On top of that are 9 layers 3 and 4 layers 4 of a-Si. N layers 5 are sequentially laminated. In such a configuration, if a pinhole 8 occurs in the a-3i layer, the a-5ij! Etching is performed using an ITO etching solution (hydrochloric acid + ferric chloride solution) using i as a mask, and side etching is performed so that a portion 9 slightly larger than the shape of the pinhole 8 is removed. In Fig. 2, an upper electrode 6 is formed by vapor deposition of M on this, and a terminal 11 is connected to the lower electrode 2 through an a-3iJii 7 destroyed by laser or ultrasonic waves, and an upper electrode 6 and a terminal 12 are connected. At this time, since the ITO removal part 9 exists below the pinhole 8, the M and ITO do not come into contact with each other, and a short circuit can be avoided. This result a
The yield rate of Si photoelectric conversion elements improves. Note that when an a-5i layer is formed on the entire surface of the lower electrode 2 and buttered, the resist film that adheres to the surface does not exist on the a-SiFi pinhole 8, so the resist film is In the remaining state, ITO may be etched through a pinhole. In this method, the lower electrode covered with a-sta is hardly etched, so the necessary portion of the lower 1Ji electrode remains as it is, and the characteristics are not degraded by etching.
本発明によれば、５Ｘ膜半瑯体素子の良品率の低下の主
因である半４体′ａ膜のピンホールのような欠陥を介し
ての両電極の短絡を、欠陥の下部およびその周辺部の下
部型ｉｆｌ ｉｌ１体を半導体薄膜をマスクとして欠陥
を通してエツチングを行って除去することにより簡単に
阻止することができ、安価で品質の高い素子が得られる
。そのほか、欠陥を通、シてＭとＩＴＯが接触すると電
気化学的にＩＴＯが腐食する現象が起こるが、その現象
も防止されるので信鎖性が向上する。According to the present invention, the short circuit between both electrodes through defects such as pinholes in the semi-quad film, which is the main cause of a decrease in the yield rate of 5 This can be easily prevented by etching and removing the lower part of the lower mold body using the semiconductor thin film as a mask through the defect, and an inexpensive and high quality element can be obtained. In addition, a phenomenon in which ITO is electrochemically corroded occurs when M and ITO come into contact through a defect, but since this phenomenon is also prevented, the reliability is improved.
第１図は本発明の一実施例の工程を示す断面図、第２図
は第１図の工程を経たａ −５ｉ素子の断面図、第３図
はａ −５ｉ素子に生ずる短絡現象を示す断面図である
。
１ニガラス基板、２：下部電極、３：ａＳｉｐ層、４：
ａ−５ｉｉ層、５：ａ−３ｉｎ層、６：上部電極、８：
ピンホール、９：下部電極除去部。FIG. 1 is a cross-sectional view showing the steps of an embodiment of the present invention, FIG. 2 is a cross-sectional view of an a-5i device that has gone through the steps shown in FIG. 1, and FIG. 3 is a diagram showing a short circuit phenomenon that occurs in the a-5i device. FIG. 1 glass substrate, 2: lower electrode, 3: aSip layer, 4:
a-5ii layer, 5: a-3in layer, 6: upper electrode, 8:
Pinhole, 9: Lower electrode removed part.
Claims (1)
おいて、絶縁基板上に下部電極を形成し、その上に半導
体薄膜を積層後、該半導体薄膜上より下部電極導体を腐
食するエッチング剤を用いてエッチングを行って、半導
体薄膜に下部電極に達する欠陥が存在するとき該欠陥下
部およびその周辺部の下部電極導体層を除去することを
特徴とする薄膜半導体素子の製造方法。1) In a method for manufacturing an element having electrodes on both sides of a semiconductor thin film, a lower electrode is formed on an insulating substrate, a semiconductor thin film is laminated thereon, and then an etching agent that corrodes the lower electrode conductor is applied from above the semiconductor thin film. 1. A method of manufacturing a thin film semiconductor device, which comprises etching a semiconductor thin film using a semiconductor thin film to remove a lower electrode conductor layer below the defect and its surrounding area when there is a defect in the semiconductor thin film that reaches the lower electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61137522A JPS62293785A (en) | 1986-06-13 | 1986-06-13 | Manufacture of thin film semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61137522A JPS62293785A (en) | 1986-06-13 | 1986-06-13 | Manufacture of thin film semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62293785A true JPS62293785A (en) | 1987-12-21 |
Family
ID=15200643
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61137522A Pending JPS62293785A (en) | 1986-06-13 | 1986-06-13 | Manufacture of thin film semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62293785A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015522947A (en) * | 2012-06-05 | 2015-08-06 | コミサリア ア レネルジィ アトミーク エ オ ゼネ ルジイ アルテアナティーフＣｏｍｍｉｓｓａｒｉａｔａ Ｌ’Ｅｎｅｒｇｉｅ Ａｔｏｍｉｑｕｅ Ｅｔ Ａｕｘ Ｅｎｅｒｇｉｅｓ Ａｌｔｅｒｎａｔｉｖｅｓ | Method for constructing a type of stack comprising a first electrode, an active layer, and a second electrode |
-
1986
- 1986-06-13 JP JP61137522A patent/JPS62293785A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015522947A (en) * | 2012-06-05 | 2015-08-06 | コミサリア ア レネルジィ アトミーク エ オ ゼネ ルジイ アルテアナティーフＣｏｍｍｉｓｓａｒｉａｔａ Ｌ’Ｅｎｅｒｇｉｅ Ａｔｏｍｉｑｕｅ Ｅｔ Ａｕｘ Ｅｎｅｒｇｉｅｓ Ａｌｔｅｒｎａｔｉｖｅｓ | Method for constructing a type of stack comprising a first electrode, an active layer, and a second electrode |
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