JPS62291166A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62291166A JPS62291166A JP61136616A JP13661686A JPS62291166A JP S62291166 A JPS62291166 A JP S62291166A JP 61136616 A JP61136616 A JP 61136616A JP 13661686 A JP13661686 A JP 13661686A JP S62291166 A JPS62291166 A JP S62291166A
- Authority
- JP
- Japan
- Prior art keywords
- photoresist
- insulating film
- metal layer
- region
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 39
- 229910052751 metal Inorganic materials 0.000 claims abstract description 26
- 239000002184 metal Substances 0.000 claims abstract description 26
- 239000012535 impurity Substances 0.000 claims abstract description 16
- 238000005468 ion implantation Methods 0.000 claims description 25
- 239000000758 substrate Substances 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 13
- 108091006146 Channels Proteins 0.000 abstract description 13
- 150000004767 nitrides Chemical class 0.000 abstract description 12
- 239000013078 crystal Substances 0.000 abstract description 5
- 230000007547 defect Effects 0.000 abstract description 5
- 108090000699 N-Type Calcium Channels Proteins 0.000 abstract description 4
- 102000004129 N-Type Calcium Channels Human genes 0.000 abstract description 4
- -1 atom ions Chemical class 0.000 abstract description 4
- 108010075750 P-Type Calcium Channels Proteins 0.000 abstract description 3
- 150000002500 ions Chemical class 0.000 abstract description 2
- 229910052796 boron Inorganic materials 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
発明の詳細な説明
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特にチャネルス
トッパを有するＣＭＯ８集積回路を含む半導体装置の製
造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device including a CMO8 integrated circuit having a channel stopper.
従来、この種の半導体装置の製造方法、例えばチャネル
ストッパを有するＣＭＯ８集積回路の製造方法は、一般
にチャネルストッパの形成にはイオン注入法を使用する
が、その場合の素子領域を覆うマスクとしては、従来か
ら、減圧Ｄ Ｖ Ｄ窒化膜の厚い膜あるいはホトレジス
トを用いてきた。Conventionally, in the manufacturing method of this type of semiconductor device, for example, the manufacturing method of a CMO8 integrated circuit having a channel stopper, an ion implantation method is generally used to form the channel stopper. Conventionally, thick films of low pressure DVD nitride films or photoresists have been used.
第２図（ａ）〜（ｄ）は従来の半導体装置の製造方法の
第１の例を説明するために工程順に示した半導体チップ
の断面図である。FIGS. 2(a) to 2(d) are cross-sectional views of a semiconductor chip shown in order of steps to explain a first example of a conventional method for manufacturing a semiconductor device.
この第１の例は、先ず、第２図（ａ、）に示すように、
例えばＮ型シリコンの半導体基板１内にＰ型のウェル２
を形成したのち、半導体基板１とウェル２の表面」−に
第１絶縁膜３例えば薄い酸化膜および第２絶縁膜４例え
ば減圧ＣＶＤの窒化膜を形成する。In this first example, first, as shown in FIG. 2(a),
For example, a P-type well 2 is placed in an N-type silicon semiconductor substrate 1.
After forming, a first insulating film 3 such as a thin oxide film and a second insulating film 4 such as a nitride film formed by low pressure CVD are formed on the surfaces of the semiconductor substrate 1 and the well 2.
次に、第２図（ｂ）に示すように、所定の素子領域にの
み選択的に第２絶縁膜４を残し、半導体基板１のｐチャ
ネルＭ ＯＳ Ｉ−ランジスタ（以後ｐＭ ＯＳ Ｔと
称する〉領域およびｐＭＯ８Ｔのフィールド領域にホト
レジスト−７′を形成してｎチャネルＭＯ３）−ランジ
スタ（以降ｎ Ｍ Ｏ８’Ｔ−と称す）のフィールド領
域にＰ型の不純物原子例えばホウ素のイオン注入９を行
ないイオン注入領域１２′を形成する。この時、ｎ Ｍ
ＯＳ Ｔの素子領域は第１絶縁膜３−トの第２絶縁膜
４をマスクとしている。Next, as shown in FIG. 2(b), the second insulating film 4 is selectively left only in predetermined device regions, and a p-channel MOS I-transistor (hereinafter referred to as pMOS T) on the semiconductor substrate 1 is formed. A photoresist 7' is formed in the field region and the field region of the pMO8T, and ion implantation 9 of P-type impurity atoms, for example, boron, is performed in the field region of the n-channel MO3) transistor (hereinafter referred to as nMO8'T-). An implanted region 12' is formed. At this time, n M
The element region of the OST uses the second insulating film 4 of the first insulating film 3 as a mask.
次に、第２図（ｃ）に示すように、ポトレジスＩ・７′
を除去した後、同様に、ｎＭｏ５Ｔ領域及びそのフィー
ルド領域を含むＰ型のウェル２を覆うようにホトレジス
ト８′を形成し、ｐ Ｍ ＯＳ Ｔのフィールド領域に
Ｎ型の不純物原子例えばリンのイオン注入１０を行ない
イオン注入領域１３′を形成する。Next, as shown in Figure 2(c), Potregis I 7'
After removing, a photoresist 8' is similarly formed to cover the P-type well 2 including the nMo5T region and its field region, and N-type impurity atoms such as phosphorus ions are implanted into the field region of the pMOST. Step 10 is performed to form an ion implantation region 13'.
更に、第２図（ｄ）に示すように、ポｉ・レジス１〜８
′を除去した後、第２絶縁膜４をマスクとし′でＬＯＣ
Ｏ３法によりフィールド酸化を行ない、フィールド領域
にフィールド絶縁膜１１として厚い酸化膜を形成すると
共にＰ型のチャネルスＩ−ツバ１２とＮ型のチャネルス
トッパ１３を同時に形成する。この時、ｎＭｏ３Ｔ領域
は第１絶縁膜３及び第２絶縁膜４で覆われている。Furthermore, as shown in FIG. 2(d), Poi Regis 1 to 8
After removing ', the second insulating film 4 is used as a mask, and the LOC is
Field oxidation is performed using the O3 method to form a thick oxide film as a field insulating film 11 in the field region, and simultaneously form a P-type channel I-flange 12 and an N-type channel stopper 13. At this time, the nMo3T region is covered with the first insulating film 3 and the second insulating film 4.
以後、第２絶縁膜４を除去したのち通常の製造工程を経
てＣＭＯ３集積回路を完成する。Thereafter, after removing the second insulating film 4, the CMO3 integrated circuit is completed through normal manufacturing steps.
第３図（ａ）〜（ｄ）は従来の半導体装置の製造方法の
第２の例を説明するために工程順に示した半導体チップ
の断面図である。FIGS. 3(a) to 3(d) are cross-sectional views of a semiconductor chip shown in order of steps to explain a second example of a conventional method for manufacturing a semiconductor device.
この第２の例は、第３図（ａ ）に示すように、先ず、
Ｎ型シリコンの半導体基板１にＰ型のウェル２を形成し
た後、第１絶縁膜３として薄い酸化膜形成し、第２絶縁
膜４として１０００人程度０減圧ＣＶＤの窒化膜を第１
の例よりも薄く形成する。In this second example, as shown in FIG. 3(a), first,
After forming a P-type well 2 on an N-type silicon semiconductor substrate 1, a thin oxide film is formed as a first insulating film 3, and a nitride film of about 1,000 low pressure CVD is deposited on the first insulating film 4 as a second insulating film 4.
Form it thinner than the example above.
次に、第３図（ｂ）に示すように、所定の素子領域上に
ホトレジスト６を形成してホトレジスト６をマスクとし
て、第２絶縁膜４を除去し、ホトレジスト６を残した状
態で、ｎＭｏ８Ｔ領域およびそのフィールド領域にレジ
スト７″を形成してｎＭＯ８Ｔのフィールド領域にＰ型
不純物原子例−５〜
えばホウ素のイオン注入９を行ない、イオン注入領域１
２′を形成する。この時ｎＭＯ３Ｔ素子領域は第１絶縁
膜３．第２絶縁膜４、さらにポトレジス１へ６で覆って
いるためイオン注入のエネルギーは比較的高くすること
ができ、所望のＰ型イオン注入領域１２′を形成する事
ができる。Next, as shown in FIG. 3(b), a photoresist 6 is formed on a predetermined device region, and the second insulating film 4 is removed using the photoresist 6 as a mask. A resist 7'' is formed in the field region and its field region, and ion implantation 9 of P-type impurity atoms, for example boron, is performed in the field region of the nMO8T.
2' is formed. At this time, the nMO3T element region is covered with the first insulating film 3. Since the second insulating film 4 and the photoresist 1 are covered with 6, the ion implantation energy can be relatively high, and a desired P-type ion implantation region 12' can be formed.
次に、第３図（ｃ）に示すように、ホトレジスト７″及
び６とを除去した後に、ホトレジスト８″を所定のパタ
ーンでｎＭＯ８Ｔ及びそのフィールド領域を含むＰ型の
ウェル２の上を覆うように形成し、ｐＭＯ３Ｔのフィー
ルド領域にＮ型の不純物原子例えばリンのイオン注入１
ｏを行いイオン注入領域１３′を形成する。しかしこの
場合、Ｉ）ＭＯ８ＴＯ８上のマスクは薄い酸化股上の１
０００人程人程窒化膜であるため、イオン注入時のエネ
ルギーをあまり大きくできず、前に説明した第１の従来
例の方法より制限された製造条件となる。Next, as shown in FIG. 3(c), after removing the photoresists 7'' and 6, a photoresist 8'' is applied in a predetermined pattern to cover the P-type well 2 including the nMO8T and its field region. ion implantation of N-type impurity atoms, for example, phosphorus, into the field region of pMO3T.
Step 3 is performed to form an ion implantation region 13'. But in this case, I) the mask on MO8TO8 is 1 on the thin oxide crotch.
Since it is a nitride film of about 1,000 yen, the energy during ion implantation cannot be increased very much, resulting in manufacturing conditions that are more limited than those of the first conventional method described above.
更に、第３図（ｄ）に示すように、ホトレジスト８″を
除去して、第２絶縁膜４をマスクとしてＬ ＯＣＯＳ法
によりフィールド酸化を行いフィールド絶縁膜１１とし
て厚い酸化膜を形成すると共にＰ型及びＮ型のチャネル
ストッパ１２及び１３を形成する。Furthermore, as shown in FIG. 3(d), the photoresist 8'' is removed and field oxidation is performed by the LOCOS method using the second insulating film 4 as a mask to form a thick oxide film as the field insulating film 11. Type and N type channel stoppers 12 and 13 are formed.
以降は、第１の従来例と同様のプロセスによりＣＭＯ８
集積回路を完成する。After that, the CMO8 is manufactured using the same process as the first conventional example.
Complete the integrated circuit.
」−述した従来の半導体装置の製造方法は、膜厚の厚い
フィールド絶縁膜の下にチャネルストッパを形成する為
にホトレジスト及び第２絶縁膜である窒化膜をマスクと
して、フィールド絶縁膜である酸化膜に不純物原子が食
われない程度の深さに、イオン注入をしなければならず
、注入エネルギーをある程度大きくしなければならない
。” - The conventional semiconductor device manufacturing method described above uses photoresist and a nitride film, which is a second insulating film, as a mask to form a channel stopper under a thick field insulating film. Ions must be implanted to a depth that prevents impurity atoms from being eaten into the film, and the implantation energy must be increased to a certain degree.
しかし、上述の第１の例では、第２絶縁膜を減圧ＣＶＤ
の窒化膜で形成すると膜厚２０００Å以上ではクラック
が生じ易くなるので１８００人程度以下の膜厚にしなけ
ればならず、従って、イオン注入のエネルギーを低くし
てチャネルストッパを形成しようとするとイオン注入の
ドーズ量を増やすことになりフィールド領域の表面に結
晶欠陥を生じさせるという欠点がある。勿論、ドーズ量
を増やさずにイオン注入をすればチャネルストッパとし
ての充分な不純物濃度が得られない。又、−上述の第２
の例では、Ｐ型の不純物原子をイオン注入する場合には
ホトレジストがマスクとなるので上述のような欠点は無
いが、しがし、次の工程のＮ型の不純物原子をイオン注
入をする場合には第１の例と同様の欠点が生じてしまい
しがも第２絶縁膜の窒化膜の膜厚が第１の例より薄い分
だけ注入エネルギーを低くしなければならず良好な特性
をもったチャネルストッパの形成はより困難になる。However, in the first example described above, the second insulating film is formed by low pressure CVD.
If the nitride film is formed with a thickness of 2000 Å or more, cracks are likely to occur, so the film thickness must be less than 1800 Å. Therefore, if you try to form a channel stopper by lowering the ion implantation energy, the ion implantation will be difficult. This method has the disadvantage that it increases the dose and causes crystal defects on the surface of the field region. Of course, if ion implantation is performed without increasing the dose, a sufficient impurity concentration as a channel stopper cannot be obtained. Also, - the above-mentioned second
In the example above, when ion-implanting P-type impurity atoms, the photoresist serves as a mask, so there is no drawback as described above. However, when ion-implanting N-type impurity atoms in the next step, This method has the same drawbacks as the first example, but the implantation energy must be lowered because the thickness of the nitride film of the second insulating film is thinner than that of the first example. Forming channel stops becomes more difficult.
本発明の目的は、チャネルストッパを形成するためのイ
オン注入条件の範囲が広くかつフィールド領域の表面に
イオン注入による結晶欠陥を生じさせにくい安定した半
導体装置の製造方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a stable method for manufacturing a semiconductor device that allows a wide range of ion implantation conditions for forming a channel stopper and is less likely to cause crystal defects due to ion implantation on the surface of a field region.
本発明の半導体装置の製造方法は、−導電型の半導体基
板に反対導電型のウェルを形成する工程と、前記半導体
基板と前記ウェルとの表面に第１絶縁膜、第２絶縁膜及
び金属層を順次形成する工程と、前記金属層上に所定の
パターンで第１のホトレジストを形成して前記第１のホ
トレジストをマスクとして前記金属層及び前記第２絶縁
膜を順次除去して前記ウェル上及び前記半導体基板上に
それぞれ所定のパターンで前記第２絶縁膜と前記金属層
を残す工程と、前記第１のホトレジストを除去した後に
前記半導体基板上の前記第１絶縁膜の一部及び前記金属
層を覆うようにして第２のホトレジストを形成して前記
ウェル上の前記金属層と前記第２のホトレジストとをマ
スクとして反対導電型の不純物をイオン注入し前記ウェ
ル表面と前記ウェル周辺の半導体基板表面に反対導電型
の第１のイオン注入領域を形成する工程と、前記第２の
ホトレジストを除去した後に前記ウェル上の前記金属層
と前記第１のイオン注入領域上の前記第１絶縁膜との上
に第３のホトレジストを形成して前記半導体基板上の前
記金属層と前記第３のホ）へレジストをマスクとして一
導電型の不純物をイオン注入し前記半導体基板表面に一
導電型の第２のイオン入流領域を形成する工程と、前記
ホトレジスト及び前記金属層を除去して前記第１及び第
２のイオン注入領域上にフィールド絶縁膜を形成すると
共に前記第１及び第２のイオン注入領域をそれぞれ第１
及び第２のチャネルストッパとする工程とを含んで構成
される。The method for manufacturing a semiconductor device of the present invention includes the steps of forming a well of an opposite conductivity type on a semiconductor substrate of a -conductivity type, and forming a first insulating film, a second insulating film, and a metal layer on the surfaces of the semiconductor substrate and the well. forming a first photoresist in a predetermined pattern on the metal layer and sequentially removing the metal layer and the second insulating film using the first photoresist as a mask to form a layer on the well and leaving the second insulating film and the metal layer in predetermined patterns on the semiconductor substrate, and a part of the first insulating film and the metal layer on the semiconductor substrate after removing the first photoresist; A second photoresist is formed to cover the surface of the well, and an impurity of an opposite conductivity type is ion-implanted using the metal layer on the well and the second photoresist as a mask, and the surface of the well and the surface of the semiconductor substrate around the well are ion-implanted. forming a first ion-implanted region of opposite conductivity type in the well; and after removing the second photoresist, forming a bond between the metal layer on the well and the first insulating film on the first ion-implanted region. A third photoresist is formed on the semiconductor substrate, and an impurity of one conductivity type is ion-implanted into the metal layer on the semiconductor substrate and the third photoresist using the resist as a mask. forming a field insulating film over the first and second ion implantation regions by removing the photoresist and the metal layer; each first
and a step of forming a second channel stopper.
次に、本発明の一実施例について図面を参照して説明す
る。Next, an embodiment of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｄ）は本６発明の一実施例を説明する
ために工程順に示した半導体チップの断面図である。FIGS. 1(a) to 1(d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.
この実施例は、第１図（ａ＞に示すように、先ず、Ｎ型
シリコンの半導体基板１内にＰ型のウェル２を形成した
後、半導体基板１及びウェル２の表面上に第１絶縁膜３
として５００人程０の熱酸化膜、第２絶縁膜４として減
圧ＣＶ Ｉ）により成長した１０００人程度０窒化膜さ
らに厚さ１．０μｍ程度のアルミニウム等の金属層５を
順次形成する。In this embodiment, as shown in FIG. membrane 3
A thermal oxide film with a thickness of about 500 as a second insulating film 4, a nitride film with a thickness of about 1,000 grown by low pressure CVI) as a second insulating film 4, and a metal layer 5 of aluminum or the like with a thickness of about 1.0 μm are successively formed.
次に、図１（ｂ）に示すように、素子領域にホトレジス
トを所定のパターンに形成してそのホトレジストをマス
クにして金属層５を、例えばＣＣｆｆ４．ＣＦ、及びＢ
Ｃｌ３の混合ガスを用いて異方性ドライエツチングし、
続いて、第２絶縁膜４の窒化膜をＣＦ４．Ｈ２の混合ガ
スでドライエツチングする。更に、ホトレジストを除去
後、ｐＭＯ３Ｔ領域およびそのフィールド領域にホトレ
ジストアを形成し、金属層５とホトレジスト７とをマス
クとしてｎＭＯ３Ｔのフィールド領域にＰ型の不純物原
子例えばホウ素のイオン注入９を行なう。ここで、ホウ
素のイオン注入エネルギーは３０〜１５０ｋｅＶの間で
自由に選ぶ事ができ、ｎＭＯ３Ｔ領域のマスクとしての
効果は金属層１．０μｍと窒化膜１０００人によって充
分に保証されている。Next, as shown in FIG. 1B, a photoresist is formed in a predetermined pattern in the element region, and using the photoresist as a mask, the metal layer 5 is coated with, for example, CCff4. CF, and B
Anisotropic dry etching using a mixed gas of Cl3,
Subsequently, the nitride film of the second insulating film 4 is coated with CF4. Dry etching with a mixed gas of H2. Further, after removing the photoresist, a photoresist is formed in the pMO3T region and its field region, and ion implantation 9 of P-type impurity atoms, for example, boron, is performed in the nMO3T field region using the metal layer 5 and the photoresist 7 as masks. Here, the boron ion implantation energy can be freely selected between 30 and 150 keV, and the effectiveness of the nMO3T region as a mask is sufficiently guaranteed by the metal layer of 1.0 μm and the nitride film of 1,000 layers.
次に、第１図（ｃ）に示すように、レジスｌ〜７を除去
した後、同様にｎＭＯ３Ｔ領域およびそのフィールド領
域にレジスト８を形成し、ｐＭｏｓ１゛のフィールド領
域にＮ型不純物原子例えばリン乃至ヒ素のイオン注入１
ｏを行なう。ここで、リン乃至ヒ素のイオン注入エネル
ギーは３０〜２゜ＯｋｅＶの間で自由に選べ、ｐ Ｍ
ＯＳ−「領域のマスクとしての効果はｎＭＯ８Ｔの場合
と同様に充分保証される。Next, as shown in FIG. 1(c), after removing resists 1 to 7, a resist 8 is formed in the nMO3T region and its field region, and an N-type impurity atom, for example, phosphorus, is formed in the field region of pMos1. ~ Arsenic ion implantation 1
Do o. Here, the ion implantation energy of phosphorus or arsenic can be freely selected between 30 and 2°OkeV, and pM
The effectiveness of the OS region as a mask is fully guaranteed as in the case of nMO8T.
続いて、第１図（ｄ）に示すように、ホＩ・レジスト８
を除去した後、金属層８をアルミニウムならば熱リン酸
液等でウェットエツチングして除去し、第２絶縁膜４の
窒化膜をマスクにＬＯＣＯ３法を使ってフィールド酸化
を行ないフィールド領域にフィールド絶縁膜１１として
厚い酸化膜を形成すると共にその下にＰ型のチャネルス
トッパ１２とＮ型のチャネルストッパ１３とを同時に形
成する。Subsequently, as shown in FIG. 1(d), the hole resist 8
After removing the metal layer 8, if it is aluminum, it is removed by wet etching with a hot phosphoric acid solution, etc., and field oxidation is performed using the LOCO3 method using the nitride film of the second insulating film 4 as a mask to form field insulation in the field region. A thick oxide film is formed as the film 11, and a P-type channel stopper 12 and an N-type channel stopper 13 are simultaneously formed thereunder.
以後、第２絶縁膜４の窒化膜を除去したのち、通常の製
造工程を経て、ＣＭＯ３集積回路を完成する。Thereafter, after removing the nitride film of the second insulating film 4, the CMO3 integrated circuit is completed through normal manufacturing steps.
以上説明したように本発明は、チャネルストッパを形成
するためのイオン注入工程に使用する素子領域を覆うマ
スクとして、アルミニラ・ム等の金属層を利用すること
により、イオン注入条件の範囲を広くすると共にドーズ
量の増加に伴なって発生する結晶欠陥を防止して良好な
特性のチャネルストッパを有する半導体装置の製造方法
を提供できるという効果がある。As explained above, the present invention widens the range of ion implantation conditions by using a metal layer such as aluminum as a mask to cover the device region used in the ion implantation process to form a channel stopper. In addition, it is possible to provide a method for manufacturing a semiconductor device having a channel stopper with good characteristics by preventing crystal defects that occur as the dose increases.
第１図（ａ）〜（ｄ）は本発明の一実施例を説明するた
めに工程順に示した半導体チップの断面図、第２及び第
３図（ａ）〜（ｄ）はそれぞれ従来の半導体装置の製造
方法の第１及び第２の例を説明するために工程順に示し
た半導体チップの断面図である。
１・・・半導体基板、２・・・ウェル、３・・・第１絶
縁膜、４・・・第２絶縁膜、５・・・金属層、６．７゜
７′、７″、８．８’ 、８″・・・ホトレジスト、１
１・・・フィールド絶縁膜、１２．１．３・・・チャネ
ルストッパ、１２’、１３′・・・イオン注入領域。FIGS. 1(a) to (d) are cross-sectional views of a semiconductor chip shown in the order of steps to explain one embodiment of the present invention, and FIGS. 2 and 3(a) to (d) are cross-sectional views of a conventional semiconductor chip, respectively. FIG. 2 is a cross-sectional view of a semiconductor chip shown in order of steps to explain first and second examples of a method for manufacturing a device. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Well, 3... First insulating film, 4... Second insulating film, 5... Metal layer, 6.7°7', 7'', 8. 8', 8''...Photoresist, 1
1... Field insulating film, 12.1.3... Channel stopper, 12', 13'... Ion implantation region.
Claims (1)
工程と、前記半導体基板と前記ウェルとの表面に第１絶
縁膜、第２絶縁膜及び金属層を順次形成する工程と、前
記金属層上に所定のパターンで第１のホトレジストを形
成して前記第１のホトレジストをマスクとして前記金属
層及び前記第２絶縁膜を順次除去して前記ウェル上及び
前記半導体基板上にそれぞれ所定のパターンで前記第２
絶縁膜と前記金属層を残す工程と、前記第１のホトレジ
ストを除去した後に前記半導体基板上の前記第１絶縁膜
の一部及び前記金属層を覆うようにして第２のホトレジ
ストを形成して前記ウェル上の前記金属層と前記第２の
ホトレジストとをマスクとして反対導電型の不純物をイ
オン注入し前記ウェル表面と前記ウェル周辺の半導体基
板表面に反対導電型の第１のイオン注入領域を形成する
工程と、前記第２のホトレジストを除去した後に前記ウ
ェル上の前記金属層と前記第１のイオン注入領域上の前
記第１絶縁膜との上に第３のホトレジストを形成して前
記半導体基板上の前記金属層と前記第３のホトレジスト
をマスクとして一導電型の不純物をイオン注入し前記半
導体基板表面に一導電型の第２のイオン注入領域を形成
する工程と、前記ホトレジスト及び前記金属層を除去し
て前記第１及び第２のイオン注入領域上にフィールド絶
縁膜を形成すると共に前記第１及び第２のイオン注入領
域をそれぞれ第１及び第２のチャネルストッパとする工
程とを含むことを特徴とする半導体装置の製造方法。a step of forming a well of an opposite conductivity type on a semiconductor substrate of one conductivity type; a step of sequentially forming a first insulating film, a second insulating film, and a metal layer on the surfaces of the semiconductor substrate and the well; and a step of forming the metal layer on the surface of the semiconductor substrate and the well. A first photoresist is formed on the well in a predetermined pattern, and the metal layer and the second insulating film are sequentially removed using the first photoresist as a mask to form a predetermined pattern on the well and the semiconductor substrate, respectively. Said second
a step of leaving an insulating film and the metal layer, and forming a second photoresist so as to cover a part of the first insulating film and the metal layer on the semiconductor substrate after removing the first photoresist. Ion-implanting impurities of opposite conductivity type using the metal layer on the well and the second photoresist as a mask to form a first ion implantation region of opposite conductivity type on the well surface and the semiconductor substrate surface around the well. and forming a third photoresist on the metal layer on the well and the first insulating film on the first ion implantation region after removing the second photoresist, and removing the second photoresist from the semiconductor substrate. ion-implanting impurities of one conductivity type using the upper metal layer and the third photoresist as masks to form a second ion implantation region of one conductivity type on the surface of the semiconductor substrate; and the photoresist and the metal layer. forming a field insulating film on the first and second ion-implanted regions, and using the first and second ion-implanted regions as first and second channel stoppers, respectively. A method for manufacturing a semiconductor device, characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61136616A JPS62291166A (en) | 1986-06-11 | 1986-06-11 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61136616A JPS62291166A (en) | 1986-06-11 | 1986-06-11 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62291166A true JPS62291166A (en) | 1987-12-17 |
Family
ID=15179466
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61136616A Pending JPS62291166A (en) | 1986-06-11 | 1986-06-11 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62291166A (en) |
-
1986
- 1986-06-11 JP JP61136616A patent/JPS62291166A/en active Pending
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