JPS622884A - Dc commutatorless - Google Patents

Abstract

PURPOSE:To form a smoothly varying drive current with a small-scale circuit by combining a slope waveform with a step signal waveform varying in response to the rotating position of a rotor to form a drive signal, and supplying the drive signal to a stator winding. CONSTITUTION:The rotating position of a rotor is detected by a Hall IC 6, and an output signal which stepwisely switches at a level at a step proportional to a drive command current depending upon a voltage or a current supplied externally at every edge of a rotation detection signal is generated by a step controller 500 and a step current generator 1200. The slope waveform and the step current of a period depending upon the edge of a rotation detection signal from a slope generator 1400 are combined by a slope composite circuit 1500 to form a drive signal. The drive signal is supplied through a U-phase drive circuit 1600, a W-phase drive circuit 1700 and a V-phase drive circuit 1900 to stator windings 1-3.

Description

[Detailed description of the invention]

INDUSTRIAL APPLICATION FIELD The present invention relates to a commutatorless motor used under a DC power source. Conventional technology In recent years, DC non-commutated motors have come into widespread use in many audio RRHs, video tape recorders, and even floppy disk devices, and due to their simplicity, they have also been applied to air-cooling fan motors. is expanding. Conventionally, a two-phase or three-phase half-wave drive system or a full-wave drive system has been the mainstream for this type of DC non-commutator motor. Each drive method has its advantages and disadvantages.
For example, a three-phase driving force type requires fewer driving power elements than a two-phase driving force type, but requires a larger number of position detection elements to detect the rotational position of the rotor. By the way 1
1. When compared with those operated under #L-power supply, the two-phase full-wave drive method requires eight power transistors and three Hall elements. In the past, many attempts have been made to reduce the number of position detection elements in a three-phase driving force type, and a representative technique is the one disclosed in U.S. Patent No. 3,577,053 (hereinafter abbreviated as Document 1). ). The above-mentioned document 1 describes that in a three-phase half-wave drive type non-commutator motor, first, second, second, and the like having different light reflectances are disposed on the rotor. Third
A light beam is irradiated onto the identification band, and the reflected light is detected by a light receiving element, whereby changes in the rotational position of the rotor are recognized as three-step changes in the output level of the light receiving element. , a device configured to apply an i1M current to a phase winding depending on its level is shown. In the method shown in the above-mentioned document 1, three-phase half-wave drive is possible using only one position detection element and an identification band for position detection, but due to configuration constraints, the drive form is changed to three-phase half-wave type. limited to. In other words, if the format shown in the above-mentioned document 1 is adopted, only 3 types of detection can be performed per 360° electrical angle, and therefore only 3i1 switching of the energization state to each phase winding is allowed. In order to realize a three-phase full-wave drive force type that requires switching of the energization state in six ways, additional position detection elements and identification bands are required. By the way, in this type of motor, in order to reduce vibrations and torque rise during rotation, it is preferable to make the X-flow liquid supplied to the stator windings sinusoidal.
Publication No. 100088 (hereinafter abbreviated as Document 2) states that since the position detection signal obtained from the Hall element does not have an ideal sine waveform due to various factors, sine wave information is stored in a digital memory in advance. Then, the information in the memory is sequentially read out using the output signal of a frequency generator connected to the motor (generally called the FG multiplied signal), and converted into an analog voltage to create a near-ideal sinusoidal drive current. A DC commutatorless motor is shown. Problems to be Solved by the Invention However, the method shown in Document 2 requires a considerable circuit scale compared to the conventional analog processing method, and also requires a drive that changes smoothly. It also has the disadvantage that the resolution of the digital circuit needs to be considerably high in order to generate current. Means for Solving the Problems In order to solve the above-mentioned problems, the DC non-commutator motor of the present invention uses a predetermined edge of the position detection signal as a reference.
step signal waveform generating means for generating an output signal whose level changes step by step in steps proportional to a drive command current dependent on an externally supplied voltage or current each time a rotation detection signal is received; a slope generation circuit that generates a slope waveform with a period dependent on the arrival period of the edge of the rotation detection signal; a slope synthesis circuit that synthesizes the slope waveform with the output signal of the step signal waveform generation means to generate a drive signal; The present invention is characterized in that it includes a drive circuit that amplifies the drive signal and supplies the amplified drive signal to the stator winding. Operation According to the present invention, with the above-described configuration, it is possible to generate a drive current that changes smoothly with a relatively small-scale circuit configuration, even though digital processing is performed with low resolution. EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings. FIG. 2 shows a developed view of the main parts of a motor configured to carry out the present invention, in which three-phase stator windings 1, 2, .
3 are star-connected to each other, and a permanent magnet 4 mounted on a rotor (not shown) is placed opposite the stator windings 1 to 3. The main part of the permanent magnet 4 is occupied by eight main magnetic poles, and its inner circumference (although not shown in the figure, the inner circumference of the rotor is located above the permanent magnet 4 in Fig. 2). (in which the lower side is the outer circumferential part) includes a first component part 5a that is magnetized to the north pole, a second component part 5b that is not magnetized, and a second component part 5b that is magnetized to the south pole. The third component portion 5C has annular identification bands 5 arranged alternately in the circumferential direction. Further, a Hall IC (an integrated circuit in which a Hall power generator and other circuits are co-located on a chip) 6 prepared as a rotor rotational position detecting element is arranged opposite to the identification band 5. On the other hand, a power generation band in which the main magnetic pole of the permanent magnet 4 is magnetized to 96 poles is provided on the outer circumferential side, and facing the power generation band, a zigzag pattern having power generation element portions at 96 locations diffracted in the radial direction is provided. A power generation winding 7 having a shape is arranged. Furthermore, the lead wires of the stator windings 1, 2.3 are connected to a first power supply terminal U, a second power supply terminal V, and a third power supply terminal W, respectively, and the center point of the star-shaped wire connection is Connected to terminal X. In addition, the Hall IC 6 has a positive side supply! The terminal 6a1 has a negative power supply terminal 6b and an output terminal 6C, and the lead wire of the generator 11 winding 7 is connected to the output terminals 7a and 7b. Now, FIG. 1 shows a block diagram of a direct current gq flow element in one embodiment of the present invention. In FIG. 1, block 10 is the internal wiring of the motor block shown in FIG. 2. In the motor block 10, a current limiting resistor 8 is connected between the midpoint terminal X and the positive power supply terminal 6a of the Hall IC 6.
The negative power supply terminal 6b and the other output terminal 7a of the power generation winding 7 are connected to the rotation detection terminal F. A processing circuit (described later) built in the Hall IC 6 outputs to the position detection terminal P a position detection signal whose level changes in three stages depending on the rotational position of the motor. The distributor 100 distributes the signal lines to three signal lines that are sequentially activated in accordance with the input level, and the outputs of these are subjected to conditional processing by the sequential circuit 200, and the output of the distributor 100 is R
The rotation direction determination circuit 300 uses the rotation direction command signal applied to the EV X element to determine the rotation direction of the motor. Further, the signals appearing at the rotation detection terminal F and the ground terminal G are amplified to a sufficient amplitude by an amplifier 400, and then used as a clock signal for creating timings, and used as a clock signal for generating various energization timings with the rotation direction determination circuit 300. step controller 500 and stator windings 1 to 3
The signal is supplied to a synchronization trigger circuit 600 that determines the timing at which a slope is generated to be added to the energizing current. Furthermore, the output of the sequential circuit 200 is connected to the step controller 500, the synchronous trigger circuit 600, and a mode switching circuit that switches between three-phase quasi-full wave drive and three-phase full wave drive based on the output of the step controller 500. 700, is supplied to an addition/subtraction command circuit 800 that switches between an upward slope and a downward slope, and a heavy metal wave phase switching circuit 900 that performs phase distribution of drive current in three-phase quasi-full wave drive, and the output of the rotation direction determination circuit 300 is , an energization direction setting circuit 100 that sets the energization direction to the stator windings 1 to 3;
0, an energization direction switching circuit 1100 that switches the energization direction based on the output of the energization direction setting circuit 1000, and a current that depends on the error voltage applied to the E terminal and a command signal for accelerating or decelerating the motor. Error signal amplification R51
The output of the step controller 500 is supplied to the mode switching circuit 700, the addition/subtraction command circuit 800, and a step current generation circuit 1200 that generates a step current waveform during full-wave drive. The output of
1jli! to the energization direction setting circuit 1000, the energization direction switching circuit 1100, the error signal amplifier 1300, and the stator windings 1 to 3. It is supplied to a slope generation circuit 1400 that generates a slope to be added to the current. Further, signals are exchanged between the synchronization trigger circuit 600 and the slope generation circuit 1400, and both the output of the slope generation circuit 1400 and the output of the addition/subtraction command circuit 800 are transmitted to and from the half gold wave phase switching circuit 900. Alternatively, the step current output signal outputted from the step current generation circuit 1200 is supplied to a slope synthesis circuit 1500 that adds a slope to the step current output signal, and the output current of the slope synthesis circuit 1500 is supplied to the half-wave phase switching circuit 900 or The step current generation circuit 1200
is superimposed on the output current of On the other hand, an acceleration or deceleration command signal from the error signal amplifier RH 1300 is supplied to the energization direction setting circuit 1000, and the output current from the error signal amplifier 1300 is transmitted to the slope generation circuit 1400 and the half-metal wave phase cutoff circuit 900. and the step current generation circuit 1200
The output currents of the quasi-full wave phase switching circuit 900 and the step current generation circuit 1200 are supplied to the U-phase drive circuit 1600 and the W-phase drive circuit 1700 via the energization direction switching circuit 1100, and It is also supplied to the slope synthesis circuit 1500, and the U-phase drive circuit 160
The main output current of 0 and the main output current of the WtIl drive circuit 1700 are respectively supplied to the U terminal to which the U-phase stator S wire 1 is connected and the W terminal to which the W-phase stator winding 3 is connected, The U-phase drive circuit 1600 and the W-phase drive circuit 170
A part of the output current of 0 is added by a current addition circuit 1800 and supplied to the ■ phase drive circuit 1900, and the output current of the ■ phase drive circuit 1900 is connected to the ■ terminal to which the V phase stator winding 2 is connected. Supplied. In the embodiment shown in FIG. 1, a command signal for stopping and rotating the motor is applied to the J terminal, and this command signal is directly supplied to the iJ1 electrical opening direction setting circuit 00 to stop the rotation of the motor from the outside. In addition to being used to generate a brake signal when a command signal is applied, it is also used to initialize the step controller 500 and the mode switching circuit 700 via the initialization circuit 2000. Further, the amplifier 4
The output signal of 00 is also supplied to the rotation stop detector 2100, and the rotation stop detection! The output signal of H2100 is supplied to the mode switching circuit 700, and when the motor rotation is stopped, the output state of the mode switching circuit 700 is forcibly shifted to the three-phase quasi-full wave drive state. Furthermore, a forward/reverse switching signal for the rotational direction of the motor is applied to the REV terminal, and when the REV terminal is at a low potential, the motor rotates in the forward direction, and when it is at a high potential, the motor rotates in the reverse direction; When the J terminal is at a low potential, the stator winding is not energized, and when the J terminal is at a high potential, the stator winding is energized. Although the present invention does not refer to the motor rotation servo system, it is assumed here that an error voltage is fed back to the error signal amplifier 1300 via the E terminal based on speed information obtained from the F terminal. Now, before explaining the outline of the operation of each part, the operation of switching the energization state to the stator winding of the DC non-commutator motor shown in FIGS. 1 and 2 will be explained. As is clear from FIGS. 1 and 2, in the DC non-commutator motor described as an embodiment of the present invention, the means for detecting the static position of the rotor is an annular type having three types of components. Since the rotor is only provided with the identification band 5 and the only Hall IC 6, only three types of identification can be performed depending on the resting position of the rotor. However, as is well known, 3
If phase full-wave drive is to be adopted, six types of position detection information will be required depending on the stationary position of the rotor. In the DC non-commutator motor shown in Fig. 1, current is applied to all three-phase stator windings 1°2.3 based on the output signal of the Hall IC 6 until the motor rotational speed increases to a certain extent. By supplying an extra current, the starting torque is prevented from decreasing, and the rotational speed of the motor increases, causing the power generation winding 7 to
After obtaining a sufficient signal from the power generating winding 7 and the output signal from the Hall IC 6, a energization switching signal for three-phase full-wave drive is sent to the distributor 100. sequential circuit 2
00. Step controller 500. Synchronous trigger circuit 6
00. Mode switching circuit 700. Addition '$i calculation command circuit 80
0, Quasi-full wave phase switching circuit 9001 Current direction switching circuit 110
0, step IT flow generation circuit 1200. Slope generation circuit 1400. It is configured to be generated within the drive signal generating means configured by the slope synthesis circuit 1500. The principle of switching the drive mode will be explained using FIG. 3. Figure 3A shows each stator winding 1, 2 when the main pole of the permanent magnet 4 is sinusoidally magnetized in the motor structure shown in Figure 2.
．． This figure shows the torque characteristics generated when current is applied to stator windings 1 to 3. Paul IC
6. The rotational torque when the stator side including the power generation winding 7 moves to the right is defined as the positive direction. Characteristic curve ua in Fig. 3 A
is N to the stator winding 1 in Fig. 2 from the U terminal to the X terminal.
The characteristic curve ub represents the torque generated when a current flows through the stator winding l from the X terminal to the U terminal. Also,
The characteristic curve va represents the torque generated when a current flows through the stator winding 2 from the ■ terminal to the X terminal, and the characteristic curve vb represents the torque generated when the current flows through the stator winding 2 from the It represents the torque generated when flowing. Furthermore, the characteristic curve wa represents the torque generated when a current flows through the stator winding 3 from the X terminal to the X terminal direction.
The characteristic curve vAwb represents the torque generated when a current is passed through the stator winding 3 from the X terminal to the X terminal direction. On the other hand, Figure 3C shows the torque generated in the positive direction when any two phases of the star-connected three-phase stator winding are energized.
These curves are expressed as the generated torque ratio in each stator winding shown in Figure A. As is well known, in a three-phase full-wave drive motor, the envelope of these curves is the actual output torque waveform. Become. That is, in FIG. 3C, the characteristic curve wv represents the torque generated when current is applied from the X terminal in the direction of the ■ terminal in FIG. The characteristic curve uw is the torque generated when electricity is applied from the U terminal to the X terminal, and the characteristic curve gvw is ■
Torque generated when electricity is applied from the terminal to the X terminal,
The characteristic curve vu represents the torque generated when electricity is applied from the ■ terminal to the U terminal, and the characteristic curve wu represents the torque generated when electricity is applied from the X terminal to the U terminal. Assuming that the maximum torque generated by each stator winding is 1, in three-phase full-wave drive, energization is switched to each stator winding every 60 degrees electrical angle, so the maximum torque after combining is T1□, minimum torque Ta1l + average torque T I
V I is given by the following equation. In addition, each torque is all expressed as a simple index here. The third diagram shows the output signal waveform of the Hall IC 6 which has already been explained, but when the rotor of the motor is stopped, the position detection information is
6 output signals cannot be used. In order to start the motor using only the three types of position detection information, it is possible to adopt a three-phase half-wave drive mode, but in that case, the star-connected stator windings shown in Fig. 1 can be used. A power switching element is required to directly connect the X terminal, which is the midpoint, to the positive or negative feed line. In the embodiment of the present invention, such inconvenience is solved by the method described below. That is, the Hall IC 6
Corresponding to the three-step level change of the output signal, the section where the output signal is at a high potential is called a first energizing section, the section where the output signal is at a low potential is called a second energizing section, and the section where the output signal is at an intermediate potential is called a third energizing section.
In the first energizing section, the current is passed from the U terminal to the ■ terminal and the X terminal in Figure 2, and in the second energizing section, the current is passed from the ■ terminal to the In the third energization period, 1i17K is performed from the X terminal to the Ui terminal and the ■ terminal. At this time, the composite torque characteristics of the three-phase stator windings 1.2.3 are as shown in FIG. 3B, and the characteristic curve Wuc is i! in the first section. The characteristic curve vc represents the torque generated by energization in the second section, and the characteristic curve wc represents the torque generated by energization in the third section. Therefore, the output torque of the motor when ill power switching is performed at ideal timing is equal to the envelope of the characteristic curve shown in Fig. 3B, and the main winding among the three-phase stator windings is Considering that a current equal to the sum of the two-phase stator winding currents flows, the maximum torque T□2. Minimum torque Tyo, 2. The average torque Tmwt is calculated as follows. Now, if you compare the 3rd formula with the 6th formula, it will be clear that the same average torque can be obtained at startup as in 3-phase full-wave drive, and also by adding an extra power switching element. The starting current can also be saved compared to the case of three-phase half-wave drive. By the way, assuming that the resistance value per l-phase of each stator winding is the same in any drive method, the starting current in three-phase half-wave drive is twice that of three-phase full-wave drive, but this will be explained here. With this driving method, the starting current increases by only approximately 33%. In the following description, this driving method will be referred to as three-phase quasi-full-wave driving, and will be distinguished from three-phase full-wave driving or three-phase half-wave driving. Next, a specific example of the configuration of the main parts shown in the embodiment of FIG. 1 and an outline of its operation will be explained to help explain the overall operation. First, FIG. 4 is a circuit wiring diagram showing a specific example of the configuration of the Hall IC 6, which includes a constant voltage circuit section 61 using a well-known bandgap reference voltage source, etc., and a circuit section 61 formed on a silicon substrate. It consists of a Hall power generator 62 and other signal processing circuit parts. The Hall power generator 62 of FIG. 4 is the identification band 5 shown in FIG.
The potential of one output terminal 62a of the Hall power generator 62 rises when the Hall power generator 62 is facing the N-pole magnetized part.
The potential of the other output terminal 62b decreases. therefore,
Since the collector potential of the transistor 63 falls and the collector potential of the transistor 64 rises, most of the current flowing into the constant current transistor 65 becomes the collector it of the transistor 66. In the circuit shown in FIG. 4, the resistance ratio of the resistor 67 connected to the emitter side of the constant current transistor 65 and the resistor 69 connected to the emitter side of the constant current transistor 68 is set to 3:4. Therefore, if the collector current of the constant current transistor 65 is 4·Io, the collector current of the constant current transistor 68 is approximately 3·Io. Further, the resistance values of the resistor 71 connected to the emitter side of the power receiving transistor 70 and the resistor 74.75 connected to the emitter side of the constant current transistor 72.73, which constitute the positive side current mirror circuit, are equal. Since the resistance value of the resistor 77 connected to the emitter side of the constant current transistor 76 is set to be three times the resistance value of the resistor 71, the collector ``ig'' of the constant current transistor 72 and 73 is , the maximum value of both currents is approximately 3.
■. Therefore, the collector current of the constant current transistor 76 is approximately . becomes. Therefore, 4 of the collector current of the transistor 66 is
3/3 is supplied from the constant current transistor 73, and only the remaining 1/4 is supplied from the first collector 7 of the transistor 78.
8a. At this time, the second collector 78b of the transistor 78 is connected to the load resistor 79 connected to the output terminal 6c. At the same time, a current of Io is also supplied from the constant current transistor 76. Therefore, when the resistance value of the resistor 79 is Ro, a potential of 2.Io.Ro is applied to the output terminal 6c. appear. On the other hand, when the Hall power generator 62 faces the S-wound magnetized portion of the identification band 5, most of the current flowing into the transistor 65 flows through the transistor 80.
, and the first collector 81a and second collector 81b of the transistor 81 also have a collector current of . A current flows, and the current of the second collector 81b is supplied to a current mirror circuit constituted by a transistor 82 and a transistor 83. Therefore, at this time, most or all of the collector it of the constant current transistor 76 flows into the collector of the transistor 83, and the potential of the output terminal 6C becomes zero. On the other hand, when the Hall power generator 62 faces the non-magnetized portion of the identification band 5, the transistors 66, 80
Since the collector currents of the transistors 66 and 80 are almost balanced, all of the collector currents of the transistors 66 and 80 are supplied from the constant current transistors 72 and 73 and the collector currents of the transistors 78
．． 81 becomes zero, and the load resistor 79 receives the constant ti i! ) Only the collector current of the Ranjistaf 6 is supplied, and the potential of the output terminal 6C is I. -Ro
becomes. In this way, the output voltage of the Hall IC 6 changes in three stages depending on the position of the Hall power generator 62 facing the identification band 5. FIG. 5 shows the relative positional relationship between the main magnetic pole and the identification band of the DC non-commutator motor configured as shown in FIGS. 1 and 2, and the changes in the position detection signal obtained from the Hall IC 6. When the relative rotation angle between the identification band 5 provided on the rotor and the hole [C6] provided on the stator changes as shown in mechanical angle or electrical angle in FIG. Correspondingly, the output voltage of the Hall IC 6 changes as shown in FIG. 5A. Next, FIG. 6 shows a specific configuration example of the distributor 100 shown in FIG. 1, in which two types of comparators 110 and 120 having different threshold voltages,
The main part is constituted by the output processing section 130, and output terminals sl, n1 . The potential of zl exclusively shifts to a high potential according to the three levels of potential of the input terminal P. In the circuit shown in FIG. 6, transistors 111 and 112 or transistors 121 and 122 are added to add a Schmitt function to the front two-chip comparator 110 or 120, respectively. FIG. 7 shows the sequential circuit 2000 and rotation direction determination circuit 300 shown in FIG. Step controller 500° synchronous trigger circuit 600. Mode switching circuit 700. Addition/subtraction command circuit 8001 Energization direction setting circuit 1000. Initialization circuit 200
0, the operation of the initialization circuit 2000 will be described first. In the following explanation of the operation of the logic circuit, we will use positive logic, assume that each input/output terminal or each signal line is in an active state when it is at a high potential, and express the state of high potential as "1 degree". The low potential state is expressed as 0. As can be seen from FIG.
RS flip-flop with NAND gates, 4-person NAND gate 2001 and 2-person NAN
The D gate 2002 is configured by the NAND gate 2002, but before the level of the J terminal changes from "0" to "1", the
When the level of one of the input terminals of the gate 2001 is "0", immediately after the level of the J terminal shifts to "1", the output level of the NAND gate 2002 shifts to "0" and the initialization signal is output. is output. This initialization signal is used not only to initialize the step controller 500 and the mode switching circuit 700, but also to initialize the sequential circuit 200 and the rotational direction determining circuit 300 via the mode switching circuit 700. Next, an outline of the operation of the sequential circuit 200 will be explained based on the output signal waveform of the position detection signal shown in FIG. The sequential circuit shown in FIG. 7 has two NAND gates 2 whose input and output terminals are cross-coupled.
01. 202 gate pair and two NANDs whose input and output terminals are each cross-coupled connected.
A pair of gates 203 and 204 and two NAND gates 205 . 206
The main part is composed of. As already explained, the signal waveforms shown in FIG. 5 show the output signals of the Hall IC 6 shown in FIG.
The signal waveforms of C and D are outputted to output terminals nl, by a distributor 100 shown in FIG.
s1. zl (These terminals are input terminals in FIG. 7) and appear on each signal line after t, and the signal waveforms E, F, and G in FIG. 203. 201 and the output signal waveforms of the inverter 207. When the level of J terminal is “0°” or
Immediately after the terminal level shifts from °0 to °1, the output levels of the NAND gates 202 and 204 are forcibly shifted to "B" by the AND gate 704 forming the mode switching circuit 700. Therefore, Immediately after starting the motor, the output level of the NAND gate 203, the output level of the NAND gate 201,
The output level of the inverter 207 is the same as the level of the n1 terminal and the sl terminal +zl terminal, respectively. Now suppose that the Hall IC 6 in Figure 1 has an electrical angle of O in Figure 5.
o, the output level of the impark 207 will be 1°, and the output level of the NAND gates 201 and 203 will be 0°, but the rotor of the motor will not rotate. Starting from the hole I
When C6 faces the N-pole magnetized part of the identification band 5, zl
The level of the i terminal shifts to 0°, and the level of the n1 terminal shifts to "B". However, here, the level of the REV terminal is held at "0", and the motor rotor rotates in the forward direction. It is assumed that the output level of the D flip-flop 301 constituting the rotation direction discrimination circuit 300 is "0". Before the level of the nl terminal shifts to °l°, the output level of the NAND gate 202 becomes 1. Then, the output level of the NAND gate 205 becomes 0° (multiple rows are performed, and the output state of the gate pair formed by the NAND gates 203 and 204 is inverted, so that the output level of the NAND gate 203 becomes 0°). and the NAND gate 2
The output level of the inverter 207 becomes "0°". Due to this change, the output level of the inverter 207 shifts to "0°".
The output level of the NAND gate 204 shifts to l°. When the rotor continues to rotate and the Hall IC 6 reaches the electrical angle position of 180° as shown in Fig. 5, the level of the zl terminal shifts to 1° again as shown in Fig. 5. At this point, the output level of the NAND gate 204 has shifted to 0°, so the output level of the NAND gate 206 does not change, and the output level of the NAND gate 203.
201. The output state of the inverter 207 also does not change. Subsequently, when the level of the sli child becomes "1", since the output level of the NAND gate 206 has become "1" before that, the output state of the gate pair formed by the NAND gates 201 and 202 is inverted. The above NAN
The output level of the D gate 202 shifts to 1°, and the N
The output level of the AND gate 204 changes to "0° f times."In the end, the sequential circuit shown in FIG.
It has a function to reflect input to output. In this way, the 01 terminal and sl terminal in FIG. When a position detection signal as shown in FIGS. 5B, C, and D is supplied to the zl terminal, the NAND gate 203 or the n2 terminal, the NAND gate 201 . The terminals of the inverter 207 or 22 are shown in FIG. 5E. Drive command signals as shown in F and G are output. As can be seen from FIG. 5, when the motor is rotating in the opposite direction, the n1 and sl terminals are connected. The arrival order of the signals supplied to the z1 terminal is nl, zl, 5
1, and the nl and sl signals are swapped. NAND gates 208, 209, 210 in Figure 7
．． 211. The switching circuit 212 is added to allow the sequential circuit 200 to operate under the same conditions regardless of whether the motor rotates in the forward or reverse direction. Next, the rotation direction determination circuit 300 shown in FIG.
The motor rotor is rotating in the forward direction! In the state where it is rotating in the opposite direction to the imaginary one, the n1 terminal. The direction of rotation is determined by utilizing the difference in the order in which the sl and zl terminals shift to the active state, and an overview of this operation will be explained based on the signal waveform diagrams shown in Figs. 8 and 9. . First, the D flip-flop 301 is the AN
While the output level of the D gate 704 is "0", the output level is initialized to be the same as the level of the REV terminal. The signal waveforms supplied to the f1 and nl terminals and the s14 and zl terminals are shown when the motor is rotating in the positive direction, and Fig. 8E shows the output signal waveform of the NAND gate 302 at this time. Yes, there are NAND gates 303゜3 in Figure 8 F, G. H, i J, respectively.
04, 305. 306. 307. 308, M is the output signal waveform of the D flip-flop 301. This is the output signal waveform of the NAND gate 309. In FIG. 8, time 1. The previous sl terminal level is l
During the period when the NAND gate 302 and NAN
The RS flipflop by D gate 310 is reset, the RS flipflop by NAND gate 303 and NAND gate 304 is set, and the RS flipflop by NAND gate 306 and NAND gate 307 is reset. Therefore, after the trailing edge of the signal supplied to the sl terminal arrives, when the leading edge of the FG multiplied signal supplied to the f1 terminal arrives, the output of the NAND gate 305 The level transitions to 0°, resulting in the NAND gate 306 and the RS Frisobufronov due to the NAND gate 307. The output state of the NAND gate 306 is reversed and the output level of the NAND gate 306 shifts to "1". When the trailing edge of the FC signal arrives at time Lz, the output level of the NAND gate 308 shifts to "Oo". Therefore, the output state of the RS flip-flop by the NAND gate 303 and the NAND gate 304 is inverted, and then the NAND gate 306
Then, the RSS flip-flop output state of the NAND gate 307 is also inverted, and the output level of the NAND gate 308 returns to 1° again. The N at time t2
The D flip-flop 301 is triggered by the transition of the output level of the AND gate 307 to "1", and the output level of the N A N D gate 302 at the time of triggering is
Since it is 0°, the D flip-flop 301
The output level of the D flip-flop also becomes "0". The same operation is repeated from time t to time t4 or from time t to time t, and as long as the motor rotor is rotating in the forward direction, the D flip-flop Pu 301
If the output level of becomes 0° and a command signal for forward rotation is given through the REV terminal at this time, then
Since the output level of NAND gate 311 becomes °0°, the output level of NAND gate 309 becomes °1. ° becomes On the other hand, when the rotor of the motor is rotating in the opposite direction, the signal waveforms of each part of the rotation direction determination circuit 300 in FIG. 7 become as shown in FIG. 9, and at time t2, the D flip-flop 301 is triggered. Since the output level of the NAND gate 302 immediately before the rotation is always 1°, the output level of the D flip-flop 301 is also always 1', and a command signal for positive rotation is given to the RE V Q element. If so, the output level of the NAND gate 309 becomes "Oo", and an output signal indicating that the rotation is in the opposite direction to the command is sent to the eni child. Note that since the output signal of the D flip-flop 301 is directly applied to the dr terminal, the level of this terminal becomes 0° when the motor rotor is rotating in the forward direction, and when the motor rotor is rotating in the reverse direction. When rotating in the direction, it becomes °l゛. Next, an outline of the operation of the step controller 500 shown in FIG. 7 will be explained based on the signal waveform diagram shown in FIG. 10. FIGS. 10A and 10B show the signal waveforms of the output signal of the NAND gate 201 and the FC signal supplied to the "l" terminal, respectively, and FIGS. 10C, D, and E. The output signal waveforms of NAND gates 501, 502, 503, and 504, 505 are shown respectively.Furthermore, H, I, J, L, and M in FIG. Figure 10 shows the output signal waveforms of the T flip-flops 507, 508, 509 and NAND gates 510, 511 that constitute the circuit, and Figure 10 N and O show the output signal waveforms of the NAND gates 512 and 513, respectively. 1O terminals a, b, c, d, e, and f are respectively the u m O terminal and uml terminal in Fig. 7. They show the output signals appearing at the um2 terminal, um3 terminal, um4 terminal, and um5 terminal. Figure 10 g, h, i
, j are the USL terminals in FIG. 7, respectively. The output signals appearing at the us2 terminal, us3 terminal, and us4 terminal are shown in Fig. 1O. n, o, and p are the wmO terminal, Wml terminal, wm2 terminal, wm3 terminal, and wm4 terminal in FIG. 7, respectively. This shows the output signal appearing at the wm5 terminal, and the first
Figure 0 q, r, s, t are the ws1 terminal in Figure 7, respectively.
It shows output signals appearing at the ws'l terminal, ws3 terminal, and ws4 terminal. At the time in Figure 10, the NAND gate 514°51
5.516 is "1", the output level of the NAND gate 517 is 0, and the leading edge of the output signal of the NAND gate 201 has already arrived. At time t, f
When the leading edge of the FC signal supplied to one terminal arrives, the output level of the NAND gate 501 shifts to 0, and as a result, the output level of the NAND gate 502 shifts to 1 and the output level of the NAND gate 501 shifts to 0. 51
The output level of No. 5 shifts to 0° and this state is maintained. When the trailing edge of the FC signal arrives at time (2), the output level of the NAND gate 501 becomes 1.
Returning to ゛, the output level of the NAND gate 503 is “0”.
Therefore, the output level of the NAND gate 504 shifts to 1°, and the output level of the NAND gate 516 shifts to 1°.
The output level shifts to “0”. Time

[When the leading edge of the FC signal arrives again, the output level of 505 changes to
As a result, the output level of the NAND gate 517 shifts to "0", so the output level of the NAND gate 514 shifts to "0", and the output level of the NAND gate 517 shifts to "0".
The output level of the gate 515 shifts to "1". As a result, the output level of the NAND gate 502 becomes "0", the output level of the NAND gate 516 becomes "1", and then the output level of the NAND gate 504 shifts to "1". Since the output level becomes °O'', the NAND gate 50
The output level of the NAND gate 201 returns to "l" and the series of operations ends. Eventually, from time t to time t3, the output signal of the NAND gate 201 and the FC signal supplied to the fli terminal are as shown in FIGS. When the change occurs as shown in , time t2
to time t, the NAND gate 516
The output level of T flip-flop 50 becomes “0°”.
7 is reset and at the same time T flip-flop 508 . 509 cents,
The output state of the RS flipflop composed of the NAND gate 510 and the NAND gate 519 is also inverted, and the output level of the NAND gate 51O becomes "L".
Move to ゛. That is, the output signal of the NAND gate 504 is transmitted to the T-flip block 507 . 508. 509 and the RSS flip-flop, and the output of this counter is briscented to [111(l]) at time t2, and this briscent continues until time t. When the trailing edge of the FC signal arrives at time t4, the 4-bit counter starts counting down again, but at time t14, when the count value of the counter reaches [10001], the output level of the NAND gate 520 becomes "0". Then, NAND gate 5
11 and the NAND gate 521 is inverted, and the output level of the NAND gate 511 shifts to 0°. the result,
The NAND gate 510 and the NAND gate 519
The output state of the RS flip-flop is also inverted, and the output level of the NAND gate 510 shifts to 0. 509 cents. Therefore, the output of the 4-bit counter is preset to [01101 at time t14, and when the leading edge of the FC signal arrives again at time [1°], the output level of the N A, N D gate 511 becomes "
1'', the T flip-flop 508 and the T
The cent on flip-flop 509 is released at time tl.
From &, the 4-bit counter resumes down-counting operation. After that, time t! The down-count operation continues until the NAND gate 516 generates the preset signal again at time t0, but when the leading edge of the FG double signal arrives at time t0, the same operation as at time t is repeated. In this way, the count value of the 4-focus counter is expressed in decimal notation during one period of the position detection signal, 14, 13, .
12.11.10. 9. 6. 5. 4. 3.
If this counter is considered as the LSB output of the virtual counter, the number of bits of the counter will be 5, and the count value will be 1 of the position detection signal. During the period, in decimal notation, 29
．． 28.27.26.25.24.23.2221, 2
0.19.18.13.12.11.10. 9. 8
．． It decreases in the order of 7°6.5, 4.3.2. On the other hand, NAND gate 522. 523. 524.
525°526, 527. 528. 529.
530 constitutes a decoder that decodes the output of the lower 4 bits of the 5-bit virtual counter. Said NAND
Gate 522 outputs the lower 4 bits of the counter when [11
00], the output level becomes “0°,”
The output level of the NAND gate 523 becomes "0°" when the output of the lower 4 bits of the counter becomes [1011] or [1010], and the output level of the NAND gate 524 becomes "0°" when the output of the lower 4 bits of the counter becomes [1010].
The output level of the NAND gate 525 becomes "0" when the output of the lower 4 bits of the counter becomes [1001] or [1000]. and the NAND gate 5
26, when the output of the lower 4 bits of the counter becomes [1000], its output level becomes 0, and the NA
The ND gate 527 outputs the lower 4 bits of the counter [
0110], the output level of the NAND gate 528 becomes 0, and when the output of the lower four pins of the counter becomes [0100], the output level of the NAND gate 528 becomes 0. The output level of the lower 4 bits of the counter becomes 0" between [00111 and [00013], and the output level of the NAND gate 5 becomes 0".
30, when the output of the lower 4 bits of the counter becomes [00101, its output level becomes 0°. These decoders are used for the purpose of generating interval signals for creating step current waveforms.
It is also used to create the signal waveform shown in Figure 10 and the signal waveform shown in Figure 10. That is, at time t, the output of the 5-bit virtual counter becomes [11100], so the NAND gate 5
The output level of NAND gate 531 shifts to 0°, which causes the output level of NAND gate 531 to shift to 0°,
Subsequently, the output level of the NAND gate 532 shifts to "1", and as a result, the output level of the NAND gate 513 shifts to "0". At time t's, the output of the 5-bit virtual counter is [011001, so the NA
The output level of the ND gate 522 shifts to "0", but
This time, the output level of the NAND gate 533 shifts to "0", and then the output level of the NAND gate 513 shifts to "B", and as a result, the output level of the NAND gate 532 shifts to "0".
The output level of the NAND gate 5 shifts to "O". Furthermore, at time i11, the output of the 5-pin virtual counter becomes [101001, so the NAND gate 5
The output level of NAND gate 534 shifts to "0", which causes the output level of NAND gate 534 to shift to "0",
Subsequently, the output level of the NAND gate 535 shifts to "1°," and as a result, the output level of the NAND gate 512 shifts to "0°." Even at time tzi, the output of the 5-bit virtual counter reaches [00100]. Therefore, the output level of the NAND gate 528 shifts to "0", but this time the output level of the NAND gate 536 shifts to "0", and then the output level of the NAND gate 512 shifts to "1". death,
As a result, the output level of the NAND gate 535 is
Move to 0°. Also, the output terminal umQxum5 in FIG. usl P-
us4. wmQ ~wm5. The interval signals shown in FIGS. 10a-t are outputted to wslA-ws4, and a method of generating these interval signals will be explained. First, the NAND gate 528. is connected to the umo terminal and the wmQ terminal. The same signal waveform as the output signal of 522 is sent out, and these are used as they are as signals for the minimum value section of the step current waveform. Also, u m 5 terminal, w
The inverted output signals of the NAND gates 524 and 527 are sent to the m5 terminal, and these are used as signals for the maximum value section of the step current waveform. Other section signals are NAND gates -537, 538
, NAND gate 539°540, NAND gate 54
1. 542□NAND gate 543. 544.
NAND gate 545. 5 composed by 546
For example, the output signal of the NAND gate 537 is used for the interval signal u m 4, which is generated by combining the output signals of the RS flip-flops and the output signals of the T flip-flops 1507 to 509, and the output signal of the NAND gate 537 is used for the interval signal us3. The output signal of the T flip-flop 509 is used,
The output signal of the NAND gate 541 is used for the section signal wm2, and the output signal of the NAND gate 539 is used for the section signal wS3. Next, the operation of the mode switching circuit 700 shown in FIG. 7 will be explained. The mode switching circuit 700 has D flip-flops 701 and N
AND gate 702. Inverter 703. AND gate 704. 705. It is composed of a NAND gate 706. If the output level of the D flip-flop 701 is "0" while the level of the J terminal is 0, the initialization circuit 200 is activated immediately after the level of the J terminal shifts to 1.
The output level of the NAND gate 2002 that constitutes 0 is “
Since the angle shifts to 0°, the output level of the D flip-flop 701 is 1° when the motor is started. As the rotational speed of the motor increases, the FG times signal is supplied to the fli element, which causes the step controller 500 to start normal operation, and the NAND gate 51
6, the counter is regularly updated, and at the midpoint between time t0 and time [, in FIG.
When the leading edge of the output signal 01 arrives, if the output level of the NAND gate 529 constituting the step controller 500 has shifted to 0°, the output level of the D flip-flop 701 has shifted to 0°. The output signal of this D-flip flow block 701 is sent to the md terminal as a mode switching signal, and is also supplied to a synchronization trigger circuit 600, an addition/subtraction command circuit 800, and an illll same direction setting circuit 1000. Note that when the level of the md terminal is "0" When it is "lo", it is in half-wave drive mode, and when it is "lo", it is in full-wave drive mode. Further, the output signal of the NAND gate 702 is sent to the bk terminal, but the output level of the NAND gate 702 is such that the level of the JQ terminal is 0°, and the
When the output level of the buffer flop 701 reaches "1", it becomes "0", and this output is sent to the U-phase drive circuit 1600, the W-phase drive circuit 1700, and so on via the current direction switching circuit 1100.
It is used for the purpose of causing the v-phase drive circuit 1900 to feed power to the hole C6 in only one direction. The AND gate 704 initializes the sequential circuit 200 and the rotation direction determination circuit 300 when the initialization circuit 2000 sends out an initialization signal or when the NAND gate 702 sends out an output signal, and the AND gate 705 When the circuit 2000 sends an initialization signal or when the rotation stop detector 2100 shifts the level of the qt terminal to "1", the D flip-flop 701 and the step controller 500 are initialized. The operation of the command circuit 800 will be explained with reference to the signal waveform shown in Fig. 11. Fig. 11 shows the step current waveform during full-wave drive and the three-phase drive created based on this step current waveform. FIG. 11 is a signal waveform diagram showing the generation process of a flow waveform, and the signal waveforms in FIGS. 11A and B are the same as the signal waveforms in FIGS. 10A and B, respectively; The signal waveforms shown in FIG. 10H1[, J, and K are the same as those shown in FIG. The symbols written on the top of the signal waveform are hexadecimal representations of the count values of the lower 4 pins of the 5-bit hypothetical counter described above.Furthermore, G and H in FIG.
NAND gate 543 and NAND gate 545 in the figure
11 is the output signal waveform of the slope generation circuit 1400 of FIG. 1, and FIG.
K, N, and 0 are all output signal waveforms of the step current generation circuit 1200 in FIG.
is a signal waveform generated inside the slope synthesis circuit 1500 in FIG. 1, and M in FIG. Q is the drive current waveform supplied to the U-phase drive circuit 1600 and the W-phase drive circuit 1700 in FIG.
Figures R and S are the signal waveforms of the ii1 electric direction setting circuit 1000 supplied to the uli and wl terminals in Figure 7, respectively, and T and U in Figure 11 are the waveforms of the current addition circuit 1800 in Figure 1. This is the drive current waveform of the ■ phase created as a result. The current waveform of FIG. 11M is the first waveform of the current waveform of FIG. 11J generated from the step current generation circuit 1200 of FIG.
It is obtained by synthesizing the current waveform shown in FIG. Add the current value of the 11th chart limited by the current value of FIG. 11 to the current value of FIG.
By subtracting the current value in Figure 11 limited by the current value in Figure 11 from the current value in Figure J,
It creates a current waveform. The addition nx command circuit 800 has a function of sending these addition/subtraction command signals to the slope synthesis circuit 1500, and the time for creating the U-phase drive fJ] current waveform shown in FIG. 11M. From t to time tl? section signal up to,
Or when'i'lt I? As the section signal from 111Lz to 111Lz, the NAND gate 543 . 544 is used to generate the W-phase driving waveform shown in FIG. 11Q.
As the interval signal up to s, the step controller 500
The output of the RS frinbu fromb (no. 8 is used) by the NAND gates 545 and 546 that constitute the However, when the level of the mdi terminal is "0", the output signal of the NAND gate 201 constituting the sequential circuit 200 is sent to the ua terminal, and the n2Q signal is sent to the Wa terminal. The same output signal as the signal sent to the child is sent out.Next, when the level of the 'a power direction setting circuit 1000 and the md terminal is "1 degree", that is, when it is in a full-wave drive state, The signals in Figures 11R and 11S are
The energization direction switching circuit 1 shown in Fig. 1 is connected via the l terminal and the wl terminal.
On the other hand, when the level of the md terminal is "0°," a signal whose level is unrelated to the rotational position of the motor rotor is sent to the u1 and wl terminals. Depending on the levels of the dr, en, and dn terminals, the phases of the signals sent to the ul and wl terminals are inverted as shown in Table 1. First, the NAND gates 1001.1002.1003.
A switching circuit constituted by 1004, 1005, and 1006 switches the output signal of the NAND gate 512 constituting the step controller 500 to u when the motor is rotating in the forward direction and the level of the dr terminal is 0°.
The output signal of the NAND gate 513 is sent to the W
1 terminal, but the motor is rotating in the opposite direction and d
When the level of the r terminal is 1", the NA
The output signal of the ND gate 512 is sent to the W1 terminal, and the output signal of the NAND gate 513 is sent to the u1 terminal. This corresponds to the switching operation between the 81 signal and the 01 signal in the sequential circuit 200 depending on whether the rotation direction of the motor is forward or reverse. Note that by exchanging the position detection signals in the sequential circuit 200, the leading edge of the signal waveform in FIG. 11A is always magnetized to the N pole of the identification band 5 in FIG. For example, even if the width of the non-magnetized portion of the identification band 5 is not uniform due to variations in magnetization, the three-phase After shifting to full-wave drive, a drive signal with a uniform width will be distributed to each phase of U, V, and W in Fig. 1, and the timing of starting energization will also change when switching the rotation direction. will not shift. Further, when the level of the md terminal is "0", the output level of the NAND gates 1003 and 1006 shifts to 1' regardless of the output of the NAND gates 512 and 513. The output signal is inverter 1007. NAND gate 1008.10
09. A first exclusive OR circuit constituted by AN'D gate 010, and an inverter 1011. N
AND gates 1012, 1013. AND gate 10
It is transmitted to the u1 terminal and the Wl terminal through the second exclusive OR circuit configured with 14 days, but these exclusive OR circuits are connected to the output level of the NAND game (1015)
When the angle is 0°, the input signal is transmitted as is, and the NAN
When the output level of the D gate 015 is 0, the phase of the input signal is inverted and transmitted. Table 1 shows the output level ex of the NAND gate 1015.
This shows the input conditions that result in a negative value. Note that the dn terminal is supplied with an acceleration/deceleration command signal from the error signal amplifier 1300 in FIG. 1, as will be described later.
When the deceleration command is supplied, the level shifts to 1°. In Table 1 a), the level of the J terminal is 1',
Moreover, the motor rotates in the positive direction, and the error signal amplifier 1
300, the deceleration command is sent and the level of the 6-pin terminal becomes “
When the level shifts to 1', the output level of the NAND gate 1015 shifts to 1' in order to decelerate the motor. In addition, in Table 1 b), when the rotation direction mismatch signal is sent while the motor is rotating in the forward direction and the level of the en terminal shifts to °0°, the output level of the NAND game [015] In Table 1 C), the output level of the NAND gate 1015 also changes when the acceleration command is sent from the error signal amplifier 1300 with the motor rotating in the opposite direction. 1, the i, 1% i direction setting circuit 1000 operates to either rotate the motor in the opposite direction or maintain rotation in the opposite direction. Furthermore, in Table 1 d), even when the level of the J terminal is 0' and the motor is rotating in the forward direction, the output level of the NAND gate 1015 shifts to 1'; This is a function added for the purpose of causing the motor to temporarily generate reverse torque to quickly stop the motor when a rotation stop command signal is supplied from the outside during rotation in the forward direction. Table 1 Next, the synchronous trigger circuit 600 in FIG. 7 sends out a trigger signal for generating a sawtooth wave to the slope generation circuit 1400 in FIG. 1 via the x2 terminal, but this trigger signal is , When the level of the md Oi terminal increases to "1", it is synchronized with the leading edge and trailing edge of the FG double signal supplied to the "1 terminal", and the level of the md terminal becomes "0". When there is a sequential circuit 20
It is synchronized with the leading edge of the position detection signal 311 supplied from 0 to 311. First, when the level of the mdi terminal is 1° and the level of the xi terminal to which the return signal from the slope generation circuit 1400 is supplied is 0°, when the trailing edge of the FG signal arrives, the NAND gate ) The output level of 601 shifts to 0, causing the level of the X2 terminal to shift to "lo," but when a return signal is sent from the slope generation circuit 1400 and the level of the
RS by AND gate 602 and NAND gate 603
Since the output state of the flipflop is inverted and the output level of the NAND gate 603 shifts to 0°, the output level of the NAND gate 601 also returns to 1°.Furthermore, when the leading edge of the FC signal arrives, the NAND
The output level of D gate 604 shifts to 0° and becomes X2.
The level of the terminal shifts to "1", but when the level of the xl terminal shifts to "1", the NAND gate 605 and NA
Since the output state of the RS buffer 7 by the ND gate 606 is inverted and the output level of the NAND gate 603 shifts to 0, the output level of the NAND gate 601 also returns to "lo". -4, m d Q When the child level is “0°,” NA
ND game) 607. 608. FC signal and NAN that constitute the sequential circuit 200 by a switching circuit based on 609
The output signal of the D gate 201 is switched so that the NA
ND game) At the leading edge and trailing edge of 201, the NAND gate 601 and the NA
The output levels of the ND gates 604 respectively shift to "0°" and the level of the X2 terminal shifts to "1", and
At the leading edge of the output signal of the NAN gate 206 constituting the sequential circuit 200, that is, at the trailing edge of the position detection signal sent to the z2 terminal,
The output level of the AND gate 610 shifts to °l, and a return signal is sent from the slope generation circuit 1400 to
When terminal (7) L/ to /l/ moves to °l°, the NA
ND gate 602 and the NAND gate 6o3
S flipflop or the NAND gate 605
and the RS flimp flop by the NAND gate 606 or the NAND gate 611 and the NAND gate 61
2, the output state of the RS flip-flop is inverted to the NAND gate 601 or the NAND gate 6.
04 or the output level of the NAND gate 610 also returns to "1". Next, FIG. 12 is a circuit connection diagram showing a specific example of the configuration of the error signal amplifier 1300. An error voltage for control l is supplied, and when its value becomes higher than the voltage of 1/2 of the power supply voltage Vcc obtained by resistors 1301 and 1302 with the same resistance value, the motor is accelerated, and the reverse The motor is decelerated when the motor becomes low.The md terminal is the terminal to which the output signal of the mode switching circuit 700 shown in FIG. In the case of three-phase full-wave drive, it becomes "lo". Also, the rotational direction mismatch signal from the rotational direction discrimination circuit 300 shown in FIG. 1 or FIG. 7 is supplied to the en terminal, and the level becomes 0°. At times, the transistor 1303 is turned on and is configured to substantially increase the speed error voltage to its maximum value in the deceleration direction.As shown in FIG.
Tora 7 Jista 1306.130? , 1308. Resistance 1309. Tora 7jista 1310.1311. Resistance 1312.1313. Diodes 1314, 1315 constitute an absolute value amplifier, and input dividing resistors 1304.
The resistance ratio of 1305 is set to 19 to achieve a wide input dynamic range. The output current of this absolute value amplifier is passed through the diodes 1314 and 1315 to the transistors 1316, 1317, and 131B. 1319, resistors 1320, 1321, 1322, and the output current of transistor 1318 is supplied to a first current mirror circuit constituted by resistors 1320, 1321, 1322, and transistors 1323, 1324, 1325, 1326, . resistance 13
27.1328.1329, and the transistor 131
The output t[ of 9 is the transistor 1330.1331.13
32 is supplied to a third current mirror circuit constituted by 32. The transistors 1325.1326.
The output current of 1332 is supplied to the sfl terminal and the sf terminal 5C, respectively, but the level of the md terminal is
When the transistor 1333 is turned on, that is, in full-wave drive, current is supplied only to the cf terminal, and on the other hand, when the level of the md terminal is 0°, the transistor 1333 is turned on and current is supplied only to the cf terminal. is in the off state, and instead the transistor 1334 is in the on state, supplying current to the sfl terminal and the S' terminal.
When the level of the md terminal is low, a current corresponding to the potential of the E terminal is sucked from the terminal, and an output current for three-phase quasi-full wave is supplied from the s f 1 terminal and the md terminal.
The terminal level is °O. At this time, a current corresponding to the potential of the E terminal is sucked. Also, transistor 1335.1336.1337.1
338°1339, 1340.1341. resistance 1342
．． 1343 constitutes a comparator, and when the potential of the E terminal becomes lower than the potential given by the resistors 1301 and 1302, the level of the dn57H terminal becomes "B", and on the other hand, when it becomes high, it becomes O°. However, this output is used as a command signal for acceleration or deceleration of the motor. Next, FIG. 13 shows the wave phase switching circuit 900, step current generation circuit 1200, and slope generation circuit 1400 of the type shown in FIG. This is a circuit wiring diagram showing a specific configuration example of the slope synthesis circuit 1500 and the rotation stop detector 2100, in which each input/output terminal is connected to the same location as the input/output terminal shown in FIG. The slope generating circuit 1400 includes a capacitor 1401 and a constant current transistor 1 for generating a sawtooth wave.
402 and a discharge transistor 1403, and transistors 1404, 1405, 1406, 140? , a first comparator centered around diode 1408, and transistor 1409 . Diode 1410, ) transistor 1411.1412.
1413.1414. A second comparator centered on the i resistor 1415 and a transistor 1416.1417
．． It consists of an output sofa stage constituted by a resistor 1418, and the output of the x14 child is connected to the synchronous trigger circuit 600 in FIG.
By supplying the output of the synchronous trigger circuit 600 to the x'IQ terminal, the capacitor 1401
The lowest potential is the SC terminal connected to the diode 1.
408, and the amplitude is approximately equal to the voltage in the 1@ direction of the resistor 1.
A sawtooth wave voltage equal to twice the voltage across the terminal 415 appears, and the repetition period of this sawtooth wave is equal to the arrival of the leading edge of the position detection signal shown in FIGS. In other words, the synchronization trigger circuit 600 in FIG. 7 has NAND gates 601, 604, 61,
When the leading edge of the input signal supplied to the input signal 0 arrives, the level of the X2 terminal is shifted to "1", which causes the slope generation circuit 140
The transistor 1403 constituting 0 is turned on,
The charges M accumulated in the capacitor 1401 until then are rapidly discharged. When the potential of the SC terminal becomes lower than the forward voltage of the diode 1408 due to this discharge, the base current is no longer supplied to the transistor 1406, and the level of the X1 terminal becomes °1". Meanwhile, the synchronous trigger circuit 600 3 when the level of moves to B.
Since the RS flimb flow controller is configured to be reset, the level of the X2 terminal returns to "0°" at this point, and as a result, the transistor 1403 is turned off, and the capacitor 1401 is charged. In this way, the capacitor 1401
Since charging and discharging are repeated, a sawtooth wave voltage appears at the SC terminal. Further, this sawtooth wave voltage is smoothed by a resistor 1419 and a capacitor 1420, and then compared with the voltage across the resistor 1415 by a second comparator, so that the potential of the VC terminal is always equal to the voltage across the resistor 1415. Transistor 1413 adjusts the charging current of capacitor 1401 to be equal to the forward voltage of 1410 plus the forward voltage of capacitor 1401 . Therefore, the amplitude of the sawtooth voltage appearing at the SC terminal is
The voltage across the resistor 1415 is approximately twice that of the voltage across the resistor 1415, regardless of the repetition period of the pulse train supplied to the two terminals. This corresponds to the signal waveform of FIG. 11J. 111When synthesizing the sawtooth waves in Figure I to create the signal waveform in Figure 11M,
This is an important function in order to always obtain similar signal waveforms regardless of changes in motor rotational speed. Next, the rotation stop detector 2100 is connected to the capacitor 2101.
A charging/discharging circuit constituted by a constant current transistor 21o2 and a discharge transistor 2103, and a detection circuit mainly constituted by transistors 2104 and 2105. When the motor is rotating, a pulse train appears at the x2 terminal, so the capacitor 2101 is repeatedly charged and discharged, and the potential at the QC terminal is maintained at a sufficiently low value, and the base current continues to flow through the transistor 21o4, but the motor When the transistor 2102 stops rotating, the transistor 2102 becomes saturated and no base current flows through the transistor 2104. At this time, the transistor 2105 is turned off, and the level of the qt terminal becomes °l. NA constituting the mode switching circuit 700 shown in FIG.
One input terminal of the ND gate 706 is supplied with the output signal of the rotation stop detector ztoo. is reset, the output level of the NAND gate 706 is “0°”.
Therefore, the D flip-flop 701 is centered. Since the rotation stop detector 2100 initializes the mode switching circuit 700 in this way, it is possible to reliably restart the motor when a sudden external force is applied during startup or rotation of the motor. Note that the rotation stop detector 2100 is
For example, if the initialization setting is performed via a terminal, it is not necessary (for example, a NAND game that configures the initialization circuit 2000 in FIG. generates the cent signal of the above-mentioned D flip-flop, so in equipment that uses a microcomputer system control such as a video tape recorder, the level of the J4 child is temporarily changed when the power is turned on or when the motor stops rotating. It is sufficient to shift the step current generation circuit 1200 to the 11th step current generation circuit 1200.
This will be explained with reference to the signal waveform diagram shown in the figure. In FIG. 13, transistors 1201, 1202, 1203, 1204, 1205, 1206, 1207, .
120B, resistance 1209°1210.1211.121
2.1213.1214.1215. ) transistor 1216.1217.121B, 1219.1220
．． Resistance 1221°1222, 1223.1224.12
25. ) Langimeta 1226. Resistor 1227 is c
The r terminal is used as a power receiving terminal, and a current mirror circuit is configured to send out five systems of current output, and the transistor 1
The transistors 1216 to 1220 generate the step current waveforms shown in FIG. 11 and O, and the output current of the transistor 1226 is the slope generating circuit 1.
Controls the amplitude of the sawtooth wave generated at 400. Now, the transistors 1203.1204.1205
The output current ratio of each split collector of ゜1206, 1207, and 1208 is 5:5:4:3:2:1,
The transistor 1216.1217.1218.12
19. The output current ratio from each sprint collector of 1220 is l:1:1:l:l, and the collector M of the transistor 1226 and the current of the transistor 12
The output IR from each split collector of the transistor 1216 becomes one quarter of the current supplied to the cf terminal, and the output current from each split collector of the transistor 1216 becomes c
The Emink area of each transistor and the resistors 1209 and 121 are adjusted so that the current is 1/2σ of the current supplied to the r terminal.
0.1211.1212.1213.1214.122
1°+222.1223.1224.1225.122
Assuming that the resistance value of 7 is set, the u m O-u m 5 terminal, usl to us4 terminal, w
mQ-wm5 terminal. When the interval signals shown in FIG. 10 are supplied to the wsl to ws4 terminals, the step current generation circuit 1200
Therefore, the output current waveforms sent to the UO terminal and wQ terminal in FIG. 13 are as shown in FIG. 11 J and N, respectively, and the output current sent from the step current generation circuit 1200 to the slope synthesis circuit 1500 in FIG. The current waveforms are shown as O in FIG. 11, respectively. The slope synthesis circuit 1500 is connected to the ua terminal in FIG. Based on the output signal of the addition/subtraction command circuit 800 supplied to the wa terminal, the sawtooth wave supplied from the slope generation circuit 1400, and the step current for limiting the composite current supplied from the step current generation circuit 1200. A drive current waveform shown in FIG. 11M or FIG. 11Q is created. Transistor 14 constituting slope generation circuit 1400
A sawtooth wave shown in FIG. 11 (3) appears at the emitter of 17, and this voltage waveform has a positive offset voltage corresponding to the forward voltage of the diode 1408, as described above. Each of the transistors 1501 and 1502 constituting the slope synthesis circuit 1500 converts the output voltage of the slope generation circuit 1400 into a current, and absorbs the offset voltage by its base-emitter voltage. Further, the transistors 1501 and 1502
The emitters of PNP type transistors 1503 and 1504 whose collectors are grounded are connected to the bases of the transistors 1503 and 1504, respectively, and the resistors 1505 and 1506 connected to the bases of the transistors 1503 and 1504 are shown in FIG. The output current of step current generation circuit 1200 is supplied. The base-emitter voltage of the transistors 1503.1504 is the same as that of the transistors 1501.1504.
The transistors 1503 and 1504 cancel out each other with those of the transistor 1502.
The maximum emitter area of 1.1502 is the transistor 1
It functions to limit the base side potential of 503.1504. As a result, the collector currents of the transistors 1501 and 1502 change as shown at P in Figure 11. The collector current of the transistor 1501 is the same as that of the transistors 1507, 150B, 1509. Resistance 1510.1
511, one output current of the two sprint collectors of the transistor 1509 is supplied to the uO terminal, and the other output current is supplied to the transistors 1512 and 1513.
The collector of the transistor 1513 is also supplied with uQ.
connected to the terminal. Note that it is assumed here that the transistor 1513 has an emitter area twice that of the transistor 1512. The transistor 15
The common base of 12.1513 is connected to the collector of a transistor 1514 whose emitter is grounded, and the signal waveform shown in FIG. 11G is supplied to the base of the transistor 1514 via the ua terminal during full-wave driving. . When the transistor 1514 is on, no current flows through the collector ti of the transistor 1513, and the output current of one split collector of the transistor 1509 is added to the current supplied from the step current generation circuit 1200 to the uO terminal. The transistor 15
14 turns off, the step current generation circuit 120
It corresponding to the output it of the other sprint collector of the transistor 1509 is subtracted from the current supplied from 0 to the uO terminal. Therefore, the U-phase drive circuit 1 of FIG.
The current supplied to 600 varies as shown in FIG. 11M. Note that the transistor 1515 is turned on during half-metal wave driving to increase the voltage-to-current conversion ratio by the transistor 1501. On the other hand, the transistors 1502.1504 and the resistors 1506, ) transistors 1516.1517.15
1B, resistance 1519° 1520, h transistor 15
The W-phase slope synthesis circuit configured by 21.1522.1523.1524 operates in the same way, and as a result,
The current supplied to the W-phase drive circuit 1700 in FIG. 1 via the WO terminal changes as shown in FIG. 11Q. Next, the mold gold wave phase switching circuit 900 is prepared for operation during half metal wave driving, and its operation will be explained with reference to the signal waveform diagram shown in FIG. The process of generating a drive signal during driving will also be explained. Figures 14A and 14B show the signal waveforms supplied to the n2 terminal + z2 terminal in Figure 13, respectively, and Figure 14C
is the output signal waveform of the slope generation circuit 1400 during half-metal wave driving, and in Fig. 14, E, F, and G are the transistors 906 that constitute the half-metal wave phase switching circuit 900, respectively.
．． 905° is the output current waveform of 904 and 903, and M and 1 in Fig. 14 are the ua terminal in Fig. 14, respectively.
This is the output signal waveform of the addition/subtraction command circuit 800 that is supplied to the slope synthesis circuit 1500 via the wa terminal, and the 14th
In Figure J, the emitters of transistors 1501 and 1502 constituting the slope synthesis circuit 1500 are shown in wandering form, and M is connected to XI! through the uO and wQ terminals, respectively. These are the output current waveforms output from the same-direction switching circuit 1100, and N, O, P, and Q in FIG.
and the current waveforms supplied to the W-phase drive circuit 1700, and R and S in FIG. The metal wave phase switching circuit 900 includes a transistor 901゜90
2, 903. 904. 905. 906. 90
7. Resistance 908°909, 910. 911. 91
2. 913, the current mirror circuit having the sf terminal as the receiving':L terminal, and transistors 914.913.
915. 916. 917. 918 and 919, and performs an operation corresponding to the step current generating circuit 12α0 during full-wave driving. In other words, the half-metal wave phase switching circuit 900 converts the current signals E, F, G, and H in FIG.
On the other hand, the slope synthesis circuit 1500 generates the drive current signal shown in FIG. 14 and the drive current signal shown in FIG. From these drive current signals, drive signals of two strings each shown in FIG.
Supplied to phase drive circuit 1700. The signal waveform in FIG. 14C and the signal waveform in FIG. 11I are both output signal waveforms of the slope generation circuit 1400, and the former is generated during half-wave driving, while the latter is generated entirely during half-wave driving. Produced during wave driving. Furthermore, the repetition period of the former is equal to the arrival period of the leading edge or trailing edge of the position detection signal shown in FIGS. 14A and 14B, whereas the repetition period of the latter is shown in FIG. 11B. It is equal to the arrival period of the leading edge and trailing edge of the FC signal. On the other hand, since the period of the slope portion of the drive current waveform shown in FIG. 14M depends on that of the emitter current waveform of transistors 1501 and 1502 shown in FIGS. Transistor 906 . for the collector current of 903 . The ratio of the collector current at 905 will determine the period of the slope portion. Note that the resistance values of the resistors connected to the collectors of the transistors 1515 and 1524 are determined by the slope synthesis circuit 150.
The maximum value (peak value of the trapezoidal wave) of the current supplied from 0 to the uO terminal and the wO terminal is the transistor 904 and 9
03 to be equal to the current value supplied to the UO terminal and the wQ terminal. Next, FIG. 15 shows the energization direction switching circuit 110 of FIG.
0, U-phase drive circuit 1600. W-phase drive circuit 170
0. Current addition circuit 1800. V phase drive circuit 1900
FIG. 2 is a circuit wiring diagram showing a specific example of the configuration. The energization direction switching circuit 1100 selects the U-phase drive current signal supplied via the UO terminal and the wO terminal in response to the rotation direction discrimination signal supplied from the rotation direction discrimination circuit 300 of FIG. 7 via the dr terminal. A function to switch the W-phase drive current signal supplied via the W-phase drive current signal, a function to switch the polarity of these drive current signals according to the levels of the u1 and wl terminals, and a mode switch as shown in Fig. 7 via the bk terminal. circuit 7
When the stop signal from 00 is supplied, the U-phase drive circuit 1600, the W-phase drive circuit 1700. It has a function of causing the V-phase drive circuit 1900 to conduct current in only one direction. Now, assuming that the motor is rotating in the forward direction and the level of the dr terminal is 0°, the transistor 11O1 and transistor 1102 that constitute the current direction switching circuit 1100 are in the off state, and the transistor 1103 is in the on state. Therefore, the drive current supplied to the uO terminal is passed through the transistor 1104 to the transistors 1105.1106.1107.1108°1109.
, resistors 1110, 1111, 1112, 1113, and the drive current supplied to w Q Q through transistors 1114, transistors 1115, 1116, .
1117°111B, 1119. Resistance 1120.11
21.1122.1123 is supplied to a current drain type current mirror circuit configured by 21.1122.1123. Furthermore, the collector current of the transistor 1109 is
124.1125.1126°+127. resistance 1128
．． 1129 and 1130, and the transistor 11
The collector current of 19 is transistor 1131.113
2.1133.1134. Resistance 1135.1136°1
The current is supplied to a current inflow type current mirror circuit configured by 137. On the other hand, at the time of Hankinha Kaku, SF
The output current from the error signal amplifier 130o is transmitted through the l terminal to the transistors 1138.1139.1140°114.
1, 1142.1143. Resistor 1144.1145.1
146, 1147, and 1148 are supplied to a current drain type current mirror circuit. First, during full-wave driving, the level of the u1 terminal is “1”
When , transistor 1149 is on, and transistor 1150 and transistor 1151 are off. At this time, the collector current of the transistor +107 flows through the diode 1152 to the U-phase drive circuit 1.
The collector 'r! of transistor 1108 is supplied to the upper drive circuit constituting 600; l current is diode 11
53 to the transistor 1149, and
Since no current is supplied via the sfl terminal, no current is supplied to the lower 01 drive circuit that constitutes the U-phase drive circuit 1600. On the other hand, when the level of the u1 terminal is "O", the transistor 1149 is off.
Transistor 1150 and transistor 1151 are turned on. At this time, the current flows through the collector of the transistor +108 via the diode 1154 to the U-phase drive circuit 160.
However, since the collector current of the transistor 1107 is absorbed by the transistor 1150, no current is supplied to the upper drive circuit forming the U-phase drive circuit 1600. The W-phase circuit plotter operates in the same way as the U-phase case, and w1
When the level of the terminal is "lo", the driving T! current is supplied to the upper drive circuit constituting the W-phase drive circuit 1700 via the transistor 11]7 and the diode 1155, and the level of the w1 terminal becomes 0°. 11, the drive current is supplied to the lower drive circuit through transistor 1118 and diode 1156. In this way, the drive current waveforms shown in FIGS. 11M and Q are changed to those shown in FIGS. According to the level of the indicated signal, it is distributed to the E side drive circuit and the lower side drive circuit of the U phase and W phase, respectively. During full wave driving, the output of the error signal amplifier 1300 is passed from the sfl terminal. is supplied, so transistor 1
The current mirror circuit constituted by resistors 138 to 1143 and resistors 1144 to 1148 becomes active, and the 14th
As shown in Figures N, O, P, and Q, during periods when no drive current is supplied to the upper drive circuit of each phase, drive current is supplied to the lower drive circuit instead. That is, time t in FIG.
At the time of , the current supplied through the uO terminal is zero as shown in the 14th diagram, so the level of the u1 terminal is “
1', the current supplied to the U-phase upper drive circuit via the diode 1152 is zero, but the collector current of the transistor 1140 is supplied to the lower drive circuit via the diode 1157. It is assumed that the current mirror ratio is set so that the collector current of this transistor +140 is one half of the current supplied via the sfl terminal.At time 0 too, the collector current is supplied via the uO terminal. When the current reaches its maximum value, the same value of current is supplied to the U-phase upper drive circuit through the diode 1152, and all of the collector current of the transistor 91140 is absorbed by the transistor 1127.
The current supplied to the U-phase lower drive circuit via the diode 1157 becomes zero. These operations are similar for the W phase as well. Now, when the motor is rotating in the opposite direction and the level of the dr terminal is "1", the transistor 1102 is turned on and the transistor 1103 is turned off.At this time, the voltage supplied from the uQ terminal The current is supplied to the current mirror circuit on the W phase side via the transistor 1158, and Tt'lJt supplied from the wQ terminal is supplied to the current mirror circuit on the U phase side via the transistor 1159, so that the U phase is driven. This means that the signal and the W-phase drive signal have been swapped.This swapping of the drive signal corresponds to the swapping of the position detection signal in the sequential circuit 200.When the level of the bk terminal becomes "0", the transistor 12
60 is in an off state, resulting in transistor 126
1.1262.1263 is turned on and absorbs the drive current supplied to the lower drive circuit of each phase, so only the upper drive circuit of each phase becomes active, and the stator t in FIG.
! Only the circuit current of the Hall IC 6 flows through the L lines 1 to 3. Therefore, although the motor does not generate rotational torque, the Hall IC 6 is in a situation where it can detect the position even when the motor is stopped.Next, the U-phase drive circuit 1600 and the W-phase drive circuit 170
The 0°V phase drive circuit 1900 is simply a current amplifier constructed by combining current mirror circuits, so a description of its operation will be omitted, but the final stage of the upper drive circuit for each phase is an NPN power transistor. In order to minimize the residual voltage when the maximum current is supplied to the stator windings 1 to 3, the U-phase drive circuit 1600 will be explained as an example. If the configuration of the current mirror circuit made up of transistors 1601 and 1602 and transistor 1603 that constitute the final stage of the lower drive circuit of U-phase drive circuit 1600 is used as is for the final stage of the upper side, transistor 16
The collector-emitter voltage of 02 is the transistor 160.
The voltage is not smaller than the sum of the base-emitter voltage of transistor 1602 and the base-emitter voltage of transistor 1602 plus the saturation voltage of the PNP transistor in the previous stage, and the minimum value is about 1.8V. On the other hand, the transistor 16 constituting the upper final stage
The collector-emitter voltage of 04 can reach the value obtained by adding the saturation voltage of the transistor 1605 in the previous stage to its own base-emitter voltage, and the minimum value is about 1.1V. Now, the current addition circuit 1800 is the U-phase drive circuit 1600.
Transistors 1801 and 1802 take out a current equal to the drive current supplied to the upper drive circuit, transistors 1803 and 1804 take out a current equal to the drive current supplied to the lower drive circuit, and upper drive of the W-phase drive circuit 1700. Transistors 1805 and 1806 that take out a current equal to the drive current supplied to the circuit, transistors 1807 and 1808 that take out a current equal to the drive current supplied to the lower drive circuit, and a diode 1809.
10, 1811 and 1812, the collector of the transistor 1801 and the transistor 180
The collector of the transistor 1809 is connected to the connection point of the transistor 1809, and the anode of the diode 1809 is connected to the connection point of the collector of the transistor 1809.
806 and the collector of the transistor 1804 are connected, and the connection point is connected to the diode 1812.
the anode of the diode 1812 is connected to the cathode of the diode 1809;
The collector of the transistor 1802 and the collector of the transistor 1808 are connected, the cathode of the diode 181O is connected to the connection point, and the collector of the transistor 1805 and the transistor 1803 are connected to each other.
The collector of the diode 1811 is connected to the connection point, and the cathode of the diode 1811 is connected to the connection point of the diode 1811.
The anode of the diode 1810 is connected to the cathode of the diode 1810. Additionally, the diode 1810.18
The anode of the diode 11 is connected to the drive current receiving point vp of the upper drive circuit of the V-phase drive circuit 1900, and the anode of the diode 1
The cathode of 809.1812 is connected to the power receiving point vn of the drive current of the lower drive circuit of the V-phase drive circuit 1900. Here, the magnitude of the current supplied to the drive current receiving point up of the upper drive circuit of the U-phase drive circuit 1600 is Iup, and the magnitude of the current supplied to the drive current receiving point un of the lower drive circuit is Iup. is run, the magnitude of the current supplied to the drive current receiving point wp of the upper drive circuit of the W-phase drive circuit 1700 is Iwp, and the magnitude of the current supplied to the drive current receiving point w of the lower drive circuit is Iwp.
If the magnitude of the current supplied to transistor n is Iwn, a current of magnitude Iup flows out from the collectors of the transistors 1801 and 1802, and a current of magnitude Iup flows into the collectors of the transistors 1803 and 1804, respectively.
N currents of magnitude n are absorbed and from the collectors of the transistors 1805 and 1806 respectively Iwp
A current having a magnitude of
7.1808 collectors each absorb a current of magnitude Iwn. Therefore, when the value of Iup becomes larger than the value of IwnO, the difference current flows through the diode 1809 to v
When the difference in Iwp becomes larger than the runO value, the difference current is supplied to the Vn point via the diode 1812, and the value of Iun! When the wpO value becomes larger, the difference current flows through the diode 1811
When the value of Iwn becomes larger than the value of IupO, the difference current flows through the diode 181.
0 to the vp point. That is, from the current addition circuit 1800 to the V-phase drive circuit 19
The value 1vp of the drive current supplied to the upper drive circuit of 00 and the value 1vn of the drive current supplied to the lower drive circuit are given by the following equation. The current waveforms shown in FIGS. 14R and 14S are those shown in FIG. 14N. The results obtained from Equation 7 and Equation 8 are plotted based on the current values obtained from the tura waveforms shown in 0, P, and Q, respectively, and the current waveforms in T and U in Figure 11 are plotted. was obtained in the same way. Of course, it has been confirmed that the same NK waveform can be obtained not only by calculation but also by the actual circuit shown in FIG. Now, returning to Figure 1, we can summarize the actions explained so far as follows. First, when the Ji terminal level is "0" and the motor rotor is stopped, at least one of the U terminal, ■ terminal, and W terminal is at a high potential, and the stator winding A current is supplied to the Hall IC 6 via the current limiting resistor 8 to detect the stationary position of the rotor, and the Hall IC 6 is set to a high potential depending on the stationary position of the rotor. Generates intermediate and low potential outputs. The position detection signal is distributed according to the output level of the Hall IC 6, and the position detection signal is distributed by the 7S 100, and this position detection information is sent to the sequential circuit 20.
0 to the gold wave phase switching circuit 900,
While the level of J5a is “0°, sequential circuit 2
00 operates as a mere buffer, and U-phase drive circuit 1600 . W phase drive circuit 1700° ■phase drive circuit 1
Power is also not supplied from 900 to stator windings 1 to 3. When the level of the J terminal shifts to °1, the drive circuit of each phase switches to any one of the U terminal, ■ terminal, and W terminal based on the position detection information supplied to the mold wave phase switching circuit 900. Absorbs current from the terminals and generates rotational torque in the rotor. It should be noted that at this time, it is assumed that the Hall IC 6 happened to stop at a position where the electrical angle of rotation is 60° in FIG. Then, in either case, the Hall IC 6 generates the same output as when facing the non-magnetized portion of the identification band 5, and the stator windings 1 to 3 are energized based on that information.
As can be seen from the characteristic curve in FIG. 3B, the rotor will generate rotational torque in the opposite direction. However, regular position detection information is obtained by only a small movement of the rotor, and after that, the sequence of receiving and receiving position detection signals is regulated by the sequential circuit 200, so smooth rotation can be maintained. . When the rotor starts rotating, the FG multiplied signal from the power generation winding 7 appears, so the output level of the D flip-flop 701 (Fig. 7) that constitutes the mode switching circuit 700 shifts to 0 at a predetermined timing. Then, the current supply mode to the stator windings 1 to 3 is switched to three-phase full-wave drive, and the torque characteristic of the motor becomes as the envelope of the characteristic curve shown in FIG. 3C. After the energization mode shifts to three-phase full-wave drive, if the rotational speed of the motor decreases until the FC signal disappears due to sudden load changes, etc., the output level of the D flip-flop 7 block 701 returns to "L". Therefore, the energization mode becomes three-phase quasi-full wave drive again.On the other hand, if the level of the J terminal shifts to "0" while the energization mode is three-phase full-wave drive,
As long as the output level of the flimp frontop is 101,
The level of the bk terminal in Fig. 15 is maintained at 1°, and the stator windings 1 to 3 continue to be energized.At this time, the level of the J terminal is 0, so Table 1 shows As shown, the NAND cable that configures the energization direction setting QIIOQO)
The output level of 1015 (Figure 7) is "1",
From energizing direction setting circuit 1000 to energizing direction setting circuit 8110
The phase of the output signal sent to stator winding 1 is reversed and
The direction of energization to ~3 is reversed, and the motor is rapidly decelerated. When the rotational speed of the motor approaches zero and the FC signal disappears or the rotation stop detection 252100 generates an output signal, the output level of the D Friction Flop 701 changes to
Since the angle shifts to 1°, the level of the bk terminal also shifts to 0°, and energization to the fixed pre-windings X1-3 is stopped. In addition, if a command signal in the forward direction is applied from the REV terminal while the motor continues to rotate in the reverse direction, such as when switching between forward and reverse directions, the commanded direction of rotation and the actual direction of rotation will match. Therefore, a rotation direction mismatch signal is supplied from the rotation direction determination circuit 300 to the error signal amplifier 1300 and the energization direction setting circuit 1000. As a result, when the level of the eni child in Figure 11 becomes "0",
The transistor 1303, which had been off until then, turns on, which is the same as the potential at the E terminal dropping to near zero, and the error signal amplifier 1300 is activated via the cf terminal (in full-wave drive). ) The maximum output current is supplied to the step current generation circuit 1200. On the other hand, when the rotational direction mismatch signal is supplied to the energization direction setting circuit 1000, as can be seen from Table 1, the NAND game in FIG.
Since the output level ex shifts to °l°, the direction of current supply to the stator windings 1 to 3 is reversed, and the motor is rapidly decelerated. When the rotation speed of the motor exceeds zero and starts rotating in the forward direction, the rotation direction determination circuit 300 in FIG.
The output level of the D flip-flop 301 constituting the
°, the level of the d" terminal shifts to °O°, and the level of the en terminal shifts to "lo". From then on, the motor is accelerated in the same way as when starting from a stopped state. Now, FIG. 16 is a sectional view of the torque generating part of the motor prepared to explain the mechanism of vibration and noise generation. In FIGS. 12 is a stator yoke on which stator S lines 1a and lb are arranged, and all curves with arrows represent lines of magnetic force. In the relative position of the rotor and stator shown in FIG. The windings 1a and lb generate a force parallel to the magnetization direction, which becomes the rotational torque of the motor. However, in the relative position of the rotor and stator shown in FIG. The torque not only becomes zero, but also generates a force perpendicular to the magnetization direction of the permanent magnet 4. With the relative positional relationship shown in FIG. 16B and the direction of energization to the stator windings 1a and lb, each stator winding generates a repulsive force that lifts the rotor, and each stator winding generates a repulsive force that lifts the rotor. When the current direction is reversed, a force is generated that attracts the rotor to the stator, and the repetition of these repulsive attractions becomes a major cause of motor vibration.
Along with the generation of vibration, noise is also generated at the same time. The magnitudes of this repulsive force and attractive force are minimum at the relative position shown in Figure 16A, and maximum at the relative position shown in Figure 16B, but at intermediate positions between these, they gradually increase or increase depending on the position. Therefore, in order to reduce vibration and noise, it is sufficient to reduce the fluctuations in repulsion and attraction per rotation of the rotor, and in the case of a 3-phase DC non-commutated motor, the fluctuation in electrical angle can be reduced. Since it has three sets of stator windings arranged 120 degrees apart, the sum of the repulsive force and attractive force of each stator winding hardly changes even when the rotor changes. All you have to do is create a drive current waveform. Specifically, in the signal waveform of FIG. 11M, the time [,
The slope from to time El greatly contributes to vibration and noise, and if the current is increased linearly from time tll, setting the current waveform so that the current value reaches its maximum before time tri will cause the slope to increase. Calculations have confirmed that the fluctuations in repulsive force and attractive force increase rapidly as the steepness increases. In other words, in order to minimize the force in the direction of the rotation axis of the motor and reduce vibration and noise in a 3-phase full-wave drive with 180" current applied, it is necessary to reduce vibration and noise by 60" from the start of energization.
An important factor is the management of the slope in the section up to 60° and the 60° section up to the end of energization. On the other hand, in order to reduce the fundamental frequency component of motor torque fluctuation, as is clear from comparing the torque characteristics in Figure 3A and the torque characteristics in Figure 3C, it is necessary to start energizing each stator winding. An important factor is the management of the shape of the energization waveform in the section excluding the section from 30° to 30° and the 30° section until the end of energization. In the DC non-commutator motor shown in Fig. 1, Fig. 11 J
, N, any drive current waveform can be created by the step controller '500 and the step current generation circuit 1200, and the drive circuit for each phase consists of the step current generation circuit 1200 and the slope synthesis circuit 1500. A current proportional to the drive current generated by the stator windings 1 to 3 is supplied to the stator windings 1 to 3. Therefore, it is possible to easily create a current waveform that minimizes vibration and noise during rotation of the motor. That is, during full-wave driving, the steps shown in FIG.
In, resistance 1209~1215.1221~122
By changing the ratio of the resistors 4.1225 and 1227, the shape of the drive current waveforms shown in Figure 11 M and Q can be freely changed, and when driving the skewer full wave, the shape of the drive current waveform shown in Figure 13 can be changed. In the phase switching circuit 900, the resistor 908
By changing the ratio of the resistance values of 913 to 913, the slope of the driving current waveform of M can be selected to the optimum value. By the way, as can be seen from the signal waveforms N and M in FIG. 11, it is possible to use only a step controller 500 consisting of a 4-bit counter and a step current generating circuit 1200 of the size shown in FIG. In this case, the change in the level of the drive waveform is not smooth enough, and in particular, if the step is set so that the envelope line has a sine wave shape, the step near zero becomes large, and this causes a change in the stator winding. It behaves like a speaker's voice coil, which causes high-frequency noise. However, in the DC non-commutator motor of the present invention, the slope generation circuit 1400 generates the slope waveform (sawtooth wave) shown in FIG. By combining the output signals with the output signals of , it is possible to create smooth drive current waveforms as shown in FIG. 11 M and Q with a relatively small-scale circuit configuration. Although the embodiment shown in FIG. 1 shows a three-phase DC non-commutator motor, the present invention can be applied not only to three-phase motors but also to two-phase or single-phase motors with sufficient effect. It is something. Effects of the Invention As is clear from the above description, the DC non-commutator motor of the present invention can
Step signal waveform generating means (example) that generates an output signal whose level changes step by step in steps proportional to the drive command current depending on the voltage supplied from the outside or the t current each time an edge of the rotation detection signal arrives. (The step controller 500 and the step current generating circuit 1200 constitute a step signal waveform generating means.)
and a slope generation circuit 1400 that generates a slope waveform with a period dependent on the arrival period of the edge of the rotation detection signal.
, a slope synthesis circuit 1500 that generates a drive signal by synthesizing the slope waveform with the output signal of the step signal waveform generating means, and a drive circuit that amplifies the drive signal and supplies it to the stator winding. Therefore, a smooth drive current waveform can be created with a relatively small-scale circuit configuration, resulting in great effects.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a DC non-commutator motor according to an embodiment of the present invention, Fig. 2 is a schematic diagram of a motor section configured to carry out the present invention, and Fig. 3 is a diagram showing the torque characteristics of the motor. A torque characteristic diagram to explain energization switching, Figure 4 is a wiring diagram of the internal circuit of the Hall IC, and Figure 5 is a diagram of identification band wear corresponding to the pattern to explain the processing operation of the position detection signal. Waveform diagram, Figure 6 is a circuit connection diagram showing a configuration example of a distributor, Figure 7 is a sequential circuit 1 rotation direction discrimination circuit, step controller, synchronous trigger circuit, mode switching circuit, addition/subtraction command circuit, illll same direction setting Logic circuit diagrams showing configuration examples of circuit periodization circuits, FIGS. 8 and 9,
1O, 11, and 14 are all signal waveform diagrams for explaining the operation of each block in FIG. 1, FIG. 12 is a circuit connection diagram showing an example of the configuration of an error signal amplifier, and FIG. The diagram shows a half-metal wave phase switching circuit, a step current generation circuit, and a slope generation circuit. A circuit connection diagram showing a specific configuration example of the slope synthesis circuit 1 rotation stop detector, Figure 15 shows the specifics of the current direction switching circuit, U-phase drive circuit, W-phase drive circuit, current addition circuit, and V-phase drive circuit. FIG. 16 is a circuit diagram showing an example of the configuration, and is a sectional view of the torque generating portion of the motor. 1.2.3...Stator winding, 4...Permanent magnet, 6...Hall IC5200...
・Sequential circuit, 500... Step controller, 600... Synchronous trigger circuit, 800...
...Addition/subtraction I current circuit, 1200...Step current generation circuit, 1300...Error signal amplifier,
1400...Slope generation circuit, 1500...
... Slope synthesis circuit, 1600 ... U phase drive circuit, 1700 ... W phase drive circuit, 190
0...v4'I'I drive circuit. Name of agent Patent attorney Toshio Nakao Haka1 person Figure 3 Figure 5 D (Zr) G (and 7) Ka14 Figure 3 (Ko J1 Figure 16

Claims (2)

[Claims] (1) A rotor including a stator winding, a permanent magnet having a magnetized portion facing the stator winding, and a position detection means for detecting the rotational position of the rotor and generating a position detection signal. and a rotation detection means that generates a rotation detection signal having a higher frequency than the position detection signal when the rotor rotates, and an error signal that generates a drive command current depending on an externally supplied voltage or current. an amplifier, and a step signal that generates an output signal whose level is switched stepwise at a step proportional to the drive command current each time an edge of the rotation detection signal arrives, with a predetermined edge of the position detection signal as a reference. a waveform generating means; a slope generating circuit that generates a slope waveform with a period dependent on the arrival period of the edge of the rotation detection signal; and generating a drive signal by synthesizing the slope waveform with the output signal of the step signal waveform generating means. A DC non-commutator motor comprising a slope synthesis circuit and a drive circuit that amplifies the drive signal and supplies the drive signal to the stator winding. (2) A step controller that starts counting the edges of the rotation detection signal from a specific value every time a predetermined edge of the position detection signal arrives and generates a timing signal, and receives the output current from the error signal amplifier; Claim 1, wherein the step signal waveform generating means is constituted by a step current generating circuit comprising a current mirror circuit having a plurality of transistors that outputs a current with a predetermined distribution ratio based on a timing signal. DC commutatorless motor.