JP2604707B2 - DC no commutator motor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a commutatorless motor used under a DC power supply.

2. Description of the Related Art In recent years, DC non-commutator motors have been frequently used in many audio equipment, video tape recorders, and even floppy disk devices, and applications are expanding from their ease to fan motors for air cooling. doing.

Conventionally, a two-phase or three-phase half-wave drive system or a full-wave drive system has predominantly been used as this type of DC non-commutator motor. Each driving method has advantages and disadvantages. For example, a three-phase driving method requires a smaller number of driving power elements than a two-phase driving method, but has a larger number of position detecting elements for detecting the rotational position of the rotor. Will be needed. By the way, when compared with a single power supply, the two-phase full-wave driving method requires eight power transistors and two Hall elements, and the three-phase full-wave driving method requires six power transistors. And three Hall elements are required.

Conventionally, many attempts have been made to reduce the number of position detection elements in a three-phase drive system, and a typical technique is disclosed in U.S. Pat. No. 3,577,053 (hereinafter abbreviated as Document 1). ing. According to Document 1, in a three-phase half-wave drive type non-commutator motor, an identification band having first, second, and third components having different light reflectivities is provided on a rotor, and the identification band is provided. By irradiating a light beam and detecting reflected light with a light receiving element, a change in the rotational position of the rotor is captured as a three-step change in the output level of the light receiving element,
A device configured to energize the phase winding depending on its level is shown.

In the method disclosed in the above-mentioned document 1, three-phase half-wave driving is enabled by only one position detecting element and an identification band for position detection.
Limited to phase half-wave type. That is, if the form shown in the above-mentioned document 1 is adopted, only three types of detection can be performed per 360 ° electrical angle, and thus only three types of switching of the energization state to each phase winding are necessarily allowed. In order to realize a three-phase full-wave driving method that requires the switching of the six conduction states, an extra position detecting element and an additional identification band are required.

Incidentally, in this type of motor, in order to reduce vibration and torque ripple during rotation, it is preferable that the current waveform supplied to the stator winding be sinusoidal.
In the publication No. 00088 (hereinafter abbreviated as Document 2), since the position detection signal obtained from the Hall element does not have an ideal sine waveform due to various factors, sine wave information is stored in advance in a digital memory. In advance, the information of the memory is sequentially read out by an output signal (generally called an FG signal) of a frequency generator connected to the motor, and is converted into an analog voltage so as to generate a nearly ideal sine-wave drive current. 1 shows a DC non-commutator motor.

Problems to be Solved by the Invention However, the method disclosed in the above-mentioned document 2 has a considerably large circuit scale as compared with the conventional method of performing processing in an analog manner. Since the digital information is converted into an analog amount, there is a problem that it is necessary to accurately maintain the balance of each phase after the conversion into the analog amount. Incidentally, JP-A-60-87
Japanese Patent No. 692 discloses a technique for generating a third-phase drive voltage by adding a first-phase drive voltage and a second-phase drive voltage in a voltage-controlled motor drive device. To realize in a semiconductor integrated circuit,
It is necessary to accurately manage the variation of the resistance value (generally, high resistance) of the voltage adding resistor, but this has been a difficult task.

Means for Solving the Problems In order to solve the above-mentioned problems, a direct current commutator motor according to the present invention has a first motor whose amplitude is proportional to the output of the error signal amplifier based on the output of a position detector. Drive signal generation means for generating a phase drive current and a second phase drive current;
The current flowing into the first phase or the second phase and the second phase or the first
The difference current between the currents flowing out of the phases flows into the third phase, and the difference current between the current flowing out of the first phase or the second phase and the current flowing into the second phase or the first phase flows out of the third phase. It is characterized by having a differential current generating means.

According to the present invention, a drive signal waveform of a third phase similar to the first phase and the second phase can be obtained from the difference between the drive currents of the first phase and the second phase by the above-described configuration. Thus, a three-phase DC non-commutator motor can be realized.

Examples Hereinafter, examples of the present invention will be described with reference to the drawings.

FIG. 2 is an exploded view of a main part of a motor configured to carry out the present invention.
2, 3 are star-connected, and the stator windings 1 to 3 are connected.
, A permanent magnet 4 mounted on a rotor (not shown) is arranged.

The main part of the permanent magnet 4 is occupied by a main magnetic pole magnetized to eight poles, and its inner periphery (not shown in the figure, but in FIG. 2, the upper side of the permanent magnet 4 is the inner periphery of the rotor). The lower part is an outer peripheral part.) Includes a first component part 5a that is N-polarized and a second component part that is not magnetized.
5b and an annular identification band 5 in which S-polarized third component parts 5c are alternately arranged in the circumferential direction.

Further, a Hall IC (an integrated circuit in which a Hall power generator and other circuits coexist on a chip) 6 provided as a rotation position detecting element of the rotor is disposed facing the identification band 5.

On the other hand, a power generation band in which the main magnetic pole of the permanent magnet 4 is magnetized to 96 poles is provided on the outer peripheral side, and a zigzag having 96 power generation element portions diffracted in the radial direction facing this power generation band is provided. A power generation winding 7 is arranged.

Further, the lead wires of the stator windings 1, 2, and 3 are:
Each is connected to the first power supply terminal U, the second power supply terminal V, and the third power supply terminal W, and the star-connected middle point is connected to the terminal X.

The Hall IC 6 has a positive power supply terminal 6a, a negative power supply terminal 6b, and an output terminal 6c, and the lead wire of the power generation winding 7 is connected to the output terminals 7a and 7b.

FIG. 1 is a block diagram showing a direct current commutator motor according to an embodiment of the present invention. In FIG. 1, a block 10 is used to connect the internal connection of the motor block shown in FIG. In the motor block 10, a current limiting resistor 8 is connected between the midpoint terminal X and the plus side feed terminal 6a of the Hall IC 6, and the minus side feed terminal 6b of the Hall IC 6 and the The other output terminal 7a is connected to the rotation detection terminal F.

A position detection signal whose level changes in three stages depending on the rotational position of the motor is output to the position detection terminal P by a processing circuit (described later) incorporated in the Hall IC 6, and this position detection signal is distributed. The signals are distributed to three signal lines that are sequentially activated according to the input level by the distributor 100. These outputs are subjected to conditional processing by the sequential circuit 200, and the output of the distributor 100 is applied to the REV terminal. The rotation direction determination circuit 300 is used together with the rotation direction command signal to determine the rotation direction of the motor.

The signals appearing at the rotation detection terminal F and the ground terminal G are amplified to a sufficient amplitude by the amplifier 400, and then the rotation direction discriminating circuit 300 is used as a clock signal for generating a timing. And a synchronous trigger circuit 600 that determines the timing of the occurrence of a slope added to the current flowing through the stator windings 1 to 3.

Further, the output of the sequential circuit 200 is the step controller 500 and the synchronous trigger circuit 600, and a mode switching circuit for switching between three-phase quasi-full-wave drive and three-phase front-wave drive based on the output of the step controller 500. 700,
An addition / subtraction command circuit 800 for switching between a rising slope and a falling slope, and a quasi-full-wave phase switching circuit 900 for performing phase distribution of a driving current in three-phase quasi-full-wave driving, are supplied to the output of the rotation direction determination circuit 300, An energization direction setting circuit 1000 for setting the energization direction to the stator windings 1 to 3; an energization direction switching circuit 1100 for switching the energization direction based on the output of the energization direction setting circuit 1000; It is supplied to an error signal amplifier 1300 which amplifies an error signal from a rotation speed detector (not shown in FIG. 1). The terminal E is a terminal to which a command voltage for accelerating or decelerating the rotation speed of the motor is applied, and an error signal from a rotation speed detector not shown in FIG. 1 is normally applied. .

The error signal amplifier 1300 generates a command signal for accelerating or decelerating a current value depending on an error voltage applied to the E terminal, as described later. The step controller 50
The output of 0 is the mode switching circuit 700 and the addition / subtraction command circuit.
800 and a step current generating circuit 1200 for generating a step current waveform at the time of full-wave driving, the mode switching circuit
The output of 700 is the sequential circuit 200 and the rotation direction discriminating circuit 300, the addition / subtraction command circuit 800, the energizing direction setting circuit 1000 and the energizing direction switching circuit 1100, and the error signal amplifier 1300, and the stator. It is supplied to a slope generation circuit 1400 that generates a slope to be added to the current flowing through the windings 1 to 3. Further, the synchronous trigger circuit 60
0 and the signal is exchanged between the slope generation circuit 1400 and the output of the slope generation circuit 1400 and the output of the addition / subtraction command circuit 800 are both the quasi-full wave phase switching circuit 900.
Alternatively, it is supplied to a slope synthesis circuit 1500 for adding a slope to a step-shaped current output signal output from the step current generation circuit 1200, and the slope synthesis circuit 1500
Is superimposed on the output current of the quasi-full-wave phase switching circuit 900 or the step current generation circuit 1200.

On the other hand, an acceleration or deceleration command signal from the error signal amplifier 1300 is supplied to the energization direction setting circuit 1000,
The output current from the error signal amplifier 1300 is supplied to the slope generation circuit 1400 and the quasi-full-wave phase switching circuit 900 and the step current generation circuit 1200, and the quasi-full-wave phase switching circuit 900 and the step current generation circuit 1200 Is supplied to the U-phase drive circuit 1600 and the W-phase drive circuit 1700 via the conduction direction switching circuit 1100, and is also supplied to the slope synthesizing circuit 1500, and the U-phase drive circuit
The main output current of 1600 and the main output current of the W-phase drive circuit 1700 are respectively the U terminal to which the U-phase stator winding 1 is connected and the W terminal.
Is supplied to the W terminal to which the three-phase stator winding 3 is connected, and the output current of a part of the U-phase drive circuit 1600 and the output current of the W-phase drive circuit 1700 is added by a current addition circuit 1800 to form a V-phase drive circuit 1900. The output current of the V-phase drive circuit 1900 is supplied to a V terminal to which the V-phase stator winding 2 is connected.

In the embodiment of FIG. 1, a motor stop / rotation command signal is applied to the J terminal, and this command signal is directly supplied to the energization direction setting circuit 1000, and a motor rotation stop command signal is supplied from outside. In addition to being used to generate a brake signal when applied, it is also used to initialize the step controller 500 and the mode switching circuit 700 via an initialization circuit 2000. The output signal of the amplifier 400 is also supplied to the rotation stop detector 2100, and the rotation stop detector 21100
The output signal of 00 is supplied to the mode switching circuit 700,
When the rotation of the motor is stopped, the output state of the mode switching circuit 700 is forcibly shifted to the three-phase quasi-full-wave drive state. Further, a forward / reverse switching signal in the rotation direction of the motor is applied to the REV terminal.When the REV terminal is at a low potential, the motor rotates in the forward direction, and when the REV terminal is at the high potential, the motor rotates in the reverse direction, When the J terminal has a low potential, the current supply to the stator winding is stopped, and when the J terminal has a high potential, the current supply to the stator winding is performed.

Although the present invention does not refer to the rotary servo system of the motor, it is assumed here that the error voltage is fed back to the error signal amplifier 1300 via the E terminal based on the speed information obtained from the F terminal.

Before describing the outline of the operation of each unit, the operation of switching the energization state to the stator winding of the DC non-commutator motor shown in FIGS. 1 and 2 will be described.

As is clear from FIGS. 1 and 2, in the DC non-commutator motor described as an embodiment of the present invention, an annular shape having three kinds of components is used as a means for detecting the stationary position of the rotor. , And only the Hall IC 6 are provided, so that only three types of identification can be performed according to the stationary position of the rotor. However, as is well known, 3
If a phase full-wave drive mode is to be adopted, six types of position detection information are required according to the stationary position of the rotor.

In the DC-less commutator motor shown in FIG. 1, current is supplied to all three-phase stator windings 1, 2, and 3 based on the output signal of the Hall IC 6 until the rotation speed of the motor increases to some extent. By supplying an extra current to prevent a decrease in the starting torque, the rotation speed of the motor is increased and a sufficient signal is obtained from the power generation winding 7. Based on the output signal of the Hall IC 6, the energization switching signal for three-phase full-wave driving is supplied to the distributor 100, the sequential circuit 200, the step controller 500, the synchronous trigger circuit 600, and the mode switching circuit 70.
0, the addition / subtraction command circuit 800, the quasi-full-wave phase switching circuit 900, the conduction direction switching circuit 1100, the step current generation circuit 1200, the slope generation circuit 1400, and the drive signal generation means constituted by the slope synthesis circuit 1500. It is configured.
The principle of switching between the driving modes will be described with reference to FIG.

FIG. 3A shows each of the stator windings 1, 2,... When the main pole of the permanent magnet 4 is sine-wave magnetized in the motor structure of FIG.
3 shows a torque characteristic generated when a current is applied to the rotor 3. In FIG. 2, the rotational torque when the stator side including the stator windings 1 to 3, the Hall IC 6, and the power generation winding 7 moves to the right is shown. Is the positive direction. A characteristic curve ua in FIG. 3A represents a torque generated when a current flows from the U terminal to the X terminal direction in the stator winding 1 in FIG. 2, and a characteristic curve ub is a characteristic curve ub. Represents the torque generated when a current flows from the X terminal to the U terminal. A characteristic curve va represents a torque generated when a current flows through the stator winding 2 in the direction from the V terminal to the X terminal, and a characteristic curve vb represents a direction in which the stator winding 2 flows from the X terminal to the V terminal. Represents the torque generated when a current is applied to the motor. Further, a characteristic curve wa represents a torque generated when a current flows from the W terminal to the X terminal in the stator winding 3, and a characteristic curve wb represents the torque from the X terminal to the W terminal in the stator winding 3. Represents the torque generated when a current is applied to the motor.

On the other hand, FIG. 3C shows the torque generated in the positive direction when power is supplied to any two phases of the star-connected three-phase stator windings in each of the stator windings shown in FIG. 3A. As is well known, the envelope of these curves becomes the actual output torque waveform in a three-phase full-wave drive motor. That is, in FIG.
wv is the torque generated when current is applied from the W terminal to the V terminal in FIG. 2, the characteristic curve uv is the torque generated when current is applied from the U terminal to the V terminal, and the characteristic curve uw is the direction from the U terminal to the W terminal. And characteristic curves generated when power is supplied to
vw is the torque generated when current is applied from the V terminal to the W terminal, the characteristic curve vu is the torque generated when current is applied from the V terminal to the U terminal, and the characteristic curve wu is when the current is applied from the W terminal to the U terminal. , Respectively.

Assuming that the maximum torque generated by each stator winding is 1, 3
Since the phase excitation switching to the stator windings every 60 ° electrical angle in the full-wave driving is performed, the maximum torque T _ma1 after synthesized, the minimum T _mi1, average torque T _av1 is given by: . Here, all the torques are unitless and are represented by simple indices.

FIG. 3D shows the output signal waveform of the Hall IC 6 already described. When the rotor of the motor is stopped, the Hall IC 6 is used as the position detection information.
The output signal of can not be used. In order to start the motor using only the three types of position detection information, it is conceivable to adopt a three-phase half-wave drive mode.
A power switching element is required to directly connect the X terminal, which is the middle point of the star-connected stator windings, to the plus or minus feed line.

In the embodiment of the present invention, such a disadvantage is solved by the method described below. That is, the Hall IC 6
In response to the three-stage level change of the output signal, the section where the output signal is at a high potential is the first conduction section, the section where the output signal is at a low potential is the second conduction section, and the section where the output signal is at the intermediate potential is the third
In the first energizing section, the U terminal shown in FIG. 2 is energized to the V terminal and the W terminal, and in the second energizing section, the V terminal is energized to the W terminal and the U terminal. In the third energizing section, energization from the W terminal to the U terminal and the V terminal is performed. At this time,
The combined torque characteristics of the three-phase stator windings 1, 2, and 3 are as shown in FIG. 3B. The characteristic curve uc is the torque generated by energization in the first section, and the characteristic curve vc is the second section. And the characteristic curve wc represents the torque generated by energization in the third section.

Therefore, the output torque of the motor when the energization switching is performed at an ideal timing is equal to the envelope of the characteristic curve shown in FIG. 3B, and the main winding among the three-phase stator windings has another winding. maximum torque T _ma2 considering that current equal to the sum of the currents of two phases of the stator windings flows, the minimum T _mi2, when obtaining the average torque T _av2 is as follows.

Now, as is clear from comparing the third and sixth equations,
At startup, the same average torque as in three-phase full-wave driving can be obtained, and starting current can be saved compared to when three-phase half-wave driving is performed by adding an extra power switching element. it can. By the way, if the resistance value per phase of each stator winding is equal in any of the driving methods, the starting current in the three-phase half-wave driving becomes twice as large as that in the three-phase full-wave driving. According to the driving method described above, the starting current is increased only by about 33%.

In the following description, this driving method is called three-phase quasi-full-wave driving and is distinguished from three-phase full-wave driving or three-phase half-wave driving.

Next, a specific configuration example of the main part shown in the embodiment shown in FIG. 1 and an outline of its operation will be described to help explain the whole operation. First, FIG. FIG. 5 is a circuit connection diagram showing a typical configuration example, a constant voltage circuit section 61 using a well-known band gap reference voltage source, etc., a Hall power generator 62 formed on a silicon substrate, and other signals. It is composed of a processing circuit part.

The hall generator 62 shown in FIG. 4 corresponds to the identification band 5 shown in FIG.
Of the Hall power generator 62, the potential of one output terminal 62a increases, and the potential of the other output terminal 62b decreases. Therefore, the collector potential of the transistor 63 falls and the collector potential of the transistor 64 rises, so that most of the current flowing into the constant current transistor 65 becomes the collector current of the transistor 66.

In the circuit of FIG. 4, the resistance ratio of the resistor 67 connected to the emitter side of the constant current transistor 65 and the resistor 69 connected to the emitter side of the constant current transistor 68 is set to 3: 4. So the constant current transistor
Assuming that the collector current of 65 is 4 · I ₀ , the collector current of the constant current transistor 68 is approximately 3 · I ₀ . Also, the resistance value of the resistor 71 connected to the emitter side of the power receiving transistor 70 forming the plus side current mirror circuit and the resistance value of the resistors 74, 75 connected to the emitter side of the constant current transistors 72, 73 are made equal. Set constant current transistor 76
The resistance value of the resistor 77 connected to the emitter side of the
, The collector current of the constant current transistors 72 and 73 is approximately 3 · I ₀ at the maximum value, and the collector current of the constant current transistor 76 is approximately I _0. .

Therefore, the collector current of the transistor 66 is 4
Three-thirds are supplied from the constant current transistor 73, and only the remaining one-fourth is the first collector 78a of the transistor 78.
Supplied from At this time, the second collector 78b of the transistor 78 is connected to the load resistor 79 connected to the output terminal 6c.
With current I ₀ is supplied from, since the current I ₀ is supplied from the constant current transistor 76, the resistor 79
When the resistance value was R _0, wherein the output terminal 6c 2 · I ₀ ·
A potential R ₀ appears.

Conversely, when the Hall power generator 62 faces the S-polarized portion of the identification band 5, most of the current flowing into the constant current transistor 65 becomes the collector current of the transistor 80, and the 1 collector 81
a respectively I ₀ becomes a current flows through the second collector 81b, the current of the second collector 81b is supplied to the current mirror circuit formed by transistors 82 and transistor 83. Therefore, at this time, almost or all of the collector current of the constant current transistor 76 flows into the collector of the transistor 83, and the potential of the output terminal 6c becomes zero.

On the other hand, when the Hall power generator 62 faces the non-magnetized portion of the discriminator 5, the collector currents of the transistors 66 and 80 are substantially balanced.
All of the 6,80 collector currents are constant current transistors
The collector current of the transistors 78 and 81 is supplied from 72 and 73, and the collector current of the constant current transistor 76 is supplied to the load resistor 79 and the output terminal
The potential of 6c becomes I ₀ · R ₀ .

Thus, the output voltage of the Hall IC 6 changes in three stages depending on the position of the Hall power generator 62 facing the identification band 5.

FIG. 5 shows the relative positional relationship between the main pole and the identification band of the DC non-commutator motor constructed as shown in FIGS. 1 and 2, and the change of the position detection signal obtained from the Hall IC 6. When the relative rotation angle of the identification band 5 provided on the rotor and the Hall IC 6 disposed on the stator changes as shown by the mechanical angle or the electrical angle in FIG. Correspondingly, the output voltage of the Hall IC 6 changes as shown in FIG. 5A.

Next, FIG. 6 shows a specific configuration example of the distributor 100 shown in FIG. 1, in which two types of comparators 110 and 120 having different threshold voltages and an output processing unit 130 are used. The main part is configured and the output terminal s
The potentials of 1, n1, and z1 exclusively shift to a high potential in accordance with the three-stage potential of the input terminal P. In the circuit of FIG. 6, transistors 111 and 112 or transistors 121 and 122
Are added to add a Schmitt function to the comparator 110 or 120, respectively.

FIG. 7 shows the sequential circuit 200, the rotation direction determining circuit 300, the step controller 500, and the synchronous trigger circuit shown in FIG.
FIG. 6 shows a specific configuration example of the mode switching circuit 700, the addition / subtraction command circuit 800, the energization direction setting circuit 1000, and the initialization circuit 2000. First, the operation of the initialization circuit 2000 will be described.

In the following description of the operation of the logic circuit, all positive logic is used, and it is assumed that each input / output terminal or each signal line is in an active state when it is at a high potential, and the state of the high potential is represented by '1'. The low potential state is represented by '0'.

As can be seen from FIG. 7, the initialization circuit 2000 includes an RS flip-flop including two NAND gates each having an input / output terminal cross-coupled, and a four-input NAND.
It is constituted by a gate 2001 and a two-input NANDN gate 2002. Before the level of the J terminal shifts from '0' to '1', one of the input terminal levels of the NAND gate 2001 becomes '0'. Then, immediately after the level of the J terminal shifts to “1”, the output level of the NAND gate 2002 shifts to “0” and the initialization signal is output. This initialization signal is used for the initialization setting of the step controller 500 and the mode switching circuit 700, and is also used for the initialization setting of the sequential circuit 200 and the rotation direction determination circuit 300 via the mode switching circuit 700.

Next, the outline of the operation of the sequential circuit 200 will be described based on the output signal waveform of the position detection signal shown in FIG. The sequential circuit shown in FIG. 7 includes two NANDN gates 201, each of which has its input / output terminals cross-coupled.
A pair of gates 202 and two NAND gates 203 and 204 whose input and output terminals are respectively cross-coupled.
Gate pair and two gates connecting these gate pairs
A main part is constituted by the NAND gates 205 and 206.

The signal waveform of FIG. 5A shows the output signal of the Hall IC 6 of FIG. 1 as described above, and FIG.
The signal waveforms of C and D are output from the output terminals n1, s1, and z1 by the distributor 100 shown in FIG.
(These terminals are input terminals in FIG. 7.) The signal waveforms appearing on the respective signal lines after being distributed to the NAND gate 20 are shown in FIGS.
3, 201 and the output signal waveform of the inverter 207.

When the level of the J terminal is '0'
Immediately after the terminal level changes from '0' to '1', the NAND gate 704 constituting the mode switching circuit 700
The output levels of gates 202 and 204 are forced to '1'. Therefore, immediately after starting the motor,
The output level of the NAND gate 203, the output level of the NAND gate 201, and the output level of the inverter 207 are the same as the levels of the n1, s1, and z1 terminals, respectively.

Now, suppose that the Hall IC 6 in FIG. 1 has an electrical angle of 0 in FIG.
Assuming that it faces the position of ゜, the inverter
The output level of 207 becomes '1', and the NAND game and 201, 203
Are all '0', but when the rotor of the motor starts rotating and the Hall IC 6 faces the N-pole magnetized portion of the identification band 5, the level of the z1 terminal becomes '0'. The level of the n1 terminal shifts to “1” instead. However, here, the level of the REV terminal is held at '0', the rotor of the motor rotates in the forward direction, and the rotation direction discrimination circuit 30
The output level of the D flip-flop 301 constituting 0 is '0'
It is assumed that

Before the level of the n1 terminal changes to '1', the NAND gate 20
Since the output level of 2 is '1', the output level of the NAND gate 205 subsequently shifts to '0',
By inverting the output state of the gate pair by the NAND gate 204, the output level of the NAND gate 203 becomes "1" and the output level of the NAND gate 204 becomes "0". Due to this change, the output level of the NAND gate 206 shifts to “1”, and the output level of the inverter 207 shifts to “0”.

Subsequently, when the rotor rotates and the Hall IC 6 approaches the electrical angle of 180 ° in FIG. 5, the level of the z1 terminal shifts to “1” again as shown in FIG. 5D. ,
At this time, since the output level of the NAND gate 204 has shifted to “0”, the output level of the NAND gate 206 does not change, and the output states of the NAND gates 203 and 201 and the inverter 207 do not change.

Subsequently, when the level of the s1 terminal becomes '1', since the output level of the NAND gate 206 has become '1' before that, the output state of the gate pair by the NAND gate 201 and the NAND gate 202 is inverted. The output level of the NAND gate 201 shifts to '1', and the output level of the NAND gate 203 changes to '0'.
Move to

As a result, the sequential circuit shown in FIG. 7 has a function of reflecting an input to an output only when the input terminal is activated in a pre-ordered manner.

When the position detection signals shown in FIGS. 5B, 5C, and 5D are supplied to the n1, s1, and z1 terminals in FIG. 7, the NAND gate 203 or the n2 terminal and the NAND gate 201 are supplied. A drive command signal as shown in FIGS. 5E, 5F and 5G is output to the inverter 207 or the z2 terminal.

As can be seen from FIG. 5, when the motor is rotating in the reverse direction, the arrival order of the signals supplied to the n1, s1, and z1 terminals is n1, z1, and s1, and n1 and s1 Signal is replaced. 7 NAND gate 20
The switching circuits 8, 209, 210, 211, and 212 are added to the sequential circuit 200 to operate under the same conditions regardless of the direction of rotation of the motor.

Next, the rotation direction determination circuit 300 shown in FIG.
The order in which the n1 terminal, s1 terminal, and z1 terminal transition to the active state differs between the state in which the rotor of the motor is rotating in the forward direction and the state in which the motor rotor is rotating in the reverse direction. An outline of this operation will be described with reference to signal waveform diagrams shown in FIGS. 8 and 9.

First, the D flip-flop 301 is the NAND
While the output level of the gate 704 is "0", the output level is initialized so as to be the same as the level of the REV terminal.

8A, 8B, 8C, and 8D show signal waveforms supplied to the f1, n1, s1, and z1 terminals when the motor is rotating in the forward direction, respectively. FIG. 8E shows the output signal waveform of the NAND gate 302 at this time.
FIGS. F, G, H, I, J and K show NAND gates 303 and 3 respectively.
04, 305, 306, 307 and 308 are output signal waveforms, and FIG. 8 L and M are D flip-flop 301 and NAND gate 3 respectively.
It is an output signal waveform of 09.

In Figure 8, the time t ₁ level prior s1 terminal '1'
During this period, the RS flip-flop by the NAND gate 302 and the NAND gate 310 is reset and the NAND gate 30
Since 3 and the RS flip-flop by the NAND gate 304 are set, and the RS flip-flop by the NAND gate 306 and the NAND gate 307 are reset before that, s1
After trailing edge of the signal terminals is supplied arrives at time t _1, when the leading edge of the FG signal supplied to f1 terminal arrives, the NAND gates 305
Of the RS flip-flop by the NAND gate 306 and the NAND gate 307 is inverted, and the output level of the NAND gate 306 shifts to “1”.

In time t _2, the the trailing edge of the FG signal arrives, the the output level of the NAND gate 308 transitions to "0", the output state of the RS flip-flop by the said NAND gate 303 NAND gate 304 is inverted Subsequently, the output state of the RS flip-flop by the NAND gate 306 and the NAND gate 307 is also inverted, and the output level of the NAND gate 308 returns to “1” again. Wherein at time t ₂ D flip-flop 301 is triggered by the transition to the NAND of the output level of the gate 307 '1', the output level of the NAND gate 302 of the trigger time is because they become '0', the D
The output level of the flip-flop 301 also becomes “0”.

From time t ₃ period from time t ₄ or time t ₅ to time t ₆ repeats the same operation, as long as the motor rotor is rotated in the forward direction, the output level of the D flip-flop 301 is '0' If, at this time, a command signal for forward rotation was given via the REV terminal, the NAND gate
Since the output level of 311 becomes “0”, the output level of the NAND gate 309 becomes “1”.

On the other hand, when the motor rotor is rotating in the reverse direction, the signal waveform of each part of the rotational direction detection circuit 300 of FIG. 7 is as shown in Figure 9, the D flip-flop 301 at time t ₂ the trigger Since the output level of the NAND gate 302 immediately before the operation is always “1”, the output level of the D flip-flop 301 is also always “1”, and the REV terminal is supplied with a command signal for forward rotation. Then, the NAND
The output level of the gate 309 becomes “0”, and an output signal indicating that the rotation is in the opposite direction to the command is sent to the en terminal.

Since the output signal of the D flip-flop 301 is applied as it is to the dr terminal, the level of this terminal becomes '0' when the motor rotor is rotating in the forward direction, and the motor rotor Is '1' when is rotating in the opposite direction.

Next, the outline of the operation of the step controller 500 in FIG. 7 will be described based on the signal waveform diagram shown in FIG.

FIGS. 10A and 10B respectively show the output signal of the NAND gate 201,
FIG. 10 shows signal waveforms of the FG signal supplied to the f1 terminal, and C, D, E, F, and G in FIG.
It shows output signal waveforms of 501, 502, 503, 504, and 505. Further, in FIG. 10, H, I, J, K, L, and M are inverters 506, 3 bits and T flip-flops 507, 508, 509 constituting a down counter, and a NAND gate 5, respectively.
10 and 511 show the output signal waveforms, and FIGS. 10N and O show the output signal waveforms of the NAND gates 512 and 513, respectively, and FIG. 10a, b, c, d, e, and f
Are the um0 terminal, um1 terminal, um2 terminal, and um3 in FIG. 7, respectively.
FIG. 10 shows output signals appearing at the terminals um4, um5, and um5, respectively.
FIG. 10 shows output signals appearing at the 1 terminal, the us2 terminal, the us3 terminal, and the us4 terminal, and k, l, m, n, o, and p in FIG.
FIG. 10 shows output signals appearing at the wm0 terminal, wm1 terminal, wm2 terminal, wm3 terminal, wm4 terminal, and wm5 terminal in FIG. 7, respectively, and q, r, s, and t in FIG. ws1
The output signals appearing at the terminal, ws2 terminal, ws3 terminal, and ws4 terminal are shown.

At time t ₁ earlier Fig. 10 an output level of the NAND gate 514, 515, 516 is '1', they become the output level of the NAND gate 517 is '0' and also the leading edge of the output signal of the NAND gate 201 With the arrival already,
When the leading edge of the FG signal supplied to f1 terminal arrives at time t _1, the output level of the NAND gate 501 goes to '0', with the result, the output level of the NAND gate 502 transitions to '1' The output level of the NAND gate 515 shifts to '0' and this state is maintained. In time t _2, the the trailing edge of the FG signal arrives, the output level of the NAND gate 501 returns to "1", the output level of the NAND gate 503 transitions to "0", the output of NAND gate 504 When the level shifts to '1' and the NAND
The output level of gate 516 goes to '0'.

At time t _3, the leading edge of the FG signal arrives again, fly to an output level of the NAND gate 505 is '0', so that the output level of the NAND gate 517 is '1'
, The output level of the NAND gate 514 shifts to '0', and the output level of the NAND gate 515 changes to '1'.
Move to As a result, the output level of the NAND gate 502 becomes '0', further, the output level of the NAND gate 516 becomes '1', and subsequently, the output level of the NAND gate 504 becomes '0'. The output level of the gate 505 returns to “1”, and a series of operations ends.

After all, it said from time t ₀ to time t ₃ NAND gate 201
10A and 10B and the FG signal supplied to the f1 terminal
When changed as shown in the in between time t ₂ of to time t ₃ the output level of the NAND gate 516 is '0' T flip-flop 507 becomes is reset via the AND gate 518 at the same time T Flip-flops 508 and 509 were set and constituted by NAND gate 510 and NAND gate 519
The output state of the RS flip-flop is also inverted, and the output level of the NAND gate 510 shifts to “1”.

That is, the output signal of the NAND gate 504 becomes the preset signal of the down counter 4 bits constituted by the T flip-flops 507, 508, 509 and the RS flip-flop, the output of this counter at time t ₂ [ is preset to 1110], this preset lasts until time t _3.

When the trailing edge of the FG signal arrives at time t ₄ , the 4-bit counter starts counting down again. At time t ₁₄ , when the count value of the counter becomes [1000], the output level of the NAND gate 520 is output. Becomes "0", the output state of the RS flip-flop constituted by the NAND gate 511 and the NAND gate 521 is inverted, and the output level of the NAND gate 511 shifts to "0". As a result, the NAND gate 510 and the NAND gate 519
Output state of the RS flip-flop is also inverted,
When the output level of the ND gate 510 shifts to '0',
The T flip-flop 508 is output via the AND gate 518.
And the T flip-flop 509 is set.

Accordingly, the output of the 4-bit counter at time t ₁₄ is preset to [0110], at time t _15,
When the leading edge of the FG signal comes again, the NA
Output level '1' since returning from the T flip-flop 508 and the T flip-set flop 509 is released time t ₁₆ in 4-bit counter ND gate 511 resumes counting down.

Thereafter, the NAND gate 516 is followed by a down-counting operation until generation of a preset signal again at time t _26, at time t _26, when the leading edge of the FG signal arrives, the same operation as at time t ₂ is repeated It is.

In this way, the count value of the 4-bit counter is displayed in decimal notation during one cycle of the position detection signal, and is represented by 14, 13, 12,
11,10,9,6,5,4,3,2,1 decrease, but if the FG signal which is the clock signal of this counter is regarded as the LSB output of the virtual counter, the number of bits of the counter Is 5, and the count value is in decimal notation during one cycle of the position detection signal, and is 29, 29, 27, 26, 25, 24, 23, 2
2, 21, 20, 19, 18, 13, 12, 11, 10, 9, 8, 7,
It decreases in the order of 6, 5, 4, 3, and 2.

On the other hand, NAND gates 522, 523, 524, 525, 526, 527, 52
8, 529 and 530 constitute a decoder for decoding the lower 4 bits of the output of the 5-bit virtual counter. The NA
The ND gate 522 outputs the lower four bits of the counter [110
0], the output level becomes '0', and N
The AND gate 52 outputs the lower four bits of the counter [101
1] or [1010], the output level becomes '0', and the NAND gate 524 changes the output level to '0' when the output of the lower 4 bits of the counter becomes [1010]. When the output of the lower 4 bits of the counter becomes [1001] or [1000], the output level of the NAND gate 525 becomes “0”, and the output of the lower 4 bits of the counter becomes [0]. 1000!], The output level becomes `0`, and the NAND gate 527 changes its output level to` 0` when the output of the lower 4 bits of the counter becomes [0110]. The output level of the gate 528 becomes "0" when the output of the lower 4 bits of the counter becomes [0100], and the NAND gate 529 outputs the output of the lower 4 bits of the counter from [0011] to [0001]. The output level becomes '0' during the period, and the NAND gate 530 outputs the lower 4 bits of the counter. Tsu output of the door there is the output level when it becomes [0010] become '0'.

These decoders are used not only for generating a section signal for generating a step current waveform, but also for the purpose of FIG.
10 and the signal waveform of FIG. 10O.

That is, the output level of the the output of the virtual counter of 5 bits at time t ₃ becomes [11100] NAND gate 522 transitions to "0", whereby NAND gate 531
Of the NAND gate 532 shifts to “0”, then shifts to the output level “1” of the NAND gate 532, and as a result, the output level of the NAND gate 513 shifts to “0”. Since the output of the virtual counter of 5 bits is [01100] At time t ₁₅ the N
The output level of the AND gate 522 shifts to '0', but this time
The output level of the NAND gate 533 shifts to '0',
The output level of the NAND gate 513 shifts to “1”, and as a result, the output level of the NAND gate 532 shifts to “0”.

Further, the output level of the the output of the virtual counter of 5 bits at time t ₁₁ becomes [10100] NAND gate 528 transitions to "0", whereby NAND gate 534
Output level goes to '0', followed by NAND gate 535
Output level changes to '1', which results in the NAND gate 51
The output level of 2 shifts to '0'. Also in the time t ₂₃ 5
Since the output of the virtual counter of bits becomes [00100], the output level of the NAND gate 528 shifts to '0', but this time the output level of the NAND gate 536 shifts to '0', and subsequently, the NAND The output level of gate 512 shifts to '1',
As a result, the output level of the NAND gate 535 shifts to '0'.

The output terminals um0 to um5, us1 to us4, wm0 to wm in FIG.
The interval signals shown in FIGS. 10A to 10T are output to m5 and ws1 to ws4. A method of generating these interval signals will be described.

First, the NAND gates 528 and 522 are connected to the um0 terminal and the wm0 terminal.
The same signal waveform as the output signal is sent out, and these are used as they are as signals for the minimum value section of the step current waveform. The um5 and wm5 terminals have the NAND gate
The inverted output signals of 524 and 527 are transmitted, and these are used as signals for the maximum value section of the step current waveform. Other section signals are NAND gates 537, 538,
NAND gate 539, 540, NAND gate 541, 542, NAND gate
The signals are generated by combining output signals of five RS flip-flops constituted by 543 and 544 and NAND gates 545 and 546, and output signals of T flip-flops 507 to 509. For example, the output signal of the NAND gate 537 is used for the section signal um4, the output signal of the T flip-flop 509 is used for the section signal us3, and the NAND gate 5 is used for the section signal wm2.
The output signal of 41 is used, and the output signal of the NAND gate 539 is used as the section signal ws3.

Next, the operation of the mode switching circuit 700 in FIG. 7 will be described.

The mode switching circuit 700 includes a D flip-flop 701, a NAND gate 702, an inverter 703, AND gates 704 and 705, and a NAND gate 706.

If the output level of the D flip-flop 701 is "0" while the level of the J terminal is "0", the initialization circuit 2000 is configured immediately after the level of the J terminal has shifted to "1". Since the output level of NAND gate 2002 shifts to '0',
When the motor is started, the output level of the T flip-flop 701 is "1".

As the rotation speed of the motor increases, the FG signal is supplied to the f1 terminal, so that the step controller 500 starts a normal operation and the presetting of the counter by the NAND gate 516 is performed regularly. ,
At the midpoint of the time t ₁ from the time t ₀ of FIG. 10, the sequence circuit
When the output level of the NAND gate 529 constituting the step controller 500 has shifted to '0' when the leading edge of the output signal of the NAND gate 201 constituting the 200 has arrived, the output level of the D flip-flop 701 has changed. Shifts to '0'.

The output signal of the D flip-flop 701 is sent to the md terminal as a mode switching signal, and the synchronization trigger circuit 60
0, it is also supplied to the addition / subtraction command circuit 800 and the conduction direction setting circuit 1000. When the level of the md terminal is “0”, the mode is the quasi-full-wave drive mode, and when the level is “1”, the mode is the full-wave drive mode.

The output signal of the NAND gate 702 is sent to the terminal bk. However, when the output level of the NAND gate 702 is “0” at the terminal J and the D flip-flop 701
Becomes "0" when the output level becomes "1", and this output is supplied to the U-phase drive circuit 160 through the conduction direction switching circuit 1100.
It is used for the purpose of causing the W-phase drive circuit 1700 and the V-phase drive circuit 1900 to perform power supply to the Hall IC 6 in only one direction.

The AND gate 704 initializes the sequential circuit 200 and the rotation direction discriminating circuit 300 when the initialization circuit 2000 sends out an initialization signal or when the NAND gate 701 sends out an output signal. The D flip-flop 701 and the step controller 500 are initialized when the circuit 2000 sends an initialization signal, or when the rotation stop detector 2100 shifts the level of the qt terminal to “1”.

Next, the operation of the addition / subtraction command circuit 800 will be described with reference to the signal waveforms in FIG.

FIG. 11 is a signal waveform diagram showing a step current waveform at the time of full-wave driving and a generation process of a three-phase driving current waveform created based on the step current waveform. The signal waveforms are the same as the signal waveforms in FIGS. 10A and B, respectively, and the signal waveforms in FIGS. 11C, D, E and F are the signals shown in FIGS. 10H, I, J and K, respectively. These are the same as the waveforms, and these are shown for timing reference of other signal waveforms. The symbol at the top of the signal waveform in FIG. 11C indicates the hexadecimal representation of the count value of the lower 4 bits of the already described 5-bit virtual counter. 11G and 11H show the output signal waveforms of the NAND gate 543 and the NAND gate 545 of FIG.
FIG. 1 shows the output signal waveform of the slope generation circuit 1400 of FIG. 1. FIG. 11 shows the output signal waveforms of the step current generation circuit 1200 in FIG. 11, J, K, N, and O. L and P are 1st
11 are signal waveforms generated inside the slope synthesis circuit 1500, and FIGS. 11M and Q are drive current waveforms supplied to the U-phase drive circuit 1600 and the W-phase drive circuit 1700 in FIG. 1, respectively. 11, R and S show the energization direction setting circuit 1000 and the output signal waveform supplied to the u1 terminal and w1 terminal of FIG. 7, respectively, and FIGS. 11 T and U show the current addition circuit of FIG. It is a starting current waveform of the V phase generated by 1800.

The current waveform of FIG. 11M is obtained by adding the current waveform of FIG. 11I generated by the slope generation circuit 1400 of FIG. 1 to the current waveform of FIG. 11J generated by the step current generation circuit 1200 of FIG. is obtained by combining the slope synthesizing circuit 1500 of FIG. 1, when this, in the period from time t ₁₁ from the time t ₁₇ was the limit at a current of FIG. 11 K to the current value of Fig. 11 J by adding the current value of FIG. 11 L, in the period from time t ₂₃ from the time t ₁₇ subtracts the current value of Fig. 11 L, which is the limit at a current of 11 Figure K from the current value of Fig. 11 J This creates the current waveform of FIG. 11M.

The addition / subtraction command circuit 800 has a function of sending these addition / subtraction command signals to the slope synthesis circuit 1500.
Interval signal from the time t ₁₁ to produce a drive current waveform of the U-phase shown in FIG. 11 M to the time t _17, or the time t,
₁₇ the output signal of the RS flip-flop by the NAND gate 543, 544 as the interval signal until time t ₂₃ which constitutes a step controller 500 is available from, for producing a driving current waveform of the W-phase shown in FIG. 11 Q from the time t ₃ time t ₉
Interval signal up or NAN constituting a step controller 500 as interval signal from time t ₉ to the time t _11,
The output signal of the RS flip-flop by the D gates 545 and 546 is used. Note that these section signals are output when the level of the md terminal is “1” by the NAND gate 801 or NAN.
The signal is sent to the ua terminal or the wa terminal via the D gate 802. When the level of the md terminal is '0', the output signal of the NAND gate 201 constituting the sequential circuit 200 is sent to the ua terminal, and the wa terminal Outputs the same output signal as the signal sent to the n2 terminal.

Next, when the level of the md terminal is “1”, that is, in the full-wave driving state, the energization direction setting circuit 1000 outputs the signals of FIG. 11R and FIG. 11S to the u1 terminal, w1 The signal is sent to the energization direction switching circuit 1100 of FIG. 1 via the terminal, while when the level of the md terminal is '0', a signal having a level irrelevant to the rotational position of the rotor of the motor u1.
Send to terminal w1. In addition, as shown in Table 1, the u1 terminal, the J1 terminal, the dr terminal, the en terminal, and the dn terminal
Inverts the phase of the signal sent to the w1 terminal.

First, NAND gates 1001, 1002, 1003, 1004, 1005, 10
The switching circuit constituted by 06 sends the output signal of the NAND gate 512 constituting the step controller 500 to the u1 terminal when the motor is rotating in the forward direction and the level of the dr terminal is '0', Output signal of NAND gate 513 to w
1 terminal, but the motor is rotating in the reverse direction and dr
When the terminal level is '1', the output signal of the NAND gate 512 is sent to the terminal w1 and the NAND gate 513 is output.
Is output to the u1 terminal. This corresponds to the switching operation between the s1 signal and the n1 signal in the sequential circuit 200 according to the forward / reverse of the rotation direction of the motor. In addition. Sequential circuit 200
11A, the leading edge of the signal waveform in FIG. 11A is always equal to the N-pole portion of the identification band 5 in FIG. 2 regardless of the direction of rotation of the motor. This indicates the boundary position of the pole-magnetized portion. For example, even if the width of the non-magnetized portion of the identification band 5 becomes non-uniform due to variations in magnetization, the operation shifts to three-phase full-wave driving. Then, drive signals having a uniform width are distributed to each of the U, V, and W phases in FIG.
Further, even when the rotation direction is switched, the timing of the start of energization does not shift.

When the level of the md terminal is '0', the output levels of the NAND gates 1003 and 1006 are
Move to '1' regardless of 12,513 output.

The output signal of the NAND gates 1003 and 1006 is
07, a first exclusive OR circuit constituted by NAND gates 1008 and 1009 AND gates 1010, and inverters 1011 and NA
The signals are transmitted to the u1 terminal and the w1 terminal via a second exclusive OR circuit constituted by ND gates 1012 and 1013 and an AND gate 1014, and these exclusive OR circuits are connected to the NAND gate 1015.
When the output level of the NAND gate 1015 is "0", the input signal is transmitted as it is, and when the output level of the NAND gate 1015 is "1", the input signal is inverted in phase and transmitted.

Table 1 shows input conditions under which the output level ex of the NAND gate 1015 becomes '1'. It should be noted that, as will be described later, an acceleration signal from the error signal amplifier 1300 shown in FIG.
A deceleration command signal is supplied, and when the deceleration command is supplied, the level shifts to '1'.

In Table 1a), the level of the J terminal is “1”, the motor rotates in the forward direction, the deceleration command is sent from the error signal amplifier 1300, and the level of the dn terminal is “1”.
When shifting to, the NAND
The output level of the gate 1015 has shifted to '1'. Also, the first
In Table b), when the motor is rotating in the forward direction, a rotation direction mismatch signal is sent and the level of the en terminal becomes '0'.
The output level of the NAND gate 1015 also shifts to '1' when the shift is made, and in Table 1 c), the acceleration signal is sent from the error signal amplifier 1300 while the motor is rotating in the reverse direction. In this case, the output level of the NAND gate 1015 shifts to “1”, and the energization direction setting circuit 1000 operates to rotate the motor in the reverse direction or to maintain the rotation in the reverse direction. Furthermore, in Table 1 d) The output level of the NAND gate 1015 also shifts to "1" when the level of the J terminal is "0" and the motor is rotating in the forward direction. This is a function added for the purpose of temporarily generating a reverse torque to the motor when a rotation stop command signal is supplied from the outside while the motor is being stopped.

Next, the synchronization trigger circuit 600 shown in FIG. 7 sends a trigger signal for generating a sawtooth wave to the slope generation circuit 1400 shown in FIG. 1 through the x2 terminal. Is synchronized with the leading and trailing edges of the FG signal supplied to the f1 terminal when the level of the md terminal is '1', and supplied from the sequential circuit 200 when the level of the md terminal is '0'. It is synchronized with the leading edges of the three types of position detection signals to be performed.

First, when the level of the md terminal is '1' and the level of the x1 terminal to which the return signal from the slope generation circuit 1400 is supplied is '0', and the trailing edge of the FG signal arrives, NAND The output level of the gate 601 shifts to '0' and shifts the level of the x2 terminal to '1', but when the return signal is sent from the slope generation circuit 1400 and the level of the x1 terminal shifts to '1', the NAND gate 602 and NAND gate 603
Since the output state of the RS flip-flop is inverted and the output level of the NAND gate 603 shifts to “0”, the output level of the NAND gate 601 also returns to “1”. When the leading edge of the FG signal arrives, the output level of the NAND gate 604 shifts to '0' and the level of the x2 terminal shifts to '1', but when the level of the x1 terminal shifts to '1', the NAND gate 604 shifts the output level to '1'.
Since the output state of the RS flip-flop by the 605 and the NAND gate 606 is inverted and the output level of the NAND gate 606 shifts to '0', the output level of the NAND gate 604 is also '1'.
Return to

On the other hand, when the level of the md terminal is '0', the NAND gate
FG signal and sequential circuit 2 by switching circuit by 607, 608, 609
00, the output signal of the NAND gate 201 is switched, and at the leading edge and the trailing edge of the NAND gate 201, the output levels of the NAND gate 601 and the NAND gate 604 respectively shift to '0' and the x2 terminal Level is shifted to '1' and the circuit 200
At the leading edge of the output signal of the NAND gate 206, that is, at the trailing edge of the position detection signal sent to the z2 terminal, the output level of the NAND gate 610 shifts to '1', and the return signal from the slope generation circuit 1400 Is transmitted and the level of the x1 terminal shifts to '1', the NAND
The output state of the RS flip-flop by the gate 602 and the NAND gate 603 or the RS flip-flop by the NAND gate 605 and the NAND gate 606 or the output state of the RS flip-flop by the NAND gate 611 and the NAND gate 612 is inverted and the NAND gate 601 or the The output level of the NAND gate 604 or the NAND gate 610 also returns to “1”.

Next, FIG. 12 is a circuit connection diagram showing a specific configuration example of the error signal amplifier 1300. A terminal E is connected to a rotational speed detector (not shown in FIGS. 1 and 12). An error voltage is supplied, and the value of the
The motor is accelerated when it becomes higher than half the power supply voltage Vcc obtained by 1302, and conversely, when it becomes lower, the motor is decelerated. The md terminal is a terminal to which the output signal of the mode switching circuit 700 in FIG. 7 is supplied. As described above, the md terminal is set to "0" during three-phase quasi-full-wave driving and to "1" during three-phase full-wave driving. Become. The en terminal is supplied with a rotational direction mismatch signal from the rotational direction discriminating circuit 300 shown in FIG. 1 or FIG. 7, and when its level becomes “0”, the transistor 1303 is turned on, and The speed error voltage is configured to have the maximum value in the deceleration direction.

Now, in FIG. 12, resistors 1304 and 1305, transistors 1306 and 1308, resistor 1309, transistors 1310 and 1311, resistors 1312 and 1313, diodes 1314 and 1315 constitute an absolute value amplifier, and input division resistors 1304 and 1305 Is set to 19 to achieve a wide input dynamic range. The output current of this absolute value amplifier is
4, 1313, 1317, 1318, 131 via 1315
9. The current is supplied to a first current mirror circuit constituted by resistors 1320, 1321, 1322, and the output current of the transistor 1318 is supplied to transistors 1323, 1324, 1325, 1326,
The output current of the transistor 1319 is supplied to a third current mirror circuit composed of transistors 1330, 1331, and 1332. The current is supplied to a second current mirror circuit composed of resistors 1327, 1328, and 1329. The output currents of the transistors 1325, 1326, and 1332 are respectively sf1 terminals,
Although supplied to the sf and cf terminals, the level of the md terminal is '1'
In other words, when full-wave driving, the transistor 1333 is turned on and current is supplied only to the cf terminal, and when the level of the md terminal is '0', the transistor 1333 is turned off. State, and the transistor 1334 is turned on instead, so that current is supplied to the af1 terminal and the sf terminal.

Therefore, the output current for three-phase full-wave is supplied cf1
When the level of the md terminal is '1', the current corresponding to the potential of the E terminal is sucked in from the terminal, and the output current for three-phase quasi-full-wave is supplied. The level of the md terminal is output from the sf1 terminal and the sf terminal. Is "0", a current corresponding to the potential of the E terminal is sucked.

Also, transistors 1335, 1336, 1337, 1338, 1339,
1340 and 1341, resistors 1342 and 1343 constitute a comparator, and when the potential of the E terminal becomes lower than the potential given by the resistors 1301 and 1302, the level of the dn terminal becomes '1'. It becomes '0' when it gets higher,
This output is used as a command signal for acceleration or deceleration of the motor.

Next, FIG. 13 shows the quasi-full-wave phase switching circuit shown in FIG.
900, step current generation circuit 1200, slope generation circuit 140
FIG. 9 is a circuit connection diagram showing a specific configuration example of a slope synthesis circuit 1500 and a rotation stop detector 2100. Each input / output terminal is connected to the same location as the input / output terminal shown in FIG. Those are indicated by the same symbols.

First, a slope generation circuit 1400 includes a charge / discharge circuit including a capacitor 1401 for generating a sawtooth wave, a constant current transistor 1402, and a discharge transistor 1403, and transistors 1404, 1405, 1406, 1407, and a diode.
A first comparator centered at 1408 and a transistor
1409, diode 1410, transistors 1411, 1412, 141
3, 1414, a second comparator centered on a resistor 1415, and an output buffer stage composed of transistors 1416, 1417 and a resistor 1418, and supplies the output of the x1 terminal to the synchronous trigger circuit 600 of FIG. By supplying the output of the synchronous trigger circuit 600 to the x2 terminal, the SC terminal to which the capacitor 1401 is connected has a minimum potential equal to the forward voltage of the diode 1408 and an amplitude substantially equal to the resistance of the resistor 1414.
A saw-tooth voltage equal to twice the voltage at both ends of the waveform 15 appears.
It is equal to the arrival period of the leading edge of the position detection signal shown in FIGS. E, F, and G, and is equal to the arrival period of the leading edge and trailing edge of the FG signal during full-wave driving. That is, the synchronization trigger circuit 600 shown in FIG. 7 shifts the level of the x2 terminal to “1” when the leading edge of the input signal supplied to the NAND gates 601, 604, and 610 arrives. Transistor 1403 turns on, and the capacitor
The charge stored in 1401 is rapidly discharged. When the potential of the SC terminal becomes lower than the forward voltage of the diode 1408 due to this discharge, the base current is not supplied to the transistor 1406, and the level of the x1 terminal becomes “1”. on the other hand,
Since the synchronous trigger circuit 600 is configured so that the three RS flip-flops are reset when the level of the x1 terminal shifts to '1', the level of the x2 terminal returns to '0' at this time, As a result, the transistor 1403 is turned off, and the capacitor 1401 starts charging. In this way, charging and discharging of the capacitor 1401 are repeated, so that a saw-tooth waveform appears at the SC terminal.
The sawtooth voltage is smoothed by a resistor 1491 and a capacitor 1420, and is compared by a second comparator with the voltage across the resistor 1415. The potential of the VC terminal is always the voltage across the resistor 1415. The transistor 1413 adjusts the charging current of the capacitor 1401 so as to be equal to the sum of the voltage applied to the diode 141 and the forward voltage. Therefore,
The amplitude of the sawtooth wave voltage appearing at the SC terminal is almost twice the voltage across the resistor 1415 without depending on the repetition period of the pulse train supplied to the x2 terminal. This means that when the sawtooth wave of FIG. 11I is synthesized with the signal waveform of FIG. 11J to produce the signal waveform of FIG. 11M, a similar signal waveform is always obtained irrespective of the change in the rotation speed of the motor. This is an important function to get.

Next, the rotation stop detector 2100 includes a charge / discharge circuit including a capacitor 2101, a constant current transistor 2102, and a discharge transistor 2103, and a detection circuit mainly including transistors 2104 and 2105. When the motor is rotating, a pulse train appears at the x2 terminal, so charging and discharging of the capacitor 2101 are repeated, the potential of the QC terminal is maintained at a sufficiently low value, and the base current continues to flow through the transistor 2104. Stops rotating, the transistor 2102 becomes saturated and the base current stops flowing through the transistor 2104. At this time, the transistor 2105 is turned off, and the level of the qt terminal becomes “1”.

NAND constituting mode switching circuit 700 shown in FIG.
The output signal of the rotation stop detector 2100 is supplied to one input terminal of the gate 706. The level of the qt terminal is “1”, and the D flip-flop switches between quasi-full-wave drive and full-wave drive. If 701 is reset, the output level of the NAND gate 706 shifts to '0', so that the D flip-flop 701 is set. As described above, since the rotation stop detector 2100 initializes the mode switching circuit 700, it is possible to reliably start the motor or restart when a sudden external force is applied during rotation. It should be noted that the rotation stop detector 2100 is not always necessary if initialization setting is performed via the J terminal. For example, by temporarily shifting the level of the J terminal to “1”, the initialization circuit shown in FIG.
Since the NAND gate 2002 constituting the 2000 generates the set signal of the D flip-flop, in a device such as a video tape recorder which employs a system control by a microcomputer, the power is temporarily turned on when the power is turned on or the rotation of the motor is stopped. Then, the level of the JT terminal may be shifted to “1”.

Next, the operation of the step current generation circuit 1200 will be described with reference to the signal waveform diagram of FIG.

In FIG. 13, transistors 1201, 1202, 1203, 12
04, 1205, 1206, 1207, 1208, resistors 1209, 1210, 1211,
1212, 1213, 1214, 1215, transistors 1216, 1217, 12
18, 1219, 1220, resistors 1221, 1222, 1223, 1224, 1225 transistor 1226, resistor 1227, the cf terminal as a power receiving terminal,
The transistors 1203 to 1208 generate step current waveforms shown in FIGS.
16 to 1220 generate the step current waveforms of FIGS. 11 and 12, and the output current of the transistor 1226 controls the amplitude of the sawtooth waveform generated in the slope generation circuit 1400.

Now, the transistors 1203, 1204, 1205, 1206, 12
Output current ratio from each split collector of 07 and 1208 is 5:
5: 4: 3: 2: 1, and the transistors 1216, 1217, 121
The output current ratio from each split collector of 8, 1219, 1220 is 1: 1: 1: 1: 1, and the collector current of the transistor 1226 and the output current from each split collector of the transistor 1203 are cf terminals And the output current from each split collector of the transistor 1216 is 20% of the current supplied to the cf terminal.
The emitter area of each transistor and the resistances 1209, 1210, 1211, 1212, 1213, 1214, 1221, 12
Assuming that the resistance values of 22, 1223, 1224, 1225, and 1227 are set, the um0 to um5 terminals, the us1 to us4 terminals, and the wm of FIG.
When the interval signals shown in FIG. 10 are supplied to the 0 to wm5 terminals and the ws1 to ws4 terminals, respectively, the step current generation circuit 1200
The output current waveforms sent to the u0 terminal and w0 terminal in FIG. 13 are as shown in FIGS. 11J and 11N, respectively, and the output current sent from the step current generation circuit 1200 to the slope synthesis circuit 1500 in FIG. The current waveforms are as shown in FIGS.

The slope synthesizing circuit 1500 is supplied from the addition / subtraction instruction circuit 800 and the output signal supplied to the ua terminal and the wa terminal in FIG. 13, the sawtooth wave supplied from the slope generation circuit 1400, and the step current generation circuit 1200. The drive current waveform shown in FIG. 11M or 11Q is created based on the step current for limiting the combined current.

The sawtooth wave shown in FIG. 11 appears at the emitter of the transistor 1417 that forms the slope generation circuit 1400.
This voltage waveform has a positive offset voltage corresponding to the forward voltage of the diode 1408 as described above. Transistor 150 constituting slope synthesis circuit 1500
Reference numerals 1 and 1502 both convert the output voltage of the slope generation circuit 1400 into a current and absorb the offset voltage by the base-emitter voltage. The bases of the transistors 1501 and 1502 are connected to emitters of PNP-type transistors 1503 and 1504 whose collectors are grounded, respectively, and the resistors 1505 and 1506 connected to the bases of the transistors 1503 and 1504 are connected to the eleventh, respectively. The output current of the step current generation circuit 1200 shown in FIGS. Since the base-emitter voltages of the transistors 1503 and 1504 cancel each other out of the transistors 1501 and 1502, the transistors 1503 and 1504
01, 1502 The highest emitter potential is applied to the transistors 1503, 15
Works to limit to the base side potential of 04. As a result, the collector currents of the transistors 1501 and 1502 are as shown in FIG.
It changes as shown in P.

The collector current of the transistor 1501 is the transistor
1507, 1508, 1509, and a current outflow type current mirror circuit composed of resistors 1510, 1511. One output current of two split collectors of the transistor 1509 is supplied to a uo terminal, and the other output current is supplied to a uo terminal. Is supplied to a current mirror circuit of a current inflow type constituted by transistors 1512 and 1513, and the collector of the transistor 1513 is also connected to the u0 terminal. Here, it is assumed that the transistor 1513 has an emitter area twice that of the transistor 1512. The transistor 1512,
The common base of the transistor 1513 is connected to the collector of a transistor 1514 whose emitter is grounded. The base of the transistor 1514 is connected to the base via the ua terminal at the time of full-wave driving.
Are supplied.

When the transistor 1514 is on, the collector current of the transistor 1513 does not flow, and the output current of one of the split collectors of the transistor 1509 is added to the current supplied from the step current generation circuit 1200 to the u0 terminal. When the transistor 1514 is turned off, a current corresponding to the output current of the other split collector of the transistor 1509 is subtracted from the current supplied from the step current generation circuit 1200 to the u0 terminal. Therefore, the current supplied to the U-phase drive circuit 1600 in FIG. 1 via the u0 terminal changes as shown in FIG. 11M. Note that the transistor 1515 is turned on at the time of quasi-full-wave driving to increase the voltage-current conversion ratio of the transistor 1501.

On the other hand, the transistors 1502 and 1504 and the resistor 1506,
W constituted by transistors 1516, 1517, 1518, resistors 1519, 1520, and transistors 1521, 1522, 1523, 1524
The phase slope synthesizing circuit operates similarly, and as a result, the current supplied to the W-phase driving circuit 1700 in FIG. 1 via the w0 terminal changes as shown in FIG. 11Q.

Next, the quasi-full-wave switching circuit 900 is prepared for the operation at the time of quasi-full-wave driving, and its operation will be described with reference to a signal waveform diagram shown in FIG. The process of generating a drive signal during full-wave drive will also be described. 14A and 14B show signal waveforms supplied to the n2 terminal and z2 terminal in FIG. 13, respectively. FIG. 14C shows the output signal waveform of the slope generation circuit 1400 at the time of quasi-full-wave driving. Yes,
FIGS. 14D, E, F, and G are quasi-full-wave phase switching circuits 900, respectively.
14A and 14B show output current waveforms of transistors 906, 905, 904, and 903.
14 shows output signal waveforms of the addition / subtraction command circuit 800 supplied to the slope synthesis circuit 1500 via the WA terminal. FIGS. 14J and 14K show transistors forming the slope synthesis circuit 1500, respectively.
FIGS. 14L and M are the output current waveforms sent out to the energization direction switching circuit 1100 via the u0 terminal and the w0 terminal, respectively. Q
Are U-phase drive circuits 1600
And the current waveform supplied to the W-phase drive circuit 1700,
R and S in FIG. 14 are current waveforms supplied to the V-phase drive circuit 1900 from the current addition circuit 1800 in FIG.

The quasi-full wave phase switching circuit 900 includes transistors 901, 902, 90
3, 904, 905, 906, 907, resistor 908, 909, 911, 912, 913
A current mirror circuit having an sf terminal as a power receiving terminal, and transistors 914, 915, 916, 917, 918, 9
It is configured by a switching circuit centered at 19 and performs an operation corresponding to the step current generation circuit 1200 at the time of full-wave driving.

That is, the quasi-full-wave phase switching circuit 900 operates in the first
4 The current signals of FIG.
On the other hand, the slope synthesizing circuit 1500 operates in the same manner as in full-wave driving, and the driving current signal of FIG.
To generate a drive current signal. The energization direction switching circuit 1100 to be described next uses these drive current signals as shown in FIGS.
Two sets of drive signals P and Q are generated and supplied to the U-phase drive circuit 1600 and the W-phase drive circuit 1700.

Both the signal waveform of FIG. 14C and the signal waveform of FIG. 11I are the output signal waveforms of the slope generation circuit 1400, and the former is generated during the quasi-full-wave driving, while the latter is the full-wave Created when driving. The former repetition period is equal to the leading edge or trailing edge of the position detection signal shown in FIGS. 14A and 14B, whereas the latter repetition period is shown in FIG. 11B. Of the leading edge and trailing edge of the FG signal. On the other hand, the period of the slope portion of the drive current waveform shown in FIGS.
, The ratio of the collector currents of the transistors 906 and 905 to the collector currents of the transistors 904 and 903 will determine the period of the slope portion. Note that the resistance value of the resistor connected to the collectors of the transistors 1515 and 1524 is such that the maximum value (peak value of the trapezoidal wave) of the current supplied from the slope synthesis circuit 1500 to the u0 terminal and the w0 terminal is from the transistors 904 and 903. It is selected to be equal to the current value supplied to the u0 and w0 terminals.

Next, FIG. 15 is a diagram showing the energization direction switching circuit 1100, U of FIG.
Phase drive circuit 1600, W phase drive circuit 1700, current addition circuit 1800, V
FIG. 3 is a circuit connection diagram showing a specific configuration example of a phase drive circuit 1900.

The energization direction switching circuit 1100 includes a U-phase drive current signal supplied via the u0 terminal and a w0 terminal in response to the rotation direction determination signal supplied from the rotation direction determination circuit 300 of FIG. 7 via the dr terminal. A function of exchanging the drive current signal of the w-phase supplied through the switch, a function of switching the polarity of these drive current signals according to the levels of the u1 terminal and the w1 terminal, and bk
When a stop signal is supplied from the mode switching circuit 700 of FIG. 7 through the terminal, the U-phase drive circuit 1600, the W-phase drive circuit 1700, and the V-phase drive circuit 1900 have a function of energizing in only one direction. Have.

Now, assuming that the motor is rotating in the forward direction and the level of the dr terminal is '0', the energizing direction switching circuit 11
The transistors 1101 and 1102 included in 00 are off, and the transistor 1103 is on.
Therefore, the drive current supplied to the u0 terminal is supplied to the transistors 1105, 1106, 1107, 110 via the transistor 1104.
8, 1109, supplied to the current outflow type current mirror circuit constituted by the resistors 1110, 1111, 1112, 1113, the drive current supplied to the w0 terminal via the transistor 1114,
Transistors 1115, 1116, 1117, 1118, 1119, resistor 112
0, 1121, 1122, and 1123 are supplied to a current outflow type current mirror circuit. Further, the collector current of the transistor 1109 is
5, 1226, 1127, and resistors 1128, 1129, 1130 are supplied to a current inflow type current mirror circuit, and the collector current of the transistor 1119 is
It is supplied to a current mirror circuit of a current inflow type constituted by 1, 1132, 1133, 1134 and resistors 1135, 1136, 1137. On the other hand, during quasi-full-wave driving, the output current from the error signal amplifier 1300 via the sf1 terminal is
1139, 1140, 1141, 1142, 1143 Resistance 1144, 1145, 1146,
The current is supplied to a current outflow type current mirror circuit constituted by 1147 and 1148.

First, during full-wave driving, when the level of the u1 terminal is “1”, the transistor 1149 is on, and the transistors 1150 and 1151 are off.
At this time, the collector current of the transistor 1107 is supplied to the upper drive circuit forming the U-phase drive circuit 1600 via the diode 1152, but the collector current of the transistor 1108 is absorbed by the transistor 1149 via the diode 1153,
Also, since no current is supplied via the sf1 terminal,
No current is supplied to the lower drive circuit constituting the U-phase drive circuit 1600. Conversely, when the level of the u1 terminal is “0”, the transistor 1149 is off and the transistors 1150 and 1151 are on. At this time, the collector current of the transistor 1108 is
Is supplied to the lower drive circuit constituting the U-phase drive circuit 1600, but the collector current of the transistor 1107 is absorbed by the transistor 1150, so that the current is supplied to the upper drive circuit constituting the U-phase drive circuit 1600. Not supplied.

The w-phase circuit block operates similarly to the U-phase circuit block, and w1
Transistor when terminal level is '1'
The drive current is supplied to the upper drive circuit constituting the W-phase drive circuit 1700 via 1117 and the diode 1155, and when the level of the w1 terminal is '0', the lower drive circuit is provided via the transistor 1118 and the diode 1156. Is supplied with a drive current.

Thus, the driving current waveforms shown in FIGS. 11M and Q correspond to the upper driving circuit and the lower driving circuit of the U-phase and the W-phase, respectively, in accordance with the levels of the signals shown in FIGS. Distributed to the circuit.

During quasi-full-wave drive, the error signal amplifier 1
Since 300 output currents are supplied, transistors 1138-1
The current mirror circuit constituted by 143 and the resistors 1144-1148 is activated, and the period in which the drive current is not supplied to the upper drive circuit of each phase as shown in FIGS. A drive current is supplied to the lower drive circuit. That is, at the time of the first of the 14 view time t ₉ to FIG. 14 for current supplied via u0 terminal as shown in L is zero, the level of u1 terminal '1' is an even diode 1152 The current supplied to the upper drive circuit of the U-phase via the inverter becomes zero, while the collector current of the transistor 1140 is supplied to the lower drive circuit via the diode 1157. It is assumed that the current mirror ratio is set so that the collector current of the transistor 1140 is one half of the current supplied through the sf1 terminal. At time t ₁₀ when u0 current supplied through the terminal reaches the maximum value, is supplied to the upper driving circuit of the U-phase current of the same value through a diode 1152, all of the collector current of the transistor 1140 Since the current is absorbed by the transistor 1127, the current supplied to the U-phase lower drive circuit via the diode 1157 becomes zero. These operations are the same for the W phase.

When the motor is rotating in the reverse direction and the level of the dr terminal is “1”, the transistor 1102 is turned on and the transistor 1103 is turned off. At this time, the current supplied from the u0 terminal is supplied to the W-phase current mirror circuit via the transistor 1158, and the current supplied from the w0 terminal is supplied to the U-phase current mirror circuit via the transistor 1159. This means that the U-phase drive signal and the W-phase drive signal have been exchanged. The replacement of the drive signal corresponds to the replacement of the position detection signal in the sequential circuit 200.

When the level of the bk terminal becomes '0', the transistor 1260 is turned off, and as a result, the transistors 1261, 1262,
1263 is turned on to absorb the drive current supplied to the lower drive circuit of each phase, so that only the upper drive circuit of each phase becomes active, and the stator windings 1 to 3 in FIG. hole
Only the circuit current of IC6 flows. Therefore, although the motor does not generate a rotational torque, the Hall IC 6 can detect the position even when the motor is stopped.

Next, the U-phase drive circuit 1600, the W-phase drive circuit 1700, and the V-phase drive circuit 1900 are simply current amplifiers configured by combining current mirror circuits. The final stage of the upper drive circuit uses an NPN-type power transistor and has a special configuration to minimize the residual voltage when the maximum current is supplied to the stator windings 1 to 3. The circuit 1600 will be described as an example.

When the lower drive circuit of the U-phase drive circuit 1600 uses the current mirror circuit constituted by the transistors 1601 and 1602 and the transistor 1603 constituting the final stage as it is also in the upper final stage, the connection between the collector and the emitter of the transistor 1602 The current is not smaller than the sum of the base-emitter voltage of the transistor 1601 and the base-emitter voltage of the transistor 1602 plus the saturation voltage of the preceding PNP transistor, and is about 1.8 V at the minimum.

On the other hand, the transistor 16 constituting the upper final stage
In 04, the collector-emitter voltage can reach the base-emitter voltage plus the saturation voltage of the preceding transistor 1605, which is about 1.1V at minimum.

Now, the current adding circuit 1800 includes transistors 1801 and 1802 that take out a current equal to the driving current supplied to the upper driving circuit of the U-phase distress circuit 1600 and a transistor that takes a current equal to the driving current supplied to the lower driving circuit. 1803, 18
04 and transistors 1805 and 1806 that take out a current equal to the drive current supplied to the upper drive circuit of the W-phase drive circuit 1700.
And transistors 1807 and 1808 for extracting a current equal to the drive current supplied to the lower drive circuit, and diodes 1809 and 18
10, 1811, 1812, the transistor 18
The collector of the transistor 1807 is connected to the collector of the transistor 1807, and the connection point is connected to the anode of the diode 1809.The collector of the transistor 1806 and the collector of the transistor 1804 are connected to this connection point. The anode of the diode is connected
The cathode of 1812 is connected to the cathode of the diode 1809, the collector of the transistor 1802 and the collector of the transistor 1808 are connected, and the connection point is connected to the cathode of the diode 1810, the transistor
The collector of the transistor 1805 is connected to the collector of the transistor 1803, and the connection point is connected to the cathode of the diode 1811. The anode of the diode 1811 is connected to the cathode of the diode 1810. Further, the anodes of the diodes 1810 and 1811 are connected to the power receiving point vp of the drive current of the upper drive circuit of the V-phase drive circuit 1900, and the cathodes of the diodes 1809 and 1812 drive the lower drive circuit of the V-phase drive circuit 1900. It is connected to the current receiving point vn.

Here, the magnitude of the current supplied to the power receiving point up of the drive current of the upper drive circuit of the U-phase drive circuit 1600 is Iup, and the magnitude of the current supplied to the power receiving point un of the drive current of the lower drive circuit Is Iun, the magnitude of the current supplied to the power receiving point wp of the drive current of the upper drive circuit of the W-phase drive circuit 1700 is Iwp,
Assuming that the magnitude of the current supplied to the power receiving point wn of the drive current of the lower drive circuit is Iwn, from the collectors of the transistors 1801 and 1802, a current of the magnitude of Iup flows out, and the transistors 1803 and 1803, respectively. The collector of 1804 absorbs a current of the magnitude of Iun, respectively, and the collectors of the transistors 1805 and 1806 cause a current of the magnitude of Iwp to flow out, and the transistors 1807 and 180
Each of the eight collectors absorbs a current of the magnitude of Iwn.

Therefore, when the value of Iup becomes larger than the value of Iwn, the difference current is supplied to the vn point via the diode 1809, and when the value of Iwp becomes larger than the value of Iun, the difference current becomes Supplied to the vn point via 1812 and also
When the value of Iun becomes larger than the value of Iwp, the difference current is supplied to the point vp via the diode 1811, and the value of Iwn becomes Iwp.
When the value becomes larger than the value of up, the difference current is supplied to the point vp via the diode 1810.

That is, the value Ivp of the drive current supplied from the current addition circuit 1800 to the upper drive circuit of the V-phase drive circuit 1900 and the value Ivn of the drive current supplied to the lower drive circuit are given by the following equations.

Thus, transistors 1802 and 18
08 and the pair of transistors 1803 and 1805 allow the difference current between the current flowing into the U or W phase and the current flowing out of the W or U phase to flow into the V phase,
A pair of the transistor 1801 and the transistor 1807 and a pair of the transistor 1804 and the transistor 1806 operate so that the difference current between the current flowing out of the U-phase or the W-phase and the current flowing in the W-phase or the U-phase flows out of the V-phase.

The current waveforms shown in FIGS. 14R and S were obtained from the equations 7 and 8 based on the current values obtained from the current waveforms shown in FIGS. N, O, P and Q, respectively. The results are plotted, and the current waveforms of FIGS. 11 and 12 are also obtained in the same manner. Of course, it has been confirmed that the same current waveform can be obtained not only in the calculation but also in the actual circuit shown in FIG.

Returning to FIG. 1, the outline of the operation described so far is summarized as follows.

First, in a state where the level of the J terminal is '0' and the rotor of the motor is stopped, at least one of the U terminal, the V terminal, and the W terminal is at a high potential,
A current is supplied to the Hall IC 6 via one of the stator windings 1 to 3 and the current limiting resistor 8 to detect the stationary position of the rotor, and the Hall IC 6 is set to a high potential according to the stationary position of the rotor. Generates intermediate potential and low potential outputs. The position detection signal is distributed by the distributor 100 in accordance with the output level of the Hall IC 6, and this position detection information is supplied to the quasi-full-wave phase switching circuit 900 via the sequential circuit 200. Is 0, the sequential circuit 200 operates as a simple buffer, and power is supplied from the U-phase drive circuit 1600, the W-phase drive circuit 1700, and the V-phase drive circuit 1900 to the stator windings 1 to 3. Is not done.

When the level of the J terminal shifts to “1”, the driving circuit of each phase determines which of the U terminal, the V terminal, and the W terminal based on the position detection information supplied to the quasi-full-wave phase switching circuit 900. To generate a rotational torque in the rotor. At this time, the rotation electric angle of the third IC is 6
Assuming that the hall IC 6 is stopped accidentally at the position of 0 °, that is, at the boundary between the N pole and the S pole of the discrimination band 5 or at the position where the rotational electrical angle is 390 °, the Hall IC 6 is in the absence of the discrimination band 5 in any case. Since the same output as when facing the magnetized portion is generated and the stator windings 1 to 3 are energized based on the information, FIG.
As can be seen from the characteristic curve, the rotor generates a rotational torque in the reverse direction. However, normal position detection information is obtained by a very slight movement of the rotor, and thereafter the order of reception of position detection signals is regulated by the sequential circuit 200, so that smooth rotation can be maintained.

When the rotor starts rotating, an FG signal from the power generation winding 7 appears, so that the output level of the D flip-flop 701 (FIG. 7) constituting the mode switching circuit 700 shifts to "0" at a predetermined timing. Then, the energization mode to the stator windings 1 to 3 is switched to three-phase full-wave drive, and the torque characteristics of the motor are as shown by the envelope of the characteristic curve shown in FIG. 3C.

Even after the energization mode shifts to three-phase full-wave drive, if the motor speed decreases until the FG signal disappears due to a sudden load change, the output level of the D flip-flop 701 returns to '1'. , The energization mode is again the three-phase quasi-full-wave drive.

On the other hand, when the level of the J terminal shifts to “0” in the state where the energization mode is the three-phase full-wave drive, D
As long as the output level of the flip-flop is '0', the 15th
The level of the bk terminal in the figure is held at '1' and the stator windings 1 to
The energization to 3 is continued. At this time, since the level of the J terminal is “0”, as shown in Table 1, the output level of the NAND gate 1015 (FIG. 7) constituting the conduction direction setting circuit 1000 becomes “1”. The phase of the output signal sent from the energizing direction setting circuit 1000 to the energizing direction switching circuit 1100 is inverted, the energizing direction to the stator windings 1 to 3 is reversed, and the motor is rapidly decelerated. When the rotation speed of the motor becomes close to zero and the FG signal disappears or the rotation stop detector 2100 generates an output signal, the output level of the D flip-flop 701 shifts to “1”. Also shifts to '0', and energization to the stator windings 1 to 3 is stopped.

Also, if a forward command signal is applied from the REV terminal while the motor continues to rotate in the reverse direction, such as when switching between forward and reverse rotation, the commanded rotation direction matches the actual rotation direction. The error signal amplifier 1300 and the passing electric direction setting circuit 100
A rotation direction mismatch signal is supplied to 0. This makes the first
When the level of the en terminal in FIG. 1 becomes '0', the transistor 1303 which was in the off state until then turns on and the E 130
It is the same as when the potential of the terminal drops to near zero.
The error signal amplifier 1300 supplies the maximum output current to the step current generation circuit 1200 via the cf terminal (during full-wave driving). On the other hand, when the rotation direction mismatch signal is supplied to the energization direction setting circuit 1000, as can be seen from Table 1, the output level ex of the NAND gate 1015 in FIG. The direction of energization to 1-3 is reversed, and the motor is rapidly decelerated. When the rotation speed of the motor exceeds zero and starts to rotate in the forward direction, the rotation direction determination circuit 300 shown in FIG.
The output level of the D flip-flop 301 constituting the
, The level of the dr terminal shifts to '0', and the level of the en terminal shifts to '1'. Thereafter, the motor is accelerated in the same manner as when starting from a stopped state.

FIG. 16 is a sectional view of a torque generating portion of a motor prepared for explaining a mechanism for generating vibration and noise. In FIGS. 16A and 16B, reference numeral 11 denotes a rotor yoke to which a permanent magnet 4 is fixed. And 12 is the stator windings 1a, 1b on it
Are arranged on the stator yoke, and all curves with arrows represent lines of magnetic force.

At the relative position between the rotor and the stator shown in FIG. 16A, since the direction of the magnetic flux linking the stator windings 1a and 1b is perpendicular to the magnetization direction of the permanent magnet 4, Child winding 1
a and 1b generate a force in a direction parallel to the magnetization direction, and this becomes the rotational torque of the motor.

However, at the relative position between the rotor and the stator shown in FIG. 16B, the direction of the magnetic flux linking the stator windings 1a and 1b is parallel to the magnetization direction of the permanent magnet 4, and The torque not only becomes zero, but also generates a force in a direction perpendicular to the magnetization direction of the permanent magnet 4. In the relative positional relationship shown in FIG. 16B and the direction of energization to the stator windings 1a and 1b, each stator winding generates a repulsive force to lift the rotor, and is applied to each stator winding. When the energizing direction is reversed, a force for attracting the rotor to the stator is generated, and the repetition of the repulsive suction causes a large factor of the vibration of the motor, and the vibration also generates noise at the same time.

The magnitudes of the repulsive force and the suction force are minimized at the relative position in FIG. 16A, and maximized at the relative position in FIG. 16B, but gradually increase or increase at the intermediate position depending on the position. Decreasing. Therefore, in order to reduce vibration and noise, it is only necessary to reduce fluctuations in repulsion and suction per one rotation of the rotor. Since there are three sets of stator windings, a drive current waveform may be created such that the sum of the repulsive force and the attractive force of each stator winding hardly changes due to the fluctuation of the rotor. .

Specifically, in the signal waveform of FIG. 11 M, the time t ₁₁
Slope from to time t ₁₃ largely contributes to the vibration and noise, the case of increasing the linearly current from time t _11, the current value at time t ₁₃ previously set to a current waveform that maximizes It has been confirmed by calculation that the fluctuations in the repulsion force and the suction force increase sharply as the slope becomes steeper. In other words, in order to reduce the vibration and noise by minimizing the force in the direction of the rotating shaft of the motor in the three-phase full-wave starting with 180 ° energization, the section from the start of energization to 60 ° and the section from 60 ° to the end of energization are required. Slope management is an important factor.

On the other hand, in order to reduce the fundamental frequency component of the torque fluctuation of the motor, as is clear from the comparison between the torque characteristics of FIG. 3A and the torque characteristics of FIG. The management of the shape of the energization waveform in the section from the start to 30 ° and the section excluding the 30 ° section until the end of energization is an important factor.

In the DC non-commutator motor shown in FIG. 1, an arbitrary drive current waveform can be generated by the step controller 500 and the step current generation circuit 1200, as is clear from the signal waveforms of FIGS. The drive circuit of each phase supplies a current proportional to the drive current generated by the step current generation circuit 1200 and the slope synthesis circuit 1500 to the stator windings 1 to 3. Therefore, a current waveform that minimizes vibration and noise during rotation of the motor can be easily created. That is, during full-wave driving, in the step current generating circuit 1200 shown in FIG.
By changing the ratio of the resistance values of 1215, 1221 to 1224, 1225, and 1227, the shapes of the drive current waveforms in FIGS. 11M and 11Q can be freely changed. In the quasi-full-wave phase switching circuit 900, the slope of the drive current waveform in FIGS. 14L and 14M can be selected to an optimum value by changing the ratio of the resistance values of the resistors 908 to 913.

By the way, as can be seen from the specific configuration examples of the step current generation circuit 1200, the quasi-full-wave phase switching circuit 900, the slope synthesis circuit 1500 and the energization direction switching circuit 1100 in FIG. Even if a drive current signal is just created, the circuit scale becomes considerable. In general, not only the embodiment shown in FIG. 1 but also a large number of circuit elements are required in order to generate a drive current waveform that is carefully calculated in order to minimize motor vibration and noise or torque ripple. .

However, in the direct current commutator motor of the present invention, U
When generating drive current waveforms for three phases of V, W, and W phases, the current addition circuit 1800 shows the drive current waveforms for the three phases of the U phase and the W phase in equations 7 and 8 based on the drive current signals. By performing the above calculations, a V-phase drive current signal is created without increasing the circuit scale. That is, as described above, when the current value flowing into the U phase becomes larger than the current value flowing out from the W phase, the current adding circuit 1800 causes the difference current to flow out from the V phase and flow out from the W phase. When the current value becomes larger than the current value flowing into the U phase, the difference current flows into the V phase. Therefore, the current addition circuit
A V-phase drive waveform can be created by adding only a few circuit elements that make up the 1800.
Since the 1800 produces V-phase inflow current and outflow current from U-phase and W-phase inflow current and outflow current, the drive current waveforms of U-phase and W-phase are out of balance and are not completely similar. However, the sum of the outflow currents from the U, V, and W phases is always equal to the sum of the inflow currents into the U, V, and W phases.

As is apparent from the above description, the DC non-commutator motor of the present invention has a first phase drive current whose amplitude is proportional to the output of the error signal amplifier 1300, based on the output of the position detecting means. Drive signal generating means for generating a second phase drive current (in the embodiment shown in FIG. 1, the distributor 100, the sequential circuit 200, the step controller 500, the synchronous trigger circuit 600, the mode switching circuit 700, the addition / subtraction command circuit 800 The quasi-full-wave phase switching circuit 900, the conduction direction switching circuit 110, the step current generating circuit 1200, the slope generating circuit 1400, and the slope synthesizing circuit 1500 constitute a driving signal generating means), and the first or second phase. The difference current between the current flowing into the phase and the current flowing out of the second phase or the first phase flows into the third phase, and the current flowing out of the first phase or the second phase flows into the second phase or the first phase. Flow from the third phase Differential current generating means for (in the embodiment shown in FIG. 1, the drive signal of the U phase and the W
A current addition circuit 1800 for adding a phase drive signal to generate a V-phase drive signal, and supplying a current corresponding to the U-phase, W-phase, and V-phase drive signals to each of the stator windings The U-phase drive circuit 1600, the W-phase drive circuit 1700, and the V-phase drive circuit 1900 constitute difference current generating means. ), A drive signal for three phases can be generated from a drive signal for two phases only by adding a few circuit elements for constituting the current addition circuit 1800. Further, in the DC non-commutator motor of the present invention, the driving current of the third phase is generated by the differential current generating means instead of the addition of the driving voltages as in the conventional art. With this configuration, the drive current value of the third phase can be accurately generated.

[Brief description of the drawings]

FIG. 1 is a block diagram of a DC non-commutator motor according to an embodiment of the present invention, FIG. 2 is a schematic diagram of a motor portion configured to carry out the present invention, and FIG. FIG. 4 is a diagram of the internal circuit connection of the Hall IC, and FIG. 5 is a signal waveform corresponding to the magnetization pattern of the identification band for explaining the processing operation of the position detection signal. FIG. 6, FIG. 6 is a circuit connection diagram showing a configuration example of the distributor, FIG. 7 is a sequential circuit, a rotation direction determination circuit,
Logic circuit diagrams showing configuration examples of a step controller, a synchronous trigger circuit, a mode switching circuit, an addition / subtraction command circuit, a conduction direction setting circuit, and an initialization circuit, FIG. 8, FIG. 9, FIG.
11 and 14 are signal wave diagrams for explaining the operation of each block in FIG. 1, FIG. 12 is a circuit connection diagram showing a configuration example of an error signal amplifier, and FIG. Circuit connection diagram showing a specific configuration example of a wave phase switching circuit, a step current generation circuit, a slope generation circuit, a slope synthesis circuit, and a rotation stop detector. FIG. 15 shows a conduction direction switching circuit, a U-phase drive circuit, FIG. 16 is a circuit diagram showing a specific configuration example of a phase drive circuit, a current addition circuit, and a V-phase drive circuit. FIG. 16 is a sectional view of a torque generating portion of the motor. 1,2,3 ... stator winding, 4 ... permanent magnet, 6 ... Hall I
C, 200: sequential circuit, 500: step controller, 6
00: Synchronous trigger circuit, 700: Mode switching circuit, 800:
… Addition / subtraction command circuit, 900 …… Semi-full wave phase switching circuit, 1100…
... energization direction switching circuit, 1200 ... step current generation circuit,
1300 …… Error signal amplifier, 1400 …… Slope generation circuit,
1500: slope synthesis circuit, 1600: U-phase drive circuit, 17
00: W-phase drive circuit, 1800: Current addition circuit, 1900:
V-phase drive circuit.

Claims (1)

(57) [Claims] A rotor having a three-phase stator winding, a permanent magnet having a magnetized portion facing the stator winding, and a position detection signal obtained by detecting a rotational position of the rotor. A position detecting means for generating, a command voltage amplifier for accelerating or decelerating the rotation speed of the motor, and a first phase drive whose amplitude is proportional to an output of the error signal amplifier based on an output of the position detecting means. A drive signal generating means for generating a current and a drive current of the second phase, and a difference current between a current flowing into the first phase or the second phase and a current flowing out of the second phase or the first phase flows into the third phase. And a differential current generating means for causing a differential current between a current flowing out of the first phase or the second phase and a current flowing in the second phase or the first phase to flow out of the third phase. .