JPH0650955B2 - DC non-commutator motor - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a non-commutator motor used under a DC power supply.

2. Description of the Related Art In recent years, DC non-commutator motors have been widely used in many audio equipment, video tape recorders, and even floppy disk devices, and their application has expanded to their fan motors for air cooling. is doing.

Conventionally, a two-phase or three-phase half-wave drive system or full-wave drive system has predominantly been used as a DC non-commutator motor of this type. Each drive method has advantages and disadvantages,
For example, the three-phase driving method requires a smaller number of driving power elements than the two-phase driving method, but requires a large number of position detecting elements for detecting the rotational position of the rotor. By the way,
Compared to operating under a single power supply, 2
The phase full-wave drive method requires eight power transistors and two Hall elements, and the three-phase full-wave drive method requires six power transistors and three Hall elements.

Conventionally, many attempts have been made to reduce the number of position detection elements in the three-phase drive method, and a representative technique thereof is disclosed in US Pat. No. 3,577,053 (hereinafter abbreviated as Document 1). ing. In the above-mentioned Document 1, in a three-phase half-wave drive type non-commutator motor, an identification band having first, second, and third components having different light reflectances is provided on a rotor, and the identification band is provided. By irradiating a light beam and detecting the reflected light by the light receiving element, the change in the rotational position of the rotor is recognized as a three-step change in the output level of the light receiving element, and the phase winding depending on the level is energized. The configured device is shown.

In the method shown in the above-mentioned document 1, the three-phase half-wave drive is enabled by the unique position detection element and the identification band for position detection. Limited to In other words, if the form shown in the above-mentioned document 1 is used, only 3 types of detection can be performed per 360 ° electrical angle, and therefore switching of the energization state to each phase winding is inevitably allowed 3 types. In order to realize the three-phase full-wave drive method which requires switching of the six energization states, an additional position detecting element and an identification band are further required.

By the way, in this type of motor, it is preferable to make the current waveform supplied to the stator winding sinusoidal in order to reduce vibration and torque ripple during rotation.
In the publication (hereinafter, abbreviated as reference 2), since the position detection signal obtained from the Hall element does not have an ideal sine waveform due to various factors, the sine wave information is stored in a digital memory in advance. The information in the memory is sequentially read by an output signal (generally called an FG signal) of a frequency generator connected to the motor and converted into an analog voltage to generate a sinusoidal drive current close to ideal. A DC non-commutator motor is shown.

Problems to be Solved by the Invention However, the method disclosed in Document 2 has a considerably larger circuit scale than the conventional method of performing processing in an analog manner, and the driving method changes smoothly. It also has the drawback that the resolution of the digital circuit must be considerably increased in order to generate the current.

Means for Solving the Problems In order to solve the above-mentioned problems, a DC non-commutator motor according to the present invention is provided with a position detecting means for detecting a rotational position of a rotor and generating a position detection signal, and an external power supply. An error signal amplifier that generates a drive command current that depends on the voltage or current, a slope generation circuit that generates a sawtooth wave with a cycle that depends on the arrival cycle of the edge of the position detection signal, and the sawtooth wave A slope synthesizing circuit for obtaining a trapezoidal drive signal by adding a signal waveform obtained by limiting the amplitude to a level proportional to the drive command current, and the stator winding by amplifying the drive signal. Is provided with a drive circuit for supplying to.

Operation In the present invention, the above-described configuration adds a slope to the rectangular-wave drive signal waveform, so that current switching to each phase winding becomes smooth.

Examples Hereinafter, examples of the present invention will be described with reference to the drawings.

FIG. 2 is a developed view of the essential parts of a motor configured to carry out the present invention. The three-phase stator windings 1, 2,
3 are star-shaped connected to each other, and a permanent magnet 4 mounted on a rotor (not shown) is arranged facing the stator windings 1 to 3.

The main portion of the permanent magnet 4 is occupied by a main magnetic pole magnetized to 8 poles, and the inner peripheral portion (not shown in the drawing, but on the upper side of the permanent magnet 4 in FIG. The lower part is the outer peripheral part.), The first component part 5a magnetized with the N pole, the second component part 5b not magnetized, and the S component magnetized with the S pole. The third component portion 5c has annular identification bands 5 alternately arranged in the circumferential direction.

Further, a Hall IC (integrated circuit in which a Hall power generator and other circuits coexist on a chip) 6 provided as a rotor rotational position detecting element is arranged facing the identification band 5.

On the other hand, a power generation band magnetized to 96 poles is provided on the outer peripheral side of the main magnetic pole of the permanent magnet 4, and a zigzag having 96 power generation element portions facing the power generation band and radially diffracted. The power-generating winding 7 is arranged.

Further, the lead wires of the stator windings 1, 2 and 3 are connected to the first power supply terminal U, the second power supply terminal V and the third power supply terminal W, respectively, and the center point of the star connection is It is connected to the terminal X.

The Hall IC 6 has a positive side power supply terminal 6a, a negative side power supply terminal 6b, and an output terminal 6c, and the lead wire of the generator winding 7 is connected to the output terminals 7a and 7b.

Now, FIG. 1 is a block diagram of a DC non-commutator motor according to an embodiment of the present invention. In FIG. 1, a block 10 is an internal connection of the motor block shown in FIG. In the motor block 10, the midpoint terminal X and the positive side power supply terminal 6a of the Hall IC 6 are
A current limiting resistor 8 is connected between the two, and the negative side power supply terminal 6b of the Hall IC 6 and the other output terminal 7 of the power generation winding 7 are connected.
a is connected to the rotation detection terminal F.

A position detection signal whose level changes in three steps depending on the rotational position of the motor is output to the position detection terminal P by a processing circuit (described later) incorporated in the Hall IC 6, and this position detection signal is distributed. The signal is distributed by the device 100 to the signal lines of the three systems which are sequentially activated according to the input level. These outputs are subjected to conditioning processing by the sequential circuit 200, and the output of the distributor 100 is REV.
It is used together with the rotation direction command signal applied to the terminal to determine the rotation direction of the motor by the rotation direction determination circuit 300.

Further, the signals appearing at the rotation detection terminal F and the ground terminal G are amplified by the amplifier 400 to be sufficiently amplified, and then the rotation direction determination circuit 300 and various energization timings are generated as a clock signal for creating timing. It is supplied to the step controller 500 and the synchronous trigger circuit 600 that determines the timing of generation of the slope added to the currents supplied to the stator windings 1 to 3.

Further, the output of the sequential circuit 200 is a mode switching circuit for switching between three-phase quasi-full-wave driving and three-phase full-wave driving based on the outputs of the step controller 500, the synchronous trigger circuit 600, and the step controller 500. 700,
It is supplied to the addition / subtraction command circuit 800 that switches between the rising slope and the falling slope, and the quasi-full-wave phase switching circuit 900 that distributes the drive current in three-phase quasi-full-wave driving. The output of the rotation direction determination circuit 300 is An energizing direction setting circuit 1000 that sets the energizing direction to the stator windings 1 to 3, an energizing direction switching circuit 1100 that switches the energizing direction based on the output of the energizing direction setting circuit 1000, and a voltage applied to the E terminal. It is supplied to an error signal amplifier 1300 that generates a command signal for current and motor acceleration or deceleration that depends on the error voltage, and the output of the step controller 500 is the mode switching circuit 700, the addition / subtraction command circuit 800, and the full-wave drive mode. Is supplied to a step current generation circuit 1200 that generates a step current waveform of the output of the mode switching circuit 700, the sequential circuit 200, the rotation direction determination circuit 300, and the addition / subtraction. Command circuit 800
And the current supply direction setting circuit 1000 and the current supply direction switching circuit 1100, and the error signal amplifier 1300, and a slope generation circuit 1400 that generates a slope to add to the current supplied to the stator windings 1 to 3. ing. Signals are exchanged between the synchronous trigger circuit 600 and the slope generation circuit 1400, and the output of the slope generation circuit 1400 and the output of the addition / subtraction command circuit 800 are both the quasi full-wave phase switching circuit. 900 or the step current generator
It is supplied to a slope synthesis circuit 1500 that adds a slope to the step-like current output signal output from 1200, and the output current of the slope synthesis circuit 1500 is the quasi-full-wave phase switching circuit.
900 or the output current of the step current generation circuit 1200 is superimposed.

On the other hand, the acceleration or deceleration command signal from the error signal amplifier 1300 is supplied to the energization direction setting circuit 1000, and the output current from the error signal amplifier 1300 is the slope generation circuit 1400 and the quasi full-wave phase switching circuit 900. Also, the output currents of the quasi-full-wave phase switching circuit 900 and the step current generation circuit 1200 are supplied to the step current generating circuit 1200, and the output currents of the quasi full-wave phase switching circuit 900 and the step current generating circuit 1200 are passed through the energizing direction switching circuit 1100.
1600 and the W-phase drive circuit 1700, and also to the slope synthesis circuit 1500, the U-phase drive circuit 16
The main output current of 00 and the main output current of the W-phase drive circuit 1700 are respectively supplied to the U terminal to which the U-phase stator winding 1 is connected and the W terminal to which the W-phase stator winding 3 is connected. , Said U
The output currents of a part of the phase drive circuit 1600 and the W phase drive circuit 1700 are added by the current addition circuit 1800 to obtain the V phase drive circuit.
1900, the output current of the V-phase drive circuit 1900 is V
The phase stator winding 2 is supplied to the connected V terminal.

In the embodiment shown in FIG. 1, a command signal for stopping / rotating the motor is applied to the J terminal, and this command signal is directly supplied to the energization direction setting circuit 1000 so that a rotation stop command signal for the motor is externally supplied. In addition to being used to generate a brake signal when applied, it is also used to initialize the step controller 500 and the mode switching circuit 700 via the initialization circuit 2000. The output signal of the amplifier 400 is also supplied to the rotation stop detector 2100, and the rotation stop detector 21
The output signal of 00 is supplied to the mode switching circuit 700,
When the rotation of the motor is stopped, the output state of the mode switching circuit 700 is forced to shift to the three-phase quasi-full-wave drive state. Further, a forward / reverse switching signal for the rotation direction of the motor is applied to the REV terminal. When the REV terminal is at a low potential, the motor rotates in the forward direction, and when it is at a high potential, the motor rotates in the reverse direction. When the J terminal is at a low potential, energization to the stator winding is stopped, and when it is at a high potential, energization to the stator winding is performed.

Although the present invention does not refer to the rotation servo system of the motor, it is assumed here that the error voltage is fed back to the error signal amplifier 1300 via the E terminal based on the speed information obtained from the F terminal.

Before explaining the outline of the operation of each part, the operation of switching the energization state to the stator winding of the DC non-commutator motor shown in FIGS. 1 and 2 will be described.

As is clear from FIGS. 1 and 2, in the DC non-commutator motor described as the embodiment of the present invention, the stationary position of the rotor is detected by an annular ring having three kinds of constituent elements. Since the identification band 5 and the only Hall IC 6 are provided, only three identifications can be made according to the stationary position of the rotor. However, as is well known, 3
In order to adopt the form of phase full-wave drive, six types of position detection information are required according to the stationary position of the rotor.

In the DC non-commutator motor shown in FIG. 1, all three-phase stator windings 1, 2 and 3 are supplied with current based on the output signal of the Hall IC 6 until the rotation speed of the motor increases to some extent. By supplying the extra current, the start torque is prevented from lowering, the rotation speed of the motor is increased, and the power generation winding 7
After a sufficient signal is obtained from the output signal of the power generation winding 7 and the output signal of the Hall IC 6, an energization switching signal for three-phase full-wave driving is distributed to the distributor 100 and the sequential circuit 20.
0, step controller 500, synchronous trigger circuit 600,
Mode switching circuit 700, addition / subtraction command circuit 800, quasi full-wave phase switching circuit 900, conduction direction switching circuit 1100, step current generation circuit 1200, slope generation circuit 1400, slope synthesis circuit 15
It is configured to be created inside the drive signal generating means configured by 00. The principle of switching the driving mode will be described with reference to FIG.

FIG. 3A shows each stator winding 1 when the main magnetic pole of the permanent magnet 4 is magnetized with a sine wave in the motor structure shown in FIG.
Fig. 2 shows the torque characteristics that occur when a current is passed through 2 and 3, and in Fig. 2, the stator windings 1 to 3 and the hall I are shown.
The rotation torque is positive when the stator side including C6 and the power generation winding 7 moves to the right. Characteristic curve u in FIG. 3A
a represents the torque generated when a current is applied to the stator winding 1 in FIG. 2 from the U terminal to the X terminal, and the characteristic curve ub is the characteristic of the stator winding 1 from the X terminal to the U terminal. It represents the torque generated when a current is applied to. Also,
The characteristic curve va represents the torque generated when a current is applied to the stator winding 2 in the direction from the V terminal to the X terminal, and the characteristic curve vb is the current generated in the stator winding 2 in the direction from the X terminal to the V terminal. Represents the torque generated when the current flows. Further, the characteristic curve wa represents the torque generated when a current is applied to the stator winding 3 in the direction from the W terminal to the X terminal,
The characteristic curve wb represents the torque generated when a current is applied to the stator winding 3 in the direction from the X terminal to the W terminal.

On the other hand, FIG. 3C shows the torque generated in the positive direction when current is applied to any two phases of the three-phase stator windings star-connected.
As shown by the torque ratio generated in each stator winding shown in FIG. A, as is well known, the envelope of these curves in a three-phase full-wave drive motor is the actual output torque waveform. Become. That is, in FIG. 3C, the characteristic curve w
v is the torque generated when electricity is applied from the W terminal to the V terminal direction in FIG. 2, the characteristic curve uv is the torque generated when electricity is applied from the U terminal to the V terminal direction, and the characteristic curve uw is the U terminal to the W terminal direction. Is generated when the current is applied to the V terminal, the characteristic curve vw is the torque generated when the current is applied from the V terminal to the W terminal direction, and the characteristic curve vu is the torque generated when the current is applied from the V terminal to the U terminal direction, the characteristic curve wu. Represents the torque generated when electricity is applied from the W terminal to the U terminal.

If the maximum torque generated by each stator winding is 1, the energization switching to each stator winding is performed at every 60 ° electrical angle in three-phase full-wave drive. T _ma1, the minimum torque T _mi1, average torque T _av1 is given by the following equation. It should be noted that, here, all torques are made unitless and are simply expressed as indices.

FIG. 3D shows the output signal waveform of the Hall IC 6 which has already been described. In the state where the rotor of the mote is stopped, the Hall IC is used as the position detection information.
Only 6 output signals can be used. In order to start the motor using only three types of position detection information, it is conceivable to take the form of three-phase half-wave drive. In that case, in the case of the star-connected stator winding in Fig. 1, A power switching element is required to directly connect the X terminal, which is a point, to the positive or negative power supply line.

In the embodiment of the present invention, such inconvenience is solved by the method described below. That is, the Hall IC 6
Corresponding to the three-level level change of the output signal, the section in which the output signal is at a high potential is the first energization section, the section at which the output signal is in a low potential is the second energization section, and the section at the intermediate potential is the third section.
In the first energizing section, energization from the U terminal to the V terminal and the W terminal in FIG. 2 is performed, and in the second energizing section, energization from the V terminal to the W terminal and the U terminal. Then, in the third energization section, the W terminal is energized to the U terminal and the V terminal. At this time,
The combined torque characteristics of the three-phase stator windings 1, 2 and 3 are as shown in FIG. 3B, the characteristic curve uc is the torque generated by energization in the first section, and the characteristic curve vc is the second curve.
The torque generated by energization in the section and the characteristic curve wc represent the torque generated by energization in the third section.

Therefore, the output torque of the motor when the energization is switched at the ideal timing is equal to the envelope of the characteristic curve in FIG. 3B, and the main winding of the three-phase stator winding has the other winding. Considering that a current equal to the sum of the currents of the two-phase stator windings flows, maximum torque T _ma2 and minimum torque T _ma2
mi2, when obtaining the average torque T _av2 is as follows.

Now, as is clear by comparing the third and sixth equations, it is possible to obtain the same average torque as at the time of three-phase full-wave drive even at the time of start-up, and by adding an extra power switching element, It is also possible to save the starting current as compared with the case where the half-wave driving is performed. By the way, if the resistance value per one phase of each stator winding is the same in any of the driving methods, the starting current in the three-phase half-wave drive becomes twice as large as that in the three-phase full-wave drive. The drive method just described increases the start-up current by almost 33 percent.

In the following description, this driving method is called three-phase quasi-full-wave driving and is distinguished from three-phase full-wave driving or three-phase half-wave driving.

Next, a concrete configuration example of the main part shown in the embodiment of FIG. 1 and an outline of its operation will be described to help explain the overall operation.

First, FIG. 4 is a circuit connection diagram showing a specific configuration example of the Hall IC 6, which is formed on a silicon substrate with a constant voltage circuit section 61 using a well-known bandgap reference voltage source or the like. The Hall power generator 62 and other signal processing circuit parts.

When the Hall power generator 62 of FIG. 4 faces the N-polarized portion of the identification band 5 shown in FIG. 2, the potential of one output terminal 62a of the Hall power generator 62 rises, The potential of the other output terminal 62b drops. Therefore, the collector potential of the transistor 63 decreases and the collector potential of the transistor 64 increases, so that most of the current flowing into the constant current transistor 65 becomes the collector current of the transistor 66.

In the circuit of FIG. 4, the constant current transistor
The resistance ratio of the resistor 67 connected to the emitter side of 65 and the resistor 69 connected to the emitter side of the constant current transistor 68 is 3
Since it is set to pair 4, the constant current transistor 65
Assuming that the collector current of the constant current transistor 68 is 4 · I ₀ , the collector current of the constant current transistor 68 is about 3 · I ₀ . Also,
The resistor 71 connected to the emitter side of the power receiving transistor 70 and the resistors 74 and 75 connected to the emitter sides of the constant current transistors 72 and 73 that configure the positive side current mirror circuit are set to have the same resistance value. Since the resistance value of the resistor 77 connected to the emitter side of the constant current transistor 76 is set to three times the resistance value of the resistor 71, the collector currents of the constant current transistors 72 and 73 are both maximum values. It becomes approximately 3 · I ₀ , and the collector current of the constant current transistor 76 becomes approximately I ₀ .

Therefore, three quarters of the collector current of the transistor 66 is supplied from the constant current transistor 73, and only the remaining one quarter is supplied from the first collector 78a of the transistor 78. At this time, the load resistor 79 connected to the output terminal 6c is supplied with a current of I ₀ from the second collector 78b of the transistor 78 and is also supplied with a current of I ₀ from the constant current transistor 76. , The resistance 79
When the resistance value of R is ₀ , the output terminal 6c is
A potential of I ₀ · R ₀ appears.

On the contrary, when the Hall power generator 62 faces the magnetized portion of the identification band 5 at the S pole, most of the current flowing into the constant current transistor 65 becomes the collector current of the transistor 80, and the first current of the transistor 81. A current I ₀ also flows through the first collector 81a and the second collector 81b, and the current of the second collector 81b is supplied to the current mirror circuit formed by the transistor 82 and the transistor 83. Therefore, at this time, most or all of the collector current of the constant current transistor 76 flows into the collector of the transistor 83, and the potential of the output terminal 6c becomes zero.

On the other hand, when the Hall power generator 62 faces the non-magnetized portion of the identification band 5, the collector currents of the transistors 66 and 80 are substantially balanced, and thus the transistors 66 and 80.
All of the collector current of the constant current transistor 72,
The collector currents of the transistors 78 and 81 supplied from 73 become zero, and only the collector current of the constant current transistor 76 is supplied to the load resistor 79 to supply the output terminal 6
The potential of c becomes I ₀ · R ₀ .

In this way, the output voltage of the Hall IC 6 changes in three steps depending on the position of the Hall power generator 62 facing the identification band 5.

FIG. 5 shows the relative positional relationship between the main magnetic pole and the discrimination band of the DC non-commutator motor constructed as shown in FIGS. 1 and 2 and the change in the position detection signal obtained from the Hall IC 6. When the relative rotation angle of the identification band 5 provided on the rotor and the Hall IC 6 arranged on the stator is changed as shown by the mechanical angle or the electrical angle in FIG. Correspondingly, the output voltage of the Hall IC 6 changes as shown in FIG. 5A.

Next, FIG. 6 shows a concrete example of the configuration of the distributor 100 shown in FIG. 1, in which two types of comparators 110 and 120 having different threshold voltages and an output processing unit 130 are used. The main part is configured and the output terminal s
The potentials of 1, n1 and z1 exclusively shift to high potentials in accordance with the three-stage potentials of the input terminal P. In the circuit of FIG. 6, transistors 111 and 112 or transistor 12
1 and 122 are the comparators 110 or 120, respectively.
Has been added to add the Schmidt function to.

FIG. 7 shows the sequential circuit 200, the rotation direction determination circuit 300, the step controller 500, and the synchronous trigger circuit shown in FIG.
Although a specific configuration example of 600, the mode switching circuit 700, the addition / subtraction command circuit 800, the energization direction setting circuit 1000, and the initialization circuit 2000 is shown, the operation of the initialization circuit 2000 will be described first.

In the following description of the operation of the logic circuit, all positive logic is used, and it is assumed that each input / output terminal or each signal line is in an active state when it is at a high potential, and the state of a high potential is expressed by "1". However, the low potential state is represented by "0".

As can be seen from FIG. 7, the initialization circuit 2000 is composed of an RS flip-flop with two NAND gates whose input / output terminals are cross-coupled, a 4-input NAND gate 2001 and a 2-input NAND gate 2002. However, if one of the input terminals of the NAND gate 2001 is set to "0" before the level of the J terminal changes from "0" to "1", the level of the J terminal becomes "1". Immediately after shifting to '
The output level of 2002 shifts to "0" and the initialization signal is output. This initialization signal is used for initialization setting of the step controller 500 and the mode switching circuit 700, and is also used for initialization setting of the sequential circuit 200 and the rotation direction determination circuit 300 via the mode switching circuit 700.

Next, the outline of the operation of the sequential circuit 200 will be described based on the output signal waveform of the position detection signal shown in FIG. 7th
The sequential circuit shown in the figure has two NAND gates whose input / output terminals are cross-coupled.
Two NAND gates in which the gate pair and the input / output terminals are cross-coupled by 1 and 202
The main part is composed of a gate pair of 203 and 204 and two NAND gates 205 and 206 connecting these gate pairs.

The signal waveform of FIG. 5A shows the output signal of the Hall IC 6 of FIG. 1 as already described, and FIG.
Based on the output signal of the Hall IC 6, the signal waveforms of C and D are output by the distributor 100 shown in FIG.
1 and z1 (these terminals serve as input terminals in FIG. 7), which are the signal waveforms appearing in the respective signal lines after being distributed, and the signal waveforms in FIGS.
These are the output signal waveforms of the AND gates 203 and 201 and the inverter 207.

When the level of the J terminal is "0", or J
Immediately after the terminal level shifts from "0" to "1", the output levels of the NAND gates 202 and 204 are forced to shift to "1" by the AND gate 704 forming the mode switching circuit 700. Therefore, immediately after starting the motor, the output level of the NAND gate 203,
The output level of the NAND gate 201 and the output level of the inverter 207 are respectively n1 terminal, s1 terminal,
It is the same level as the z1 terminal.

Assuming now that the Hall IC 6 in FIG. 1 has an electrical angle of 0 in FIG.
If it is opposed to the position of °, the inverter
The output level of 207 becomes "1", and the NAND gate
The output levels of 201 and 203 are both "0", but when the rotor of the motor starts rotating and the Hall IC 6 faces the magnetized portion of the identification band 5 at the N pole, the level of the z1 terminal becomes "0". The level of the n1 terminal shifts to "1" instead. However, here, the level of the REV terminal is held at "0", the rotor of the motor rotates in the forward direction, and the output level of the D flip-flop 301 constituting the rotation direction determination circuit 300 becomes "0". Be present.

Since the output level of the NAND gate 202 is "1" before the level of the n1 terminal shifts to "1", the output level of the NAND gate 205 subsequently shifts to "0",
By inverting the output state of the gate pair of the NAND gate 203 and the NAND gate 204, the output level of the NAND gate 203 becomes "1" and the output level of the NAND gate 204 becomes "0". Due to this change, the NA
The output level of the ND gate 206 shifts to "1", and the output level of the inverter 207 shifts to "0".

When the rotor further rotates and the Hall IC 6 approaches the position of electrical angle 180 ° in FIG. 5, the level of the z1 terminal shifts to “1” again as shown in FIG. 5D. At this time, since the output level of the NAND gate 204 has shifted to “0”, the output level of the NAND gate 206 does not change, and the NAND gates 203, 201,
The output state of the inverter 207 does not change either.

Then, when the level of the s1 terminal becomes "1", the output level of the NAND gate 206 has become "1" before that, so the NAND gate 201 and the NAND gate 202
The output state of the gate pair is inverted, the output level of the NAND gate 201 shifts to "1", and the output level of the NAND gate 203 shifts to "0".

After all, the sequential circuit shown in FIG. 7 can be operated only when the input terminals are activated as previously ordered.
It has a function to reflect input to output.

Thus, when the position detection signals as shown in FIGS. 5B, 5C and 5D are supplied to the n1, s1 and z1 terminals of FIG. 7, the NAND gate 203 or the n2 terminal,
A drive command signal as shown in FIGS. 5E, 5F and 5G is output to the NAND gate 201, the inverter 207 or the z2 terminal.

As can be seen from FIG. 5, when the motor is rotating in the reverse direction, the arrival order of the signals supplied to the n1 terminal, s1 terminal, and z1 terminal is n1, z1, and s1. The signal of is changed. The switching circuit constituted by the NAND gates 208, 209, 210, 211, 212 of FIG. 7 is added to the sequential circuit 200 to operate under the same conditions regardless of whether the rotation direction of the motor is normal or reverse.

Next, the rotation direction determination circuit 300 shown in FIG. 7 has the n1 terminal, the s1 terminal, and the z1 terminal when the rotor of the motor is rotating in the forward direction and in the reverse direction. The rotation direction is discriminated by utilizing the difference in the order of transition to the active state. The outline of this operation is shown in FIGS. 8 and 9.
Description will be given based on the signal waveform diagram shown in the figure.

First, the D flip-flop 301 is the AND described above.
While the output level of the gate 704 is "0", the output level is initialized to the same level as the REV terminal.

FIGS. 8A, 8B, 8C and 8D show the f1 terminal, n1 terminal, s1 terminal and z when the motor is rotating in the forward direction, respectively.
8 shows a signal waveform supplied to one terminal.
FIG. E shows an output signal waveform of the NAND gate 302 at this time, and FIGS. 8F, G, H, I, J, and K respectively show NAN.
The output signal waveforms of the D gates 303, 304, 305, 306, 307, and 308 are shown, and L and M of FIG. 8 are the output signal waveforms of the D flip-flop 301 and the NAND gate 309, respectively.

In FIG. 8, the NAND gate 302 and the NA are set during the period in which the level of the s1 terminal is “1” before the time t ₁ .
Since the RS flip-flop by the ND gate 310 is reset, the RS flip-flops by the NAND gate 303 and the NAND gate 304 are set, and the RS flip-flop by the NAND gate 306 and the NAND gate 307 is reset before that, s1 After the trailing edge of the signal supplied to the terminal arrives,
At time t ₁ , when the leading edge of the FG signal supplied to the f1 terminal arrives, the NAND gate
The output level of 305 shifts to "0", and as a result, the N
RS by AND gate 306 and the NAND gate 307
The output state of the flip-flop is inverted and the NAND
The output level of the gate 306 shifts to "1".

At the time t ₂ , when the trailing edge of the FG signal arrives, the output level of the NAND gate 308 shifts to “0”, so that the output state of the RS flip-flop by the NAND gate 303 and the NAND gate 304 is inverted. Then, the output state of the RS flip-flop by the NAND gate 306 and the NAND gate 307 is also inverted, and the output level of the NAND gate 308 returns to "1" again. At time t ₂ , the D flip-flop 301 is triggered by the transition of the output level of the NAND gate 307 to “1”, and the NAN at the time of the trigger is triggered.
Since the output level of D-gate 302 is "0",
The output level of the D flip-flop 301 also becomes "0".

From time t ₃ period from time t ₄ or time t ₅ to time t ₆ repeats the same operation, as long as the motor rotor is rotated in the forward direction, the output level of the D flip-flop 301 is '0' If a command signal for forward rotation is given via the REV terminal at this time,
Since the output level of NAND gate 311 becomes "0",
The output level of the NAND gate 309 becomes "1".

On the other hand, when the rotor of the motor is rotating in the opposite direction, the signal waveform of each part of the rotation direction discrimination circuit 300 in FIG. 7 becomes as shown in FIG. 9, and the D flip-flop 301 triggers at time t ₂ . The NAND gate immediately before
Since the output level of 302 is always "1", the output level of the D flip-flop 301 is also always "1", and R
If a command signal for forward rotation is given to the EV terminal, the output level of the NAND gate 309 is "0".
Then, an output signal indicating that the rotation is in the opposite direction to the command is sent to the en terminal.

Since the output signal of the D flip-flop 301 is directly applied to the dr terminal, the level of this terminal becomes '0' when the motor rotor is rotating in the forward direction, and the motor rotor is in the reverse direction. It becomes '1' when rotating in the direction.

Next, the outline of the operation of the step controller 500 shown in FIG. 7 will be described based on the signal waveform diagram shown in FIG.

10A and 10B show the output signal of the NAND gate 201 and the signal waveform of the FG signal supplied to the f1 terminal, respectively, and C, D, E, F, and G of FIG. 10 are N respectively.
4 shows output signal waveforms of AND gates 501, 502, 503, 504, 505. Furthermore, FIG. 10 H, I, J,
K, L, and M are inverters 506 and T flip-flops 507 and 50, respectively, which form a 3-bit down counter.
8 and 509 and the output signal waveforms of NAND gates 510 and 511 are shown in FIG.
The output signal waveforms of the D gates 512 and 513 are shown, and a, b, c, d, e, and f in FIG. 10 are um0 terminal, um1 terminal, um2 terminal, and um3 terminal in FIG. 7, respectively.
The output signals appearing at the um4 terminal and the um5 terminal are shown in FIG. 10, and g, h, i, and j in FIG.
The output signals appearing at the s1 terminal, the us2 terminal, the us3 terminal, and the us4 terminal are shown in FIG. 10, k, l, m,
n, o, and p represent output signals appearing at the wm0 terminal, wm1 terminal, wm2 terminal, wm3 terminal, wm4 terminal, and wm5 terminal of FIG. 7, respectively, and q, r, and FIG.
s and t are the ws1 terminal, ws2 terminal, and ws2 terminal of FIG. 7, respectively.
The output signals appearing at the ws3 terminal and the ws4 terminal are shown.

NAND gates 514, 515 and 51 before time t _{1 in} FIG.
The output level of 6 is "1", and the NAND gate 517
Output level is '0' and the above NAN
When the leading edge of the FG signal supplied to the f1 terminal arrives at time t _{1 while} the leading edge of the output signal of the D gate 201 has already arrived, N
The output level of the AND gate 501 shifts to "0", as a result, the output level of the NAND gate 502 shifts to "1" and the output level of the NAND gate 515 shifts to "0", and this state is maintained. To be done.

In time t _2, the the trailing edge of the FG signal arrives, the output level of the NAND gate 501 returns to "1", the output level of the NAND gate 503 transitions to "0", the output of NAND gate 504 When the level shifts to "1", the NAND gate 516
Output level shifts to "0".

At time t ₃ , when the leading edge of the FG signal arrives again, the output level of the NAND gate 505 becomes “0”.
, And as a result, the output level of the NAND gate 517 shifts to '1', the NAND gate 514
Output level of the NAND gate 5 shifts to "0".
The output level of 15 shifts to '1'. As a result, the output level of the NAND gate 502 becomes "0", the output level of the NAND gate 516 becomes "1", and then the output level of the NAND gate 504 becomes "0". The output level of the gate 505 returns to "1" and the series of operations ends.

After all, when the output signal of the NAND gate 201 and the FG signal supplied to the f1 terminal change from time t ₀ to time t ₃ as shown in FIGS. 10A and 10B, time t ₂ to time t ₃ During this period, the output level of the NAND gate 516 becomes "0" and the T flip-flop 507 is reset, and at the same time, the T flip-flops 508 and 509 are set via the AND gate 518, and the NAND gate 516 is set.
The output state of the RS flip-flop formed by 510 and the NAND gate 519 is also inverted, and the output level of the NAND gate 510 shifts to "1".

That is, the output signal of the NAND gate 504 is the T signal.
It becomes a preset signal of a 4-bit down counter constituted by the flip-flops 507, 508, 509 and the RS flip-flop, and the output of this counter is preset at [1110] at time t ₂ , and this preset is performed at time t ₃ Lasts until.

When the trailing edge of the FG signal at time t ₄ is reached, although the 4-bit counter starts counting down again, at time t _14, the count value of the counter becomes [1000], the output level of the NAND gate 520 It becomes "0", then NAND gate 511 and NAN
The output state of the RS flip-flop formed by the D gate 521 is inverted and the output level of the NAND gate 511 shifts to "0". As a result, the output state of the RS flip-flop by the NAND gate 510 and the NAND gate 519 is also inverted, the output level of the NAND gate 510 shifts to "0", and the T flip-flop is passed through the AND gate 518. 508 and the T
Flip-flop 509 is set.

Therefore, the output of the 4-bit counter is preset to [0110] at time t ₁₄ , and when the leading edge of the FG signal again arrives at time t ₁₅ , the N
Since the output level of the AND gate 511 returns to "1", the T flip-flop 508 and the T flip-flop 509
Is released and the 4-bit counter restarts the down-counting operation from time t ₁₆ .

Thereafter, the NAND gate 516 is followed by a down-counting operation until generation of a preset signal again at time t _26, at time t _26, when the leading edge of the FG signal arrives, the same operation as at time t ₂ is repeated Be done.

In this way, the count value of the 4-bit counter is expressed in decimal notation during one cycle of the position detection signal, and is 14, 13, 12, 1.
Although it decreases in order of 1, 10, 9, 6, 5, 4, 3, 2, 1, but if the FG signal that is the clock signal of this counter is regarded as the LSB output of the virtual counter, the number of bits of the counter Is 5, and the count value is 1 of the position detection signal.
In decimal notation during the cycle, 29, 28, 27, 26, 25, 24, 23,
22, 21, 20, 19, 18, 13, 12, 11, 10, 9, 8, 7,
It decreases in the order of 6, 5, 4, 3, 2.

On the other hand, NAND gates 522, 523, 524, 525, 526,
527, 528, 529, and 530 form a decoder that decodes the output of the lower 4 bits of the 5-bit virtual counter. The output level of the NAND gate 522 becomes “0” when the output of the lower 4 bits of the counter becomes [1100], and the NAND gate 523 outputs the output of the lower 4 bits of the counter as [1011] or [1010]. ], The output level becomes '0', and the NAND gate 524 becomes '0' when the lower 4 bits of the counter output becomes [1010].
The ND gate 525 outputs the lower 4 bits of the counter [10
When it becomes 01] or [1000], its output level becomes "0", and when the output of the lower 4 bits of the counter of the NAND gate 526 becomes [1000], its output level becomes "0". The output level of the NAND gate 527 becomes "0" when the output of the lower 4 bits of the counter becomes [0110], and the NAND gate 528 outputs the output of the lower 4 bits of the counter to [0100]. Output level becomes "0" when it becomes
For the 529, the output of the lower bit of the counter is [0011] to [00
01], its output level becomes '0', and the NAN
In the D gate 530, the output of the lower 4 bits of the counter is [001
The output level becomes "0" when it becomes "0".

These decoders are used not only for the purpose of generating a section signal for generating a step current waveform, but also for generating the signal waveform of FIG. 10N and the signal waveform of FIG.

That is, since the output of the 5-bit virtual counter becomes [11100] at time t ₃ , the output level of the NAND gate 522 shifts to “0”.
The output level of D gate 531 shifts to "0", and then N
The output level of the AND gate 532 shifts to "1", and as a result, the output level of the NAND gate 513 shifts to "0". At time t ₁₅ , the output of the 5-bit virtual counter becomes [01100], so that the output level of the NAND gate 522 shifts to “0”.
The output level of 533 shifts to '0', and then the NA
The output level of the ND gate 513 shifts to "1", and as a result, the output level of the NAND gate 532 shifts to "0".

Further, at time t ₁₁ , the output of the 5-bit virtual counter becomes [10100], so that the output level of the NAND gate 528 shifts to “0”.
The output level of the gate 534 shifts to "0", then N
The output level of the AND gate 535 shifts to "1", and as a result, the output level of the NAND gate 512 shifts to "0". At time t ₂₃ , the output of the 5-bit virtual counter becomes [00100], so that the output level of the NAND gate 528 shifts to “0”.
The output level of 536 shifts to "0", and then the NA
The output level of the ND gate 512 shifts to "1", and as a result, the output level of the NAND gate 535 shifts to "0".

In addition, the output terminals um0-um5, us1-us of FIG.
4, wm0 to wm5, ws1 to ws4 are shown in FIGS.
The section signals shown in are output, and a method of generating these section signals will be described.

First, the um0 terminal and the wm0 terminal have the NAND gates.
The same signal waveforms as the output signals of 528 and 522 are transmitted, and these are used as they are as signals for the minimum value section of the step current waveform. Also, inverted signals of the output signals of the NAND gates 524 and 527 are sent to the um5 terminal and the wm5 terminal, and these are used as signals for the maximum value section of the step current waveform. Other section signals are NAND gates 537, 538, NAND gates 539, 54
0, NAND gate 541, 542, NAND gate 543,
5 composed of 544, NAND gates 545, 546
It is generated by combining the output signals of the RS flip-flops and the output signals of the T flip-flops 507 to 509. For example, for the section signal um4, the NAND gate 5
The output signal of the T flip-flop 509 is used for the section signal us3, and the section signal w
The output signal of the NAND gate 541 is used for m2, and the output signal of the NAND gate 539 is used for the interval signal ws3.

Next, the operation of the mode switching circuit 700 shown in FIG. 7 will be described.

The mode switching circuit 700 includes a D flip-flop 701 and a NAN.
D gate 702, inverter 703, AND gate 704, 7
05, NAND gate 706.

If the output level of the D flip-flop 701 is "0" while the level of the J terminal is "0", the initialization circuit 000 is formed immediately after the level of the J terminal shifts to "1". Since the output level of the NAND gate 2002 shifts to "0", the D flip-flop is activated when the motor is started.
The output level of 701 is '1'.

As the motor rotation speed increases, the FG signal is supplied to the f1 terminal, which causes the step controller 500 to start normal operation and the NAND gate 516 to preset the counter correctly. Then, at the midpoint between time t ₀ and time t _{1 in} FIG. 10, when the leading edge of the output signal of the NAND gate 201 which forms the sequential circuit 200 arrives, the output of the NAND gate 529 which forms the step controller 500 When the level shifts to "0", the output level of the D flip-flop 701 shifts to "0".

The output signal of the D flip-flop 701 is sent to the md terminal as a mode switching signal, and the synchronous trigger circuit 6
00, addition / subtraction command circuit 800, and energization direction setting circuit 1000 are also supplied. When the level of the md terminal is "0", it is in the quasi-full-wave drive mode, and when it is "1", it is in the full-wave drive mode.

The output signal of the NAND gate 702 is sent to the bk terminal. The output level of the NAND gate 702 is "0" at the J terminal and the output level of the D flip-flop 701 is "1". When it becomes '0'
This output is used for the purpose of causing the U-phase drive circuit 1600, the W-phase drive circuit 1700, and the V-phase drive circuit 1900 to perform only one direction for supplying power to the Hall IC 6 via the energization direction switching circuit 1100. .

The AND gate 704 outputs the initialization signal from the initialization circuit 2000, or outputs the output signal from the NAND gate 702.
AND gate 705 is used when the initialization circuit 2000 sends an initialization signal or when the rotation stop detector 21
When 00 changes the level of the qt terminal to "1", the D flip-flop 701 and the step controller 500
To initialize.

Next, the operation of the addition / subtraction command circuit 800 will be described with reference to the signal waveforms in FIG.

FIG. 11 is a signal waveform diagram showing a step current waveform during full-wave driving and a process of generating a three-phase drive current waveform generated based on this step current waveform.
The signal waveform of B is the same as the signal waveform of FIGS. 10A and 10B, respectively, and the signal waveforms of FIGS. 11C, D, E, and F are shown in FIGS. 10H, I, J, and K, respectively. The signal waveforms are the same as those described above, and these are shown for timing reference of other signal waveforms. Further, the symbols shown above the signal waveforms in FIG. 11C are hexadecimal representations of the lower 4 bits of the 5-bit virtual counter already described. Further, FIGS. 11G and 11H are output signal waveforms of the NAND gate 543 and NAND gate 545 of FIG. 7, and FIG. 11I is an output signal waveform of the slope generation circuit 1400 of FIG. J, K, N, and O are output signal waveforms of the step current generation circuit 1200 of FIG.
11 L and P are signal waveforms created inside the slope synthesizing circuit 1500 of FIG. 1, and M and Q of FIG. 11 are the U-phase driving circuit 1600 and W-phase driving circuit 1700 of FIG. 1, respectively. 11 is a drive current waveform to be supplied. R and S in FIG. 11 are output signal waveforms of the energization direction setting circuit 1000 supplied to the u1 terminal and w1 terminal in FIG. 7, respectively. Is also a V-phase drive current waveform produced by the current adder circuit 1800 of FIG.

The current waveform of FIG. 11M is the step current generation circuit of FIG.
The current waveform of FIG. 11J generated from 1200 is combined with the current waveform of FIG. 11I generated from the slope generation circuit 1400 of FIG. 1 by the slope combination circuit 1500 of FIG. At that time, in the section from time t ₁₁ to time t ₁₇ , the current value of FIG. 11L limited by the current value of FIG. 11K is added to the current value of FIG. 11J, and from time t ₁₇ to time t _In section ₂₃ , the current waveform of FIG. 11M is created by subtracting the current value of FIG. 11L limited by the current value of FIG. 11K from the current value of FIG. 11J.

The addition / subtraction command circuit 800 has a function of sending these addition / subtraction command signals to the slope synthesis circuit 1500.
11 interval signal from the time t ₁₁ to produce a drive current waveform of the U-phase shown in FIG M to time t _17, there is a time t ₁₇
According to NAND gate 543, 544 constituting the step controller 500 as interval signal until time t ₂₃ from R
Is used the output signal of the S flip-flop, 11th section of the interval signal from time t ₃ to produce a driving current waveform of the W-phase shown in FIG Q to time t ₉ or from the time t _9, until time t ₁₅ Step controller as signal 500
The output signals of the RS flip-flops by the NAND gates 545 and 546 which compose the above are used. These section signals are sent to the ua terminal or the wa terminal via the NAND gate 801 or the NAND gate 802 when the level of the md terminal is "1", but the level of the md terminal is "0". 'When the us terminal has a sequential circuit
The output signal of the NAND gate 201 which constitutes 200 is sent, and the same output signal as the signal sent to the n2 terminal is sent to the wa terminal.

Next, the energization direction setting circuit 1000 outputs the signals of FIGS. 11R and 11S to the u1 terminal, w when the level of the md terminal is “1”, that is, when the full-wave driving state is set.
It is sent to the energization direction switching circuit 1100 of FIG. 1 via the 1 terminal, while when the level of the md terminal is '0', a signal whose level is irrelevant to the rotational position of the rotor of the motor is u1. Send to the terminal, w1 terminal. Also, the phases of the signals sent to the u1 terminal and the w1 terminal are inverted as shown in Table 1 according to the levels of the J terminal, dr terminal, en terminal and dn terminal.

First, NAND gates 1001, 1002, 1003, 1004, 1005,
The switching circuit constituted by 1006 is a NAND circuit which constitutes the step controller 500 when the motor is rotating in the forward direction and the level of the dr terminal is "0".
The output signal of the gate 512 is sent to the u1 terminal, and the output signal of the NAND gate 513 is sent to the w1 terminal. When the motor is rotating in the reverse direction and the level of the dr terminal is "1", the NAND signal is output. Output signal of gate 512 w
The output signal of the NAND gate 513 is sent to the u1 terminal. This corresponds to the switching operation of the s1 signal and the n1 signal according to the forward and reverse of the rotation direction of the motor in the sequential circuit 200. By replacing the position detection signals in the sequential circuit 200, the leading edge of the signal waveform in FIG. 11A is always magnetized to the N pole of the identification band 5 in FIG. 2 regardless of whether the motor is rotating in the normal or reverse direction. Indicates the boundary position between the magnetized part and the part magnetized to the S pole,
For example, even if the width of the non-magnetized portion of the identification band 5 is not uniform due to variations in magnetization, etc., after shifting to three-phase full-wave driving, each phase of U, V, and W in FIG. A drive signal having a uniform width is distributed to
Even when switching the rotation direction, the timing of starting energization does not deviate.

When the level of the md terminal is "0", the output level of the NAND gates 1003 and 1006 is the NA.
It shifts to "1" regardless of the outputs of ND gates 512 and 513.

The output signals of the NAND gates 1003 and 1006 are inverters.
1007, NAND gates 1008 and 1009, a first exclusive OR circuit composed of an AND gate 1010, an inverter 1011, NAND gates 1012 and 1013, and an AND gate 1014.
Via the second exclusive OR circuit constituted by
The NAND gate 1015 transmits the input signal as it is when the output level of the NAND gate 1015 is "0".
When the output level of 1015 is "1", the input signal is phase-inverted and transmitted.

Table 1 shows the input conditions under which the output level ex of the NAND gate 1015 becomes "1". Note that dn
As will be described later, an acceleration / deceleration command signal from the error signal amplifier 1300 of FIG. 1 is supplied to the terminal, and when the deceleration command is supplied, the level thereof shifts to "1".

In Table 1 a), the level of the J terminal is "1", the motor rotates in the forward direction, the deceleration command is sent from the error signal amplifier 1300, and the level of the dn terminal shifts to "1". When this is done, the output level of the NAND gate 1015 shifts to "1" in order to decelerate the motor. Also, in Table 1 b), the output level of the NAND gate 1015 also changes when the rotation direction mismatch signal is sent and the level of the en terminal shifts to "0" while the motor is rotating in the forward direction. If the acceleration command is sent from the error signal amplifier 1300 while the motor is rotating in the reverse direction in Table 1), the output level of the NAND gate 1015 becomes “1”. After shifting to 1 ', the energization direction setting circuit 1000 operates so as to rotate the motor in the reverse direction or to keep the rotation in the reverse direction. Further, in Table 1 d), the output level of the NAND gate 1015 shifts to "1" even when the level of the J terminal is "0" and the motor is rotating in the forward direction. Outside during positive rotation of the motor This is a function added for the purpose of temporarily generating a reverse torque in the motor to quickly stop the motor when a rotation stop command signal is supplied from the unit.

Next, the synchronous trigger circuit 600 of FIG. 7 sends a trigger signal for generating a sawtooth wave to the slope generation circuit 1400 of FIG. 1 via the x2 terminal. When the level of is 1
It is synchronized with the leading edge and trailing edge of the FG signal supplied to one terminal, and the leading edge of the three types of position detection signals supplied from the sequential circuit 200 when the level of the md terminal is "0". Is in sync with.

First, when the level of the md terminal is “1” and the level of the x1 terminal to which the return signal from the slope generation circuit 1400 is supplied is “0”, when the trailing edge of the FG signal arrives, NAND The output level of the gate 601 shifts to "0" and shifts the level of the x2 terminal to "1", but when the return signal is sent from the slope generation circuit 1400 and the level of the x1 terminal shifts to "1", the NAND gate Since the output state of the RS flip-flop by 602 and NAND gate 603 is inverted and the output level of the NAND gate 603 shifts to "0", the NAND gate 6
The output level of 01 also returns to '1'. Further, when the leading edge of the FG signal arrives, the output level of the NAND gate 604 shifts to "0" and shifts the level of the x2 terminal to "1", but when the level of the x1 terminal shifts to "1", the NAND gate RS by 605 and NAND gate 606
Since the output state of the flip-flop is inverted and the output level of the NAND gate 606 shifts to "0", the N
The output level of the AND gate 604 also returns to "1".

On the other hand, when the level of the md terminal is "0", the NAND
The FG signal and the output signal of the NAND gate 201 forming the sequential circuit 200 are switched by the switching circuit of the gates 607, 608, 609, and the NA is generated at the leading edge and the trailing edge of the NAND gate 201.
The output levels of the ND gate 601 and the NAND gate 604 respectively shift to "0" and the level of the x2 terminal becomes "1".
NA that makes up the sequential circuit 200
At the leading edge of the output signal of the ND gate 206, that is, the trailing edge of the position detection signal sent to the z2 terminal, the output level of the NAND gate 610 shifts to "1", and the return signal is sent from the slope generation circuit 1400. When the level of the x1 terminal shifts to "1", the NAND gate 602 and the NAND gate 603 make R
The output state of the RS flip-flop by the S flip-flop or the NAND gate 605 and the NAND gate 606 or the RS flip-flop by the NAND gate 611 and the NAND gate 612 is inverted and the NAN is output.
The output level of the D gate 601, the NAND gate 604, or the NAND gate 610 also returns to "1".

Next, FIG. 12 is a circuit connection diagram showing a specific configuration example of the error signal amplifier 1300. An error voltage for controlling the rotation speed of the motor is supplied to the E terminal, and the same value is used for the resistance voltage. Value V obtained by resistance 1301 and resistance 1302
The motor is accelerated when the voltage is higher than ½ of the voltage cc, and when the voltage is lower than the voltage, the motor is decelerated. The md terminal is a terminal to which the output signal of the mode switching circuit 700 of FIG. 7 is supplied. As described above, it is "0" in the three-phase quasi full-wave drive and "1" in the three-phase full-wave drive.
become. In addition, the en-direction terminal is supplied with the rotation direction inconsistency signal from the rotation direction determination circuit 300 shown in FIG. 1 or 7, and when the level becomes “0”, the transistor 1303 is turned on, which is substantially the same. Therefore, the speed error voltage is set to the maximum value in the deceleration direction.

Now, in FIG. 12, resistors 1304, 1305, transistors
1306, 1307, 1308, resistor 1309, transistor 1310, 131
1, the resistors 1312 and 1313, the diodes 1314 and 1315 constitute an absolute value amplifier, and the resistance ratio of the input dividing resistors 1304 and 1305 is set to 19 to realize a wide input dynamic range. The output current of this absolute value amplifier is the diode
Transistors 1316, 1317, 1318, 13 through 1314, 1315
19 and resistors 1320, 1321, 1322 are supplied to the first current mirror circuit, and the output current of the transistor 1318 is further supplied to the transistors 1323, 1324, 1325, 13
26, and is supplied to a second current mirror circuit composed of resistors 1327, 1328 and 1329, and the output current of the transistor 1319 is supplied to a third current mirror circuit composed of transistors 1330, 1331 and 1332. . The output currents of the transistors 1325, 1326, 1332 are supplied to the sf1 terminal, the sf terminal, and the cf terminal, respectively.
When the level of the d terminal is "1", that is, in the case of full-wave driving, the transistor 1333 is turned on and current is supplied only to the cf terminal, and conversely, the level of the md terminal is "0". , The transistor 1333 is turned off, and the transistor 1334 is turned on instead.
Is turned on, and current is supplied to the sf1 terminal and the sf terminal.

Therefore, cf1 to which the output current for the three-phase full wave is supplied
When the level of the md terminal is '1', the current corresponding to the potential of the E terminal is absorbed from the terminal, and the output current for the three-phase quasi full wave is supplied. When it is "0", the current corresponding to the potential of the E terminal is absorbed.

In addition, transistors 1335, 1336, 1337, 1338, 1339, 13
40, 1341 and resistors 1342, 1343 form a comparator, and when the potential of the E terminal becomes lower than the potential given by the resistors 1301, 1302, the level of the dn terminal becomes "1", and vice versa. It becomes "0" when it becomes higher, but this output is used as a command signal for accelerating or decelerating the motor.

Next, FIG. 13 shows the quasi-full-wave phase switching circuit 9 shown in FIG.
00, step current generation circuit 1200, slope generation circuit 140
FIG. 9 is a circuit connection diagram showing a specific configuration example of 0, the slope synthesis circuit 1500, and the rotation stop detector 2100. Each input / output terminal is connected to the same place as the input / output terminal shown in FIG. Things are indicated by the same symbols.

First, the slope generation circuit 1400 includes a charge / discharge circuit including a capacitor 1401 for generating a sawtooth wave, a constant current transistor 1402, and a discharge transistor 1403, transistors 1404, 1405, 1406, 1407, and a diode.
First comparator centered on 1408 and transistor
1409, diode 1410, transistors 1411, 1412, 141
A second comparator centered on 3, 1414 and a resistor 1415, and an output buffer stage constituted by transistors 1416, 1417 and a resistor 1418, supplies the output of the x1 terminal to the synchronous trigger circuit 600 of FIG. By supplying the output of the synchronous trigger circuit 600 to the x2 terminal, the lowest potential is equal to the forward voltage of the diode 1408 at the SC terminal to which the capacitor 1401 is connected, and the amplitude is approximately across the resistor 1415. A sawtooth voltage equal to twice the voltage appears, and the repetition period of this sawtooth wave is equal to the arrival period of the leading edge of the position detection signal shown in FIGS. , F for full-wave drive
It is equal to the arrival period of the leading edge and the trailing edge of the G signal. That is, the synchronous trigger circuit 6 of FIG.
00 shifts the level of the x2 terminal to "1" when the leading edge of the input signal supplied to the NAND gates 601, 604, and 610 arrives, which turns on the transistor 1403 that configures the slope generation circuit 1400. , The electric charge accumulated in the capacitor 1401 up to that point is rapidly discharged. When the potential of the SC terminal becomes lower than the forward voltage of the diode 1408 due to this discharge, the base current is not supplied to the transistor 1406, and the level of the x1 terminal becomes “1”. On the other hand, the synchronous trigger circuit 600 has three RSs when the level of the x1 terminal shifts to "1".
Since the flip-flop is configured to be reset, the level of the x2 terminal returns to "0" at this point, as a result, the transistor 1403 is turned off, and the capacitor 1401 is charged. It In this way, the charging and discharging of the capacitor 1401 is repeated, so that a sawtooth voltage appears at the SC terminal. Further, the sawtooth voltage is smoothed by the resistor 1419 and the capacitor 1420, and then is smoothed by the second comparator 1415.
Transistor 1413 regulates the charging current of the capacitor 1401 so that the potential at the VC terminal is always equal to the voltage across the resistor 1415 plus the forward voltage of the diode 1410, compared to the voltage across the capacitor 1401. Therefore, SC
The amplitude of the sawtooth wave voltage appearing at the terminal does not depend on the repetition period of the pulse train supplied to the x2 terminal, and
It is almost twice the voltage across both ends. This is because when the sawtooth wave of FIG. 11I is combined with the signal waveform of FIG. 11J to create the signal waveform of FIG. 11M, a similar signal waveform is always produced regardless of the change in the rotation speed of the motor. This is an important function to obtain.

Next, the rotation stop detector 2100 comprises a charge / discharge circuit composed of a capacitor 2101, a constant current transistor 2102 and a discharge transistor 2103, and a detection circuit composed mainly of the transistors 2104 and 2105. When the motor is rotating, a pulse train appears at the x2 terminal, so charging and discharging of the capacitor 2101 are repeated, the potential at the QC terminal is maintained at a sufficiently low value, and the base current continues to flow to the transistor 2104. When the transistor stops rotating, the transistor 2102 is saturated and the base current stops flowing in the transistor 2104. At this time, the transistor 2105 is turned off, and the level of the qt terminal becomes "1".

NAN constituting the mode switching circuit 700 shown in FIG.
The rotation stop detector 2100 is connected to one input terminal of the D gate 706.
Output signal is supplied, but the level of the qt terminal is "1"
If the D flip-flop 701 for switching between the quasi full-wave drive and the full-wave drive is reset, the output level of the NAND gate 706 shifts to "0", so that the D flip-flop 701 is set. To be done. In this way, the rotation stop detector 2100 initializes the mode switching circuit 700, so that the motor can be reliably started and restarted when a sudden external force is applied during rotation. The rotation stop detector 2100 is not always necessary if initialization setting is made via the J terminal. For example, since the NAND gate 2002 constituting the initialization circuit 2000 of FIG. 7 generates the set signal of the D flip-flop by temporarily shifting the level of the J terminal to '1',
In a device such as a video tape recorder that employs system control by a microcomputer, the level of the J terminal may be temporarily shifted to "1" when the power is turned on or the rotation of the motor is stopped.

Next, the operation of the step current generation circuit 1200 will be described with reference to the signal waveform diagram of FIG.

In FIG. 13, transistors 1201, 1202, 1203, 120
4,1205,1206,1207,1208, Resistance 1209,1210,1211,1
212, 1213, 1214, 1215, transistors 1216, 1217, 121
8, 1219, 1220, resistors 1221, 1222, 1223, 1224, 1225,
The transistor 1226 and the resistor 1227 form a current mirror circuit that sends out five systems of current output by using the cf terminal as a power receiving terminal. The transistors 1203 to 1208 are shown in FIG.
And N step current waveforms are generated, the transistors 1216-1220 generate the step current waveforms of K and O in FIG. 11, and the output current of the transistor 1226 is the amplitude of the sawtooth wave generated in the slope generation circuit 1400. Control.

Now, the transistors 1203, 1204, 1205, 1206, 120
The output current ratio from each of the split collectors 7 and 1208 is 5: 5: 4: 3: 2: 1, and the transistor 121
The output current ratio from each split collector of 6, 1217, 1218, 1219, 1220 is 1: 1: 1: 1: 1, and the collector current of the transistor 1226 and the output current from each split collector of the transistor 1203. But cf
It becomes one-fourth of the current supplied to the terminal, and the output current from each split collector of the transistor 1216 is cf.
The emitter area of each transistor and the resistances 1209, 1210, 1211, 12 are set to be 1/20 of the current supplied to the terminals.
12, 1213, 1214, 1221, 1222, 1223, 1224, 1225, 1227
Assuming that the resistance value of is set, um in Fig. 13
0-um5 terminal, us1-us4 terminal, wm0-wm5
When the section signals shown in FIG. 10 are supplied to the terminals ws1 to ws4, respectively, the step current generation circuit 1200
The output current waveforms sent to the u0 terminal and w0 terminal of FIG. 13 are as shown in FIGS. 11J and N, respectively, and the step current generation circuit 1200 to the slope synthesis circuit of FIG.
The output current waveforms sent to 1500 are shown in Fig. 11 K and O, respectively.
It becomes like.

The slope synthesis circuit 1500 is supplied from the output signal of the addition / subtraction command circuit 800 supplied to the ua terminal and wa terminal of FIG. 13, the sawtooth wave supplied from the slope generation circuit 1400, and the step current generation circuit 1200. The drive current waveform of FIG. 11M or FIG. 11Q is created based on the step current for limiting the combined current.

A sawtooth wave shown in FIG. 11I appears at the emitter of the transistor 1417 that constitutes the slope generation circuit 1400. This voltage waveform has a positive offset voltage corresponding to the forward voltage of the diode 1408 as described above. Have
Transistors 1501 and 15 that make up the slope synthesis circuit 1500
Both 02 convert the output voltage of the slope generation circuit 1400 into a current and absorb the offset voltage by its base-emitter voltage. The bases of the transistors 1501 and 1502 are connected to the emitters of PNP-type transistors 1503 and 1504 whose collectors are grounded, and the resistors 1505 and 1506 connected to the bases of the transistors 1503 and 1504 are connected to the eleventh electrodes, respectively. The output current of the step current generation circuit 1200 shown in FIGS. Since the base-emitter voltage of the transistors 1503 and 1504 cancels out those of the transistors 1501 and 1502, respectively, the transistors 1503 and 1504 set the maximum emitter potential of the transistors 1501 and 1502 to the transistor 15
It works to limit the potential on the base side of 03,1504. As a result, the collector currents of the transistors 1501 and 1502 are
It changes as shown in FIGS.

The collector current of the transistor 1501 is the transistor 15
07, 1508, 1509 and resistors 1510, 1511 are supplied to the current outflow type current mirror circuit, one output current of the two split collectors of the transistor 1509 is supplied to the u0 terminal, and the other output current. Is supplied to a current inflow type current mirror circuit composed of transistors 1512 and 1513, and the collector of the transistor 1513 is also connected to the u0 terminal. It is assumed here that the transistor 1513 has an emitter area twice as large as that of the transistor 1512. The transistor 151
The collector of a transistor 1514, whose emitter is grounded, is connected to the common bases of 2 and 1513.
14 base, via the ua terminal, when the full wave drive
The signal waveform of FIG. 11G is supplied.

When the transistor 1514 is in the ON state, the collector current of the transistor 1513 does not flow, and the output current of one split collector of the transistor 1509 is added to the current supplied from the step current generation circuit 1200 to the u0 terminal. When the transistor 1514 is turned off, a current corresponding to the output current of the other split collector of the transistor 1509 is subtracted from the current supplied from the step current generation circuit 1200 to the u0 terminal. Therefore, the current supplied to the U-phase drive circuit 1600 of FIG. 1 via the u0 terminal changes as shown in FIG. 11M. The transistor 1515 is turned on during the quasi-full-wave driving to increase the voltage-current conversion ratio of the transistor 1501.

On the other hand, the W-phase slope combining circuit composed of the transistors 1502 and 1504, the resistor 1506, the transistors 1516, 1517 and 1518, the resistors 1519 and 1520, and the transistors 1521, 1522, 1523 and 1524 also operates in the same manner, and as a result, , Q0, the current supplied to the W-phase drive circuit 1700 of FIG. 1 changes as shown in FIG. 11Q.

Next, the quasi-full-wave phase switching circuit 900 is prepared for operation during quasi-full-wave driving, and its operation will be described with reference to the signal waveform diagram shown in FIG. The process of generating the drive signal during the quasi full-wave drive will also be described. 14A and 14B show the signal waveforms supplied to the n2 terminal and z2 terminal of FIG. 13, respectively, and FIG. 14C shows the output signal waveform of the slope generation circuit 1400 during quasi-full-wave driving. Yes, D, E, F, and G in FIG. 14 are transistors 906, 905, 904, and 903 constituting the quasi-full-wave phase switching circuit 900, respectively.
14H and I are output signal waveforms of the addition / subtraction command circuit 800 supplied to the slope synthesis circuit 1500 via the ua terminal and the wa terminal of FIG. 13, respectively.
14J and K are the emitter current waveforms of the transistors 1501 and 1502 that form the slope synthesis circuit 1500, respectively.
14 L and M are output current waveforms sent to the conduction direction switching circuit 1100 via the u0 terminal and the w0 terminal, respectively,
Fig. 14 N, O, P and Q are all energization direction switching circuits 1100
Is a current waveform supplied to the U-phase drive circuit 1600 and the W-phase drive circuit 1700 from FIG. 14, both R and S of FIG. 14 are current waveforms supplied from the current addition circuit 1800 of FIG. 1 to the V-phase drive circuit 1900. Is.

The quasi-full-wave phase switching circuit 900 includes transistors 901, 902, 9
03, 904, 905, 906, 907, resistance 908, 909, 910,
A current mirror circuit composed of 911, 912, and 913, which uses the sf terminal as a power receiving terminal, and transistors 914 and 9
It is composed of a switching circuit centering on 15, 916, 917, 918, and 919, and performs an operation corresponding to the step current generation circuit 1200 at the time of full-wave drive.

That is, the quasi-full-wave phase switching circuit 900 operates in the 14th phase during quasi-full-wave driving.
The current signals of FIGS. E, F, G, and H are sent to the slope synthesizing circuit 1500, while the slope synthesizing circuit 1500 operates in the same manner as during full-wave driving, and the driving current signals of FIG. Create a drive current signal. The energizing direction switching circuit 1100, which will be described next, uses the drive current signals from N, O, and FIG.
Two sets of drive signals shown by P and Q are created and supplied to the U-phase drive circuit 1600 and the W-phase drive circuit 1700.

Both the signal waveform of FIG. 14C and the signal waveform of FIG. 11I are output signal waveforms of the slope generation circuit 1400. The former is generated during quasi-full-wave driving, while the latter is full-wave. Created when driving. The former repeating cycle is equal to the arrival cycle of the leading edge or trailing edge of the position detection signal shown in FIGS. 14A and 14B, while the latter repeating cycle is shown in FIG. 11B. It becomes equal to the arrival period of the leading edge and trailing edge of the FG signal. On the other hand, FIG.
Since the period of the slope portion of the drive current waveform shown in FIG. 14 depends on that of the emitter current waveform of the transistors 1501 and 1502 shown in FIGS.
The ratio of the collector currents of the transistors 906 and 905 to the collector current of 1 determines the slope period. The resistance value of the resistors connected to the collectors of the transistors 1515 and 1524 is the maximum value of the current supplied to the u0 terminal and the w0 terminal from the slope synthesis circuit 1500 (the peak value of the trapezoidal wave) from the transistors 904 and 903. It is selected to be equal to the current value supplied to the u0 terminal and the w0 terminal.

Next, FIG. 15 shows the energizing direction switching circuit 1100, U of FIG.
Phase drive circuit 1600, W phase drive circuit 1700, current addition circuit 180
3 is a circuit connection diagram showing a specific configuration example of a 0, V-phase drive circuit 1900. FIG.

The energization direction switching circuit 1100 responds to the rotation direction discrimination signal supplied from the rotation direction discrimination circuit 300 of FIG. 7 via the dr terminal and the U-phase drive current signal supplied via the u0 terminal and the w0 terminal. The function of exchanging the w-phase drive current signal supplied via the and the polarity of these drive current signals.
When the stop signal is supplied from the mode switching circuit 700 of FIG. 7 via the bk terminal and the function of switching according to the level of the 1 terminal and the w1 terminal, the U-phase drive circuit 160
It has a function of causing the 0, W-phase drive circuit 1700, and V-phase drive circuit 1900 to be energized in only one direction.

Now, assuming that the motor is rotating in the forward direction and the level of the dr terminal is "0", the energizing direction switching circuit
The transistors 1101 and 1102 included in 1100 are off, and the transistor 1103 is on. Therefore, the driving current supplied to the u0 terminal passes through the transistor 1104 and is transmitted to the transistors 1105, 1106, 110.
7, 1108, 1109 and resistors 1110, 1111, 1112, 1113 are supplied to the current outflow type current mirror circuit, and the drive current supplied to the w0 terminal is the transistor 1114.
Through the transistors 1115, 1116, 1117, 1118, 111
9 and the resistors 1120, 1121, 1122 and 1123 are supplied to the current outflow type current mirror circuit. further,
The collector current of the transistor 1109 is
1124, 1125, 1126, 1127 and resistors 1128, 1129, 1130 are supplied to a current inflow type current mirror circuit. , 1137 to the current inflow type current mirror circuit. On the other hand, during the quasi-full-wave drive, the output current from the error signal amplifier 1300 is transferred through the sf1 terminal to the transistors 1138, 1139, 1140, 1141, 1142, 1143, and the resistors 1144, 11.
It is supplied to the current outflow type current mirror circuit composed of 45, 1146, 1147 and 1148.

First, the level of the u1 terminal is "1" during full-wave driving.
, The transistor 1149 is on,
The transistors 1150 and 1151 are turned off. At this time, the collector current of the transistor 1107 is supplied to the upper drive circuit that constitutes the U-phase drive circuit 1600 via the diode 1152, but the collector current of the transistor 1108 is absorbed by the transistor 1149 via the diode 1153, and Since current is not supplied through the sf1 terminal, no current is supplied to the lower drive circuit that constitutes the U-phase drive circuit 1600. On the contrary, the level of the u1 terminal is "0".
, The transistor 1149 is off,
The transistors 1150 and 1151 are turned on. At this time, the collector current of the transistor 1108 is supplied to the lower drive circuit that constitutes the U-phase drive circuit 1600 via the diode 1154, but the collector current of the transistor 1107 is absorbed by the transistor 1150.
No current is supplied to the upper drive circuit that constitutes the 1600.

The W-phase circuit block operates in the same manner as in the U-phase, and w1
When the level of the terminal is "1", the drive current is supplied to the upper side drive circuit constituting the W-phase drive circuit 1700 via the transistor 1117 and the diode 1155, and the level of the w1 terminal is "0". Sometimes transistor 1118
A drive current is supplied to the lower drive circuit via the diode 1156 and the diode.

In this way, the drive current waveforms shown in FIGS. 11M and Q correspond to the upper drive circuits and the lower drive circuits of the U-phase and the W-phase, respectively, according to the levels of the signals shown in FIGS. Distributed to the circuit.

Error signal amplifier from sf1 terminal during quasi-full-wave drive
Since the output current of 1300 is supplied,
The current mirror circuit constituted by 1143 and resistors 1144-1148 becomes active, and as shown in N, O, P, and Q of FIG. A drive current is supplied to the lower drive circuit. That is, at time t ₉ in FIG. 14, the current supplied through the u0 terminal is zero as shown in FIG. 14L, so that even if the level of the u1 terminal is '1', the diode
The current supplied to the U-phase upper drive circuit via 1152 becomes zero, but the collector current of the transistor 1140 is supplied to the lower drive circuit via the diode 1157. The current mirror ratio is set so that the collector current of the transistor 1140 becomes one half of the current supplied through the sf1 terminal. U at time t _10.
The current supplied through the 0 terminal reaches the maximum value, the same value current is supplied to the U-phase upper side driving circuit through the diode 1152, and all the collector current of the transistor 1140 is absorbed by the transistor 1127. Therefore, the current supplied to the lower drive circuit of the U phase via the diode 1157 becomes zero. These operations are the same for the W phase.

Now, when the motor is rotating in the reverse direction and the level of the dr terminal is "1", the transistor 1102 is turned on and the transistor 1103 is turned off. At this time, the current supplied from the u0 terminal is the transistor 1158.
Is supplied to the current mirror circuit on the W phase side via
The current supplied from the terminal is U via the transistor 1159.
Since it is supplied to the current mirror circuit on the phase side, the U-phase drive signal and the W-phase drive signal have been exchanged. The replacement of the drive signals corresponds to the replacement of the position detection signals in the sequential circuit 200.

When the level of the bk terminal becomes "0", the transistor 1260
Is turned off, and as a result, the transistors 1261 and 126
2, 1263 is turned on to absorb the drive current supplied to the lower drive circuit of each phase, so that only the upper drive circuit of each phase is activated and the stator windings 1 to 3 of FIG. Only the circuit current of the Hall IC 6 flows through the circuit. Therefore, although the motor does not generate rotational torque, the Hall IC 6 is still in a position to detect the position even when the motor is stopped.

Next, since the U-phase drive circuit 1600, the W-phase drive circuit 1700, and the V-phase drive circuit 1900 are all simple current amplifiers configured by combining current mirror circuits, description of the operation is omitted, but each phase is omitted. The last stage of the upper drive circuit of NPN
Type power transistor is used, and the stator winding 1 ~
3 has a special structure in order to minimize the residual voltage at the time of supplying the maximum current, the description will be given using the U-phase drive circuit 1600 as an example.

If the configuration of the current mirror circuit consisting of the transistors 1601 and 1602 and the transistor 1603 that form the final stage of the lower drive circuit of the U-phase drive circuit 1600 is used for the upper final stage as it is, between the collector and emitter of the transistor 1602 The voltage is not less than the sum of the base-emitter voltage of the transistor 1601 and the base-emitter voltage of the transistor 1602 plus the saturation voltage of the PNP transistor in the preceding stage, and is about 1.8 V in minimum value.

On the other hand, the transistor 1604 that constitutes the uppermost final stage
The collector-emitter voltage of can reach the value obtained by adding the saturation voltage of the transistor 1605 in the preceding stage to its own base-emitter voltage, and its minimum value is about 1.1V.

Now, the current adding circuit 1800 has transistors 1801 and 1802 that output a current equal to the drive current supplied to the upper drive circuit of the U-phase drive circuit 1600 and a transistor that outputs a current equal to the drive current supplied to the lower drive circuit. 1803, 1804
And transistors 1805 and 1806 that take out a current equal to the drive current supplied to the upper drive circuit of the W-phase drive circuit 1700.
And transistors 1807 and 1808 which take out a current equal to the drive current supplied to the lower drive circuit, and a diode 1809,
1810, 1811, 1812, and the transistor
The collector of 1801 and the collector of the transistor 1807 are connected to each other, and the anode of the diode 1809 is connected to the connection point between them, and the collector of the transistor 1806 and the collector of the transistor 1804 are connected to each other and the diode 1812 is connected to the connection point. , The cathode of the diode 1812 is connected to the cathode of the diode 1809, the collector of the transistor 1802 and the collector of the transistor 1808 are connected, the cathode of the diode 1810 is connected to the connection point, The collector of the transistor 1805 and the collector of the transistor 1803 are connected, the cathode of the diode 1811 is connected to the connection point, and the anode of the diode 1811 is connected to the cathode of the diode 1810. further,
The anodes of the diodes 1810 and 1811 are V-phase drive circuits 19
00 is connected to the receiving point vp of the drive current of the upper drive circuit,
The cathodes of the diodes 1809 and 1812 are V-phase drive circuits 19
00 is connected to the power receiving point vn of the drive current of the lower drive circuit.

Here, the magnitude of the current supplied to the power receiving point up of the drive current of the upper drive circuit of the U-phase drive circuit 1600 is Iup, and the magnitude of the current supplied to the power receiving point un of the drive current of the lower drive circuit Is Iun, and Iwp is the magnitude of the current supplied to the drive current of the upper drive circuit of the W-phase drive circuit 1700, and Iwp is the magnitude of the current supplied to the power reception point wn of the drive current of the lower drive circuit. Let Iwn be the transistor 1801, 1
A current of magnitude Iup flows out of the collector of 802, a current of magnitude Iun is absorbed in the collectors of the transistors 1803 and 1804, and a current of magnitude Iup is absorbed from the collectors of the transistors 1805 and 1806. ,Each
A current of the magnitude Iwp is drained and the transistor 18
Currents of magnitude Iwn are absorbed by the collectors of 07 and 1808, respectively.

Therefore, when the value of Iup becomes larger than the value of Iwn, the difference current is supplied to the vn point through the diode 1809, and when the difference of Iwp becomes larger than the value of Iun, the difference current becomes Is supplied to the vn point via 1812,
When the value of Iun becomes larger than the value of Iwp, the difference current is supplied to the point vp through the diode 1811,
When the value of Iwn becomes larger than the value of Iup, the difference current is supplied to the point vp via the diode 1810.

That is, the value Ivp of the drive current supplied from the current addition circuit 1800 to the upper drive circuit of the V-phase drive circuit 1900 and the value Ivn of the drive current supplied to the lower drive circuit are given by the following equations.

In this way, transistors 1802 and 1808
And a pair of the transistor 1803 and the transistor 1805 cause a difference current between a current flowing into the U phase or the W phase and a current flowing out of the W phase or the U phase to flow into the V phase,
The pair of 01 and the transistor 1807 and the pair of the transistor 1804 and the transistor 1806 operate so as to cause the difference current between the current flowing out from the U phase or the W phase and the current flowing into the W phase or the U phase to flow out from the V phase.

The current waveforms shown in FIG. 14 R and S are shown in FIG. 14 N, O,
The results obtained from the above equations 7 and 8 are plotted based on the respective current values obtained from the current waveforms shown in P and Q, and the current waveforms in FIGS. 11 and 12 are also the same. It is what I asked for. Of course, it has been confirmed that the same current waveform can be obtained not only in the calculation but also in the actual circuit shown in FIG.

Now, returning to FIG. 1, the outline of the operation described so far is summarized as follows.

First, when the level of the J terminal is '0' and the rotor of the motor is stopped, at least one of the U terminal, V terminal, and W terminal is at a high potential,
A current is supplied to the Hall IC 6 through one of the stator windings 1 to 3 and the current limiting resistor 8 to detect the stationary position of the rotor, and the Hall IC 6 has a high potential according to the stationary position of the rotor. Generates intermediate and low potential outputs. Hall i
The position detection signal is distributed by the distributor 100 according to the output level of C6.
Although it is supplied to the quasi-full-wave phase switching circuit 900 via, the sequential circuit 200 operates as a mere buffer while the level of the J terminal is "0", and the U-phase drive circuit 1600,
W phase drive circuit 1700, V phase drive circuit 1900 to stator winding 1
Power is not supplied to ~ 3.

When the level of the J terminal shifts to “1”, the drive circuit of each phase selects one of the U terminal, the V terminal, and the W terminal based on the position detection information supplied to the quasi-full-wave phase switching circuit 900. The current is absorbed from the terminal of to generate a rotation torque in the rotor. At this time, the Hall IC 6 was accidentally stopped at the position where the rotating electrical angle in FIG. 3 was 60 °, that is, at the boundary between the N pole and the S pole of the identification band 5, or at the position where the rotating electrical angle was 390 °. Then, in any case, the Hall IC 6 generates the same output as when facing the non-magnetized portion of the identification band 5, and the stator windings 1 to 3 are energized based on the information, so that FIG. As can be seen from the characteristic curve of B, the rotor will generate rotational torque in the opposite direction. However, since the normal position detection information is obtained by moving the rotor only slightly, and thereafter, the order circuit 200 regulates the order in which the position detection signals are received, so that the smooth rotation can be maintained.

When the rotor starts rotating, the FG signal from the generator winding 7 appears, so that the output level of the D flip-flop 701 (Fig. 7) that constitutes the mode switching circuit 700 shifts to "0" at a predetermined timing. Then, the energization mode to the stator windings 1 to 3 is switched to the three-phase full-wave drive, and the torque characteristic of the motor becomes like the envelope of the characteristic curve shown in FIG. 3C.

Even after the energization mode shifts to three-phase full-wave drive, the output level of the D flip-flop 701 returns to '1' if the motor speed decreases until the FG signal disappears due to a sudden load change or the like. The current-carrying mode is again three-phase quasi-full-wave drive.

On the other hand, if the J terminal level shifts to "0" while the energization mode is three-phase full-wave drive, D
As long as the output level of the flip-flop is "0",
The level of the 15 bk terminals is held at "1" and the energization to the stator windings 1 to 3 is continued. At this time, since the level of the J terminal is "0", as shown in Table 1, the NAND gate 1015 (7th
The output level shown in the figure is "1", and the energizing direction setting circuit 10
The phase of the output signal sent from 00 to the energization direction switching circuit 1100 is reversed, and the energization direction to the stator windings 1 to 3 is reversed,
The motor is decelerated rapidly. When the rotation speed of the motor becomes close to zero and the FG signal disappears or the rotation stop detector 2100 generates an output signal, the D flip-flop 7
Since the output level of 01 shifts to "1", the level of the bk terminal also shifts to "0" and the energization to the stator windings 1 to 3 is stopped.

Further, when a forward direction command signal is applied from the REV terminal while the motor continues to rotate in the reverse direction at the time of forward / reverse switching operation, the commanded rotation direction and the actual rotation direction match. The error signal amplifier 1300 and energization direction setting circuit 1000
Is supplied with a rotation direction mismatch signal. This makes the eleventh
When the level of the en terminal in the figure becomes "0", the transistor 1303 that was in the off state until then becomes the on state,
This is the same as when the potential of the E terminal drops to near zero, and the error signal amplifier 1300 supplies the maximum output current to the step current generation circuit 1200 via the cf terminal (during full-wave driving). On the other hand, when the rotation direction mismatch signal is supplied to the energization direction setting circuit 1000, as can be seen from Table 1, N in FIG.
Since the output level ex of the AND gate 1015 shifts to "1", the energization direction to the stator windings 1 to 3 is reversed and the motor is rapidly decelerated. When the rotation speed of the motor exceeds zero and starts to rotate in the positive direction, the output level of the D flip-flop 301 which constitutes the rotation direction discrimination circuit 300 of FIG. 7 becomes "0", and the level of the dr terminal. Goes to '0' and the level of the en terminal goes to '1',
After that, the motor is accelerated in the same manner as when starting from the stopped state.

Now, FIG. 16 is a cross-sectional view of the torque generating portion of the motor prepared for explaining the mechanism of vibration and noise generation. In FIGS. 16A and 16B, 11 is a rotor yoke to which the permanent magnet 4 is fixed. And 12 is the stator winding 1a,
1b is a stator yoke in which the curved line with an arrow represents a magnetic field line.

At the relative position of the rotor and the stator shown in FIG. 16A, the direction of the magnetic flux interlinking with the stator windings 1a and 1b is perpendicular to the magnetization direction of the permanent magnet 4, so The child windings 1a and 1b generate a force in a direction parallel to the magnetizing direction, and this becomes the rotational torque of the motor.

However, at the relative position between the rotor and the stator shown in FIG. 16B, the direction of the magnetic flux interlinking with the stator windings 1a and 1b becomes parallel to the magnetization direction of the permanent magnet 4, and The torque not only becomes zero but also generates a force in a direction perpendicular to the magnetizing direction of the permanent magnet 4. With the relative positional relationship shown in FIG. 16B and the direction of energization of the stator windings 1a and 1b, each stator winding generates a repulsive force that lifts the rotor, and When the energization direction is reversed, a force for attracting the rotor to the stator is generated, and the repeated repulsive suction is a major factor in the vibration of the motor, and noise is also generated along with the vibration.

The magnitudes of the repulsive force and the suction force are minimal at the relative position in FIG. 16A and maximal at the relative position in FIG. 16B, but at intermediate positions between these, gradually increase or depending on the position. Will decrease. Therefore, in order to reduce vibration and noise, repulsion per rotation of the rotor
It is only necessary to reduce the fluctuation of the suction, and a three-phase DC non-commutator motor has three sets of stator windings arranged at different electrical angles of 120 °. It suffices to create a drive current waveform such that the total of the repulsive force and the attractive force due to the winding hardly changes even when the rotor changes.

Specifically, in the signal waveform of FIG. 11M, when the slope from time t ₁₁ to time t ₁₃ greatly contributes to vibration and noise and the current is increased linearly from time t ₁₁ , It has been confirmed by calculation that, when the current waveform is set to maximize the current value before t _13, the fluctuations of the repulsive force and the attractive force increase sharply as the slope becomes steeper. In other words, in 3-phase full-wave drive with 180 ° energization, in order to minimize the force in the rotating shaft direction of the motor and reduce vibration and noise, the interval from the start of energization to 60 ° and the end of energization at 60 ° Managing the slope of the section will be an important factor.

On the other hand, in order to reduce the fundamental frequency component of the torque fluctuation of the motor, as is apparent by comparing the torque characteristics of FIG. 3A and the torque characteristics of FIG. From 30 ° to 30 ° and 30 until the end of energization
An important factor is the management of the shape of the energization waveform in the section other than the section of °.

In the DC non-commutator motor shown in FIG.
As is clear from the signal waveform of N, an arbitrary drive current waveform can be created by the step controller 500 and the step current generation circuit 1200, and the drive circuit of each phase is created by the step current generation circuit 1200 and the slope synthesis circuit 1500. Stator winding 1 produces a current proportional to the drive current
Supply to ~ 3. Therefore, it is possible to easily create a current waveform that minimizes vibration and noise during rotation of the motor. That is, during full-wave drive, the resistors 1209 to 121 in the step current generation circuit 1200 shown in FIG.
By changing the ratio of the resistance values of 5,1221 to 1224, 1225, and 1227, the shape of the drive current waveforms in FIGS. 11M and 11Q can be freely changed. In the quasi-full-wave phase switching circuit 900, the slope of the drive current waveform of FIGS. 14L and 14M can be selected to the optimum value by changing the ratio of the resistance values of the resistors 908 to 913.

By the way, as is clear from the signal waveform of FIG. 14, in the DC non-rectifier motor of the present invention, the slope generation circuit 1400
Generates a sawtooth wave having a cycle whose amplitude is proportional to the drive command signal from the error signal amplitude unit 1300 and which depends on the arrival cycle of the edge of the position detection signal, that is, the signal waveform of FIG. 14C. The signal waveform of FIG. 14J or 14K obtained by limiting the amplitude to a level proportional to the drive command current by 1500 and FIG. 14F.
Alternatively, the trapezoidal drive signal shown in FIG. 14L or 14M is created by addition or subtraction with the position detection signal of FIG. 14G.

For this reason, even in the case of quasi-full-wave drive, in which only three types of position detection are performed per 360 ° electrical angle as in ordinary half-wave drive, simple digital processing is performed, and therefore a relatively small-scale circuit configuration enables smooth operation. It is possible to create an increasing or decreasing drive current.

Although the three-phase DC non-commutator motor is shown in the embodiment of FIG. 1, the present invention has a sufficient effect when applied to not only a three-phase motor but also a two-phase or single-phase motor. It is a thing.

As is apparent from the above description, the DC non-commutator motor of the present invention detects the rotational position of the rotor and generates the position detection signal (in the embodiment, the Hall IC 6 and the distribution unit). 100 and the sequential circuit 200 constitute position detecting means), an error signal amplitude unit 1300 for generating a drive command current depending on a voltage or current supplied from the outside, and an edge of the position detecting signal. A slope generation circuit 1400 that generates a sawtooth wave having a cycle that depends on the arrival cycle, and adding a signal waveform obtained by limiting the amplitude of the sawtooth wave to a level proportional to the drive command current to the position detection signal. Slope synthesis circuit 1500 that obtains a trapezoidal wave-shaped drive signal
And a drive circuit (U-phase drive circuit 1600, W-phase drive circuit 1700, V-phase drive circuit 1900) that amplifies the drive signal and supplies the amplified drive signal to the stator winding. With the configuration, a drive current that smoothly increases or decreases can be produced, and a great effect is achieved.

[Brief description of drawings]

FIG. 1 is a block diagram of a DC non-commutator motor according to an embodiment of the present invention, FIG. 2 is a schematic diagram of a motor portion configured to carry out the present invention, and FIG. 3 shows torque characteristics of the motor. FIG. 4 is a torque characteristic diagram for explaining energization switching, FIG. 4 is an internal circuit connection diagram of the Hall IC, and FIG. 5 is a signal corresponding to a magnetization pattern of an identification band for explaining a processing operation of a position detection signal. Waveform diagram, FIG. 6 is a circuit connection diagram showing a configuration example of a distributor, and FIG. 7 is a sequential circuit, a rotation direction determination circuit, a step controller, a synchronous trigger circuit, a mode switching circuit, an addition / subtraction command circuit, a conduction direction setting circuit. , A logic circuit diagram showing a configuration example of the initialization circuit, FIG. 8, FIG. 9, and FIG.
Figures 11, 11 and 14 are all signal waveform diagrams for explaining the operation of each block in Fig. 1, Fig. 12 is a circuit connection diagram showing a configuration example of an error signal amplifier, and Fig. 13 is Quasi full-wave phase switching circuit, step current generating circuit, slope generating circuit, slope synthesizing circuit, circuit connection diagram showing a specific configuration example of the rotation stop detector, Fig. 15 is a conduction direction switching circuit, U-phase drive circuit , W-phase drive circuit, current addition circuit, V-phase drive circuit showing a specific configuration example of the circuit, FIG. 16 is a sectional view of the motor torque generating portion. 1, 2, 3 ... Stator winding, 4 ... Permanent magnet, 6 ... Hall IC, 200 ... Sequential circuit, 600 ... Synchronous trigger circuit, 900 ... Quasi full-wave phase switching circuit, 1300 ... Error signal amplifier, 1400 ... Slope generation circuit, 1500 ... Slope synthesis circuit, 1600 ... U phase drive circuit, 1700 ... W phase drive circuit,
1900 ... V-phase drive circuit.

Claims (1)

[Claims] 1. A rotor provided with a stator winding, a permanent magnet having a magnetized portion facing the stator winding, and a position for detecting a rotational position of the rotor to generate a position detection signal. Detecting means, an error signal amplifier that generates a drive command current that depends on a voltage or current supplied from the outside, and a slope generation circuit that generates a sawtooth wave with a cycle that depends on the arrival cycle of the edge of the position detection signal. A slope synthesizing circuit for obtaining a trapezoidal drive signal by adding a signal waveform obtained by limiting the amplitude of the sawtooth wave to a level proportional to the drive command current, and an amplitude of the drive signal. A direct current non-commutator motor comprising a drive circuit for supplying the stator winding to the stator winding.