JPS6228804A - Proportional integration device - Google Patents
Proportional integration deviceInfo
- Publication number
- JPS6228804A JPS6228804A JP16748585A JP16748585A JPS6228804A JP S6228804 A JPS6228804 A JP S6228804A JP 16748585 A JP16748585 A JP 16748585A JP 16748585 A JP16748585 A JP 16748585A JP S6228804 A JPS6228804 A JP S6228804A
- Authority
- JP
- Japan
- Prior art keywords
- deviation
- signal
- proportional
- feedback
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- Feedback Control In General (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、目標値と現在値との偏差量から比例積分器へ
の入力を決定する事により比例積分動作を高速に行なう
比例積分装置に関するものである。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a proportional integral device that performs proportional integral operation at high speed by determining input to a proportional integrator from the amount of deviation between a target value and a current value. It is something.
従来のこの種の比例積分装置として第3図に示す目標値
と現在値との偏差量のみから制御する比例積分装置が知
られている。As a conventional proportional-integral device of this type, there is known a proportional-integral device shown in FIG. 3 which performs control only from the amount of deviation between a target value and a current value.
図において、1は基準信号2と、フィートノ<ツク信号
3の偏差ikヲ算出する加減算器、4はこの算出結果か
ら得られた制御動作信号5を入力し、制御出力信号6を
出力する比例積分器で、この制御量は比例要素の場合、
一定のゲインでゲイン倍され、また積分要素の場合、時
定数に応じた変化率で積分される。7は人力された制御
量6をフィードバック信号3に変換して、上記加減算器
1に出力するフィードバック要素である。このような構
成から成る従来の比例積分装置においては、制御対象分
の設定された基準信号2とフィードバック信号3との偏
差量を比−例積分器4によって制御出力信号6として出
力していた。In the figure, 1 is an adder/subtractor that calculates the deviation between the reference signal 2 and the foot signal 3, and 4 is a proportional integral that inputs the control operation signal 5 obtained from this calculation result and outputs the control output signal 6. In the case of a proportional element, this controlled variable is
The gain is multiplied by a constant gain, and in the case of an integral element, it is integrated at a rate of change depending on the time constant. A feedback element 7 converts the manually controlled control amount 6 into a feedback signal 3 and outputs it to the adder/subtractor 1. In the conventional proportional integration device having such a configuration, the deviation amount between the reference signal 2 set for the controlled object and the feedback signal 3 is outputted as the control output signal 6 by the proportional integrator 4.
従来の比例積分装置は以上のように構成されているので
、応答の遅い制御系に於いては、目標値とフィードバッ
クの偏差量が少ない場合には、より応答が遅くなり、パ
ラメータ一定の為、制御系の応答性を充分に満足するこ
とが不可能であるという問題点があった。Conventional proportional-integral devices are configured as described above, so in a control system with a slow response, if the amount of deviation between the target value and feedback is small, the response will be slower, and since the parameters are constant, There was a problem in that it was impossible to fully satisfy the responsiveness of the control system.
本発明は上記の様な問題点を解消する為になされたもの
で、目標値とフィードバック値の偏差量を目標値の変化
に伴ない変化させ、制御系の応答を高める墨のできる比
例積分装置tを得る!J!を目的とする。The present invention has been made to solve the above-mentioned problems, and is a proportional-integral device that changes the amount of deviation between the target value and the feedback value in accordance with the change in the target value, and increases the response of the control system. Get t! J! With the goal.
この発明に係る比例積分装置は、比例積分器への基準信
号全目標値とフィードバック値の偏差量の関数として変
化させることにより最適な応答を得られるようにしたも
のである。The proportional integrator according to the present invention is capable of obtaining an optimal response by changing the reference signal to the proportional integrator as a function of the amount of deviation between the total target value and the feedback value.
この発明における比例積分装置は目標値が変化しても、
その変化に伴って偏差量を変化させるので最適な応答を
得られる。Even if the target value changes, the proportional integral device in this invention
Since the amount of deviation is changed in accordance with the change, an optimal response can be obtained.
以下、この発明の一実施例を図について説明する。第1
図において、8は基準信号2をゲイン倍9する乗算器、
10は基準信号2とフィードバック値3との偏差11金
算出する加減算器、12は基準信号とフィードバック値
の偏差11が変化する事を検出する比較器、13は基準
信号全ゲイン倍9する時間を決定するタイマーである。An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 8 is a multiplier that multiplies the reference signal 2 by a gain of 9;
10 is an adder/subtractor that calculates the deviation 11 between the reference signal 2 and the feedback value 3, 12 is a comparator that detects a change in the deviation 11 between the reference signal and the feedback value, and 13 is the time to multiply the total gain of the reference signal by 9. It is a timer that determines.
次に動作について説明する。まず加減算器10により基
準入力信号2とフィードバック信号3との偏差11が算
出される。この偏差を比較器12で所定値と比較し、こ
の所定値より大きくなった時、タイマ13により、一定
期間(時定数間)の間、ゲイン9が乗算器8により基準
信号2に乗算される。つまり、微小の基準入力信号であ
っても、時定数間ゲイン倍される為、制御動作信号5が
大なる過渡領域での応答性を向上させることができる。Next, the operation will be explained. First, the adder/subtractor 10 calculates the deviation 11 between the reference input signal 2 and the feedback signal 3. This deviation is compared with a predetermined value by the comparator 12, and when it becomes larger than the predetermined value, the timer 13 causes the multiplier 8 to multiply the reference signal 2 by the gain 9 for a certain period (during the time constant). . In other words, even a very small reference input signal is multiplied by the gain during the time constant, so that the response in a transient region where the control operation signal 5 is large can be improved.
第2図は比例積分要素を含む直結フィードバック系のイ
ンデシャル応答を表わしているが、図において従来技術
におけるフィードバック信号は特性Aで示され、この特
性Aより本発明におけるフィードバック信号を示す特性
Bの応答性の方が速やかに目標値へ到達する事を示して
いる。また特性Bはl×αの目標値に対し、接近してい
くが、時定数時間後に目標値が図におけるu(t)に示
されるように1×αから1に変化する為、特性Cのフィ
ードバック値と打ち消し合って、特性Aよりも早く、目
標に到達する事が可能である。FIG. 2 shows the initial response of a direct-coupled feedback system including proportional-integral elements. In the figure, the feedback signal in the prior art is shown by characteristic A, and from this characteristic A, the response of characteristic B is the feedback signal in the present invention. This shows that the target value is reached more quickly in the case of gender. Characteristic B approaches the target value of l×α, but after a time constant time, the target value changes from 1×α to 1 as shown by u(t) in the figure, so characteristic C It is possible to reach the target faster than characteristic A by canceling out the feedback value.
なお、上記実施例では、比例積分装置の場合について示
したが通常の比例積分制御を用いる他の制御対象装置で
あってもよく、上記実施例と同様の効果を奏する。In addition, although the case of a proportional-integral apparatus was shown in the said Example, the other controlled apparatus which uses normal proportional-integral control may be used, and the same effect as the said Example will be produced.
以上の様に、本発明によれば比例積分器への基準信号を
目標値とフィードバック値の偏差量の関数として変化さ
せるよう構成したので、制御系の応答性を回上させるこ
とができるという効果がある。As described above, according to the present invention, since the reference signal to the proportional integrator is configured to change as a function of the amount of deviation between the target value and the feedback value, the responsiveness of the control system can be improved. There is.
第1図は本発明の一実施例を示す積分装置の構成図、第
2図は従来装置と本発明の装置とのインデシャル応答を
比較して示す特性図、第3図は従来装置の構成を示す構
成図である。
図中、1は加減算器、2は基準信号、3はフィードバッ
ク信号、4は比例積分器、5は制御動作信号、6は制御
量信号である。
なお1図中同一符号は同−又は相当部分を示す。
特許出願人 三菱を機株式会社
代理人 弁理士 1)1 博 昭
(外2名)Fig. 1 is a configuration diagram of an integrating device showing an embodiment of the present invention, Fig. 2 is a characteristic diagram showing a comparison of the initial responses of a conventional device and a device of the present invention, and Fig. 3 is a diagram showing the configuration of the conventional device. FIG. In the figure, 1 is an adder/subtractor, 2 is a reference signal, 3 is a feedback signal, 4 is a proportional integrator, 5 is a control operation signal, and 6 is a control amount signal. Note that the same reference numerals in each figure indicate the same or corresponding parts. Patent applicant Mitsubishi Oki Co., Ltd. Agent Patent attorney 1) 1 Hiroshiaki (2 others)
Claims (1)
バック信号から偏差量を算出する加減算器と、この加減
算器による算出結果から得られた制御動作信号により制
御出力信号を出力する比例積分器とを備えた比例積分装
置において、前記偏差量を目標値の変化に伴つて変化さ
せることにより最適基準信号を決定するフイードフオワ
ード機能を備えたことを特徴とする比例積分装置。A proportional controller equipped with an adder/subtractor that calculates the amount of deviation from a reference signal for the controlled object and a feedback signal indicating the current value, and a proportional integrator that outputs a control output signal based on the control operation signal obtained from the calculation result of the adder/subtractor. What is claimed is: 1. A proportional integration device comprising a feed forward function for determining an optimal reference signal by changing the amount of deviation in accordance with a change in a target value.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16748585A JPS6228804A (en) | 1985-07-31 | 1985-07-31 | Proportional integration device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16748585A JPS6228804A (en) | 1985-07-31 | 1985-07-31 | Proportional integration device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6228804A true JPS6228804A (en) | 1987-02-06 |
Family
ID=15850555
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16748585A Pending JPS6228804A (en) | 1985-07-31 | 1985-07-31 | Proportional integration device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6228804A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1991013390A1 (en) * | 1988-03-28 | 1991-09-05 | Unit Instruments, Inc. | Fast response control circuit |
-
1985
- 1985-07-31 JP JP16748585A patent/JPS6228804A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1991013390A1 (en) * | 1988-03-28 | 1991-09-05 | Unit Instruments, Inc. | Fast response control circuit |
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