JPS58144907A - Digital controller - Google Patents

Digital controller

Info

Publication number
JPS58144907A
JPS58144907A JP2681482A JP2681482A JPS58144907A JP S58144907 A JPS58144907 A JP S58144907A JP 2681482 A JP2681482 A JP 2681482A JP 2681482 A JP2681482 A JP 2681482A JP S58144907 A JPS58144907 A JP S58144907A
Authority
JP
Japan
Prior art keywords
integrator
control
initial value
output
manipulated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2681482A
Other languages
Japanese (ja)
Inventor
Yoshinao Sano
佐野 芳直
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP2681482A priority Critical patent/JPS58144907A/en
Publication of JPS58144907A publication Critical patent/JPS58144907A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B11/00Automatic controllers
    • G05B11/01Automatic controllers electric
    • G05B11/36Automatic controllers electric with provision for obtaining particular characteristics, e.g. proportional, integral, differential
    • G05B11/42Automatic controllers electric with provision for obtaining particular characteristics, e.g. proportional, integral, differential for obtaining a characteristic which is both proportional and time-dependent, e.g. P.I., P.I.D.

Abstract

PURPOSE:To suppress an overshoot, etc. and to improve the control performance of a digital controller, by connecting successively an integrator and a limiter to the output side of a velocity type PID control arithmetic part and then providing an integrator initial value control part between the control output terminal obtained from the limiter and the integrator. CONSTITUTION:A velocity type PID control arithmetic part 8 receives the input of the target value j(k) and controlled variable c(k) and calculates a differential DELTAu(k) of controlled variable u(k). Then an integrator 9 adds the differential DELTAu(k) calculated at the part 8 to the (k-1)-th controlled variable u(k-1), i.e. the initial value of the integrator. Thus the manipulated valuable u(k) is calculated. A limiter 7 feeds the manipulated valuable u(k) and decides the control output uL(k) to give an input to an integrator initial value control part 10. In this case, the integral initial value is substituted within the k-th control period so that the value u(k) of the integrator is equal to the operation output.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明はディジタル制御装置LK係り、・特にPID制
御演算を行い、そのPID制御演算の結果にリミットを
かけるディジタル制御装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a digital control device LK, and particularly to a digital control device that performs PID control calculations and places limits on the results of the PID control calculations.

〔発明の技術的背景〕[Technical background of the invention]

11EI図に基づ**来Oデ(ジタル制御装置の構成を
説明する。減算器lは目標値j (k)と制御量管(k
)を入力し、偏差・伽)をPID制御演算部2に出力す
る。PID制御演算部2は偏差・k)を入力し、操作量
U (k)をす々、り7に出力する。こ辷で、PID制
御演算部2は積分II3と微分量4と加ll14!!5
と乗算器6とから構成畜れている。積分器3は偏差・伽
)を入力し、偏差m−)O積分結果を加算器5へ出力す
る。微分量4は偏−・伽)を入力し、偏差−0c)O微
分結果を加算器暴へ出力すゐ。加算器5は偏差・0IC
)、積分結果および微分結果を入力し、ζ−れらの加算
を行い、その加算結果を乗算器6に出力する。乗wag
は加jl#釆を入力し、この加算結果に比例rインを乗
じ、操作量U伽)をり(Vり7に出力する。り電、タフ
は操作量U(ト)を入力し、操作出力UL伽)を制御対
象に出力する。
The configuration of the digital control device will be explained based on Figure 11EI.The subtracter l is used to calculate the target value j (k)
) is inputted, and the deviation ス) is outputted to the PID control calculation section 2. The PID control calculation unit 2 inputs the deviation/k) and immediately outputs the manipulated variable U (k) to the controller 7. At this point, the PID control calculation unit 2 adds the integral II3 and the differential amount 4! ! 5
and a multiplier 6. The integrator 3 inputs the deviation m-)O and outputs the integration result to the adder 5. For the differential quantity 4, input the deviation -0c) and output the differential result to the adder. Adder 5 is the deviation/0IC
), integration results and differentiation results are input, ζ-are added, and the addition result is output to the multiplier 6. square wag
Inputs the addition jl# button, multiplies this addition result by the proportional rin, and outputs the manipulated variable U 佽) to ri(Vri7). output UL) to the controlled object.

次に、上記のように構成され友従来のディジタル制御装
置の動作を説−する、従来のディジタル制御装置では各
制御周゛期毎に以下に述べる一連の動作を行っているが
、ここでak=1 、2.3・・・なるに番目の制御周
期での一連の動作について説明する。減算器1は目標値
j伽)と、制御対象の状態を示す制御量C伽)を人力し
、次式(1)で示す如く、偏差・伽)の演算を行う。
Next, we will explain the operation of the conventional digital control device configured as described above.In the conventional digital control device, a series of operations described below are performed for each control cycle. =1, 2.3... A series of operations in the control cycle will be explained. The subtracter 1 manually inputs the target value j) and the control amount C) indicating the state of the controlled object, and calculates the deviation C) as shown in the following equation (1).

・へ)=j伽)−cへ)’  ”    −・−・・・
・−、(1)次に、 PID制御演算部2では、積分器
3、微分器4、加算器5、乗算器6を用い、次式(2)
K示すように偏差・(k)より操作量U (k)を演算
している。
・to)=j伽)−cto)' ” −・−・・・・
-, (1) Next, the PID control calculation unit 2 uses an integrator 3, a differentiator 4, an adder 5, and a multiplier 6, and calculates the following equation (2).
As shown in K, the manipulated variable U (k) is calculated from the deviation (k).

UQc)= Ke(*(k)十−[−(e (0)十m
 (1) 十・・−・−・i  2 +−(・(k−1)十〇(k))〕 @(k)−・(k−1) 十74      、t)  −−−−−°−−−−−
=−=(2)但し、上式(2)において、Keは比例r
イン、!iは積分時間、Tdは微分時間、Δtは制@局
期をそれぞれ示している。
UQc) = Ke(*(k) 10-[-(e (0) 10m
(1) 10・・・−・i 2 +−(・(k−1) 10(k))] @(k)−・(k−1) 174 , t) −−−−−° ------
=-=(2) However, in the above formula (2), Ke is the proportional r
in,! i represents integration time, Td represents differential time, and Δt represents control period.

台形公式にて近似演算している。また、微分器4微分を
近似演算している。加算器5は偏差・Oc)と、積分結
果と黴分結釆の加算を行い、乗算器6ではこの加算結果
に比f1ダインに6を乗じている。
Approximate calculation is performed using the trapezoidal formula. Further, the 4-differentiator differential is approximated. The adder 5 adds the deviation (Oc), the integration result, and the molding result, and the multiplier 6 multiplies the addition result by the ratio f1 dyne by 6.

次に1乗I@so出方である操作量U伽)は、リミッタ
7に人力され、下式(3)K示すような上・下限OvZ
ットがかけられ、制御出方ULOc)として制御対象(
図示せず)へ出力される・ 但し、ζζで一1Xは操作量味)の上限値、υml。
Next, the first power I@so output (operated amount U) is manually input to the limiter 7, and the upper and lower limits OvZ as shown in the following formula (3)
The control target (ULOc) is
(not shown); however, ζζ - 1X is the upper limit of the manipulated variable), υml.

は操作量U伽)の下限値である。is the lower limit value of the manipulated variable (U).

以上が1制御周期内での従来のディジタル制御装置の動
作である。従来0デイジタル制御装置は以上述べ九一連
の動作を制御周期毎に行い、制御量C伽)がVAg値j
伽)k−散するよう制御対象を制御している。
The above is the operation of the conventional digital control device within one control cycle. The conventional digital control device performs the nine series of operations described above in each control cycle, and the control amount C) is equal to the VAg value j.
佽) The controlled object is controlled so that k-disperses.

〔背景技W;tO問題点〕[Background technique W; tO problems]

しかしながら、上記従来装置においては、仮に目標値j
伽)が大きくステツブ状に増加したとすると、偏差・(
k)が増加し、従りて偏差・伽)K PID制御演算を
施した結果の操作量U伽)も増加し、遂にはりiq夕の
上限値Ufn□を超えて増加し続ける。
However, in the above conventional device, if the target value j
If 伽) increases in a large and step-like manner, then the deviation ・(
k) increases, and accordingly, the deviation (k) K (operated amount U, which is the result of PID control calculation) also increases, and finally exceeds the upper limit value Ufn□ of iq and continues to increase.

このとき、制御対象へ出力される操作出力υLOc)の
信号値はリミッタ7の働きKよりU工axtでしか増加
しないため、操作量U伽)の値が充分制御対象に反映さ
れず、偏差・(k)が残シ続けて積分器3の積分値が過
大になる。この結果、ようやく制御量の(転)が目標値
j伽)を上回り、偏差・□C)が負の値となりても積分
41#3の積分値が過大な正値となっているため、すぐ
Kは操作量U (k)および操作出力υL(転)は負値
、即ち減少指示の信号値とはならず、しばらくの間は増
加指示の信号値となる。従って、従来のディジタル制御
装置では第2図に示すように1目標値j Oc)の大き
なステリグ状変化に対し、制御量@伽)はオーパージ為
−トの大きな振動性の応答をし、目標値j Oc)に速
やかに収束ができない。
At this time, the signal value of the manipulated output υLOc) output to the controlled object increases only by U axt than the action K of the limiter 7, so the value of the manipulated variable U) is not sufficiently reflected in the controlled object, resulting in deviation and (k) continues to remain, and the integral value of the integrator 3 becomes excessive. As a result, even though the (turn) of the controlled variable finally exceeds the target value j) and the deviation □C) becomes a negative value, the integral value of integral 41#3 is an excessively positive value, so it is immediately K is the manipulated variable U (k) and the manipulated output υL (k) is a negative value, that is, the signal value does not indicate a decrease instruction, but remains a signal value indicating an increase instruction for a while. Therefore, in the conventional digital control device, as shown in Fig. 2, for a large sterig-like change in the target value jOc), the controlled variable @ス) responds with a large oscillatory response due to the opacity, and the target value j Oc) cannot be quickly converged.

壇た、目標値j (k)が急に減少した場合にはアンダ
ーシ暴−トの大きな振動性の応答をし、制御量C伽)は
目標値j伽)に速やかに収束ができない等の問題点が6
り九。
In addition, if the target value j (k) suddenly decreases, there will be a large oscillatory response with undersheath, and the control amount C) will not be able to quickly converge to the target value j). 6 points
Riku.

〔発明の目的〕[Purpose of the invention]

本発明は以上O1:LK鑑みなされたもので、すtツタ
がTo−)ても、制御量@(転)が目標値J(k)K対
してオーパージ為−トの少なく、非振動性で連中がな収
束をするディジタル制御装置を提供することを目的とす
る。
The present invention has been made in view of the above O1:LK, and even if the speed is To-), the controlled variable @ (rotation) has less overflow with respect to the target value J(k)K and is non-oscillatory. It is an object of the present invention to provide a digital control device that achieves continuous convergence.

〔発明のIIEIり この目的を達成するため、本発明は、速度形PID制御
演算−の出方側に履次積分器およびすiツタを従続接続
し、リミッタよシ制御出力を得ると共K、制御出力端と
積分器間K (k+1 )番目の積分器初期値をkil
mの制御周期の操作出力で置換える積分器初期値111
1Bを設けるととKよシ、オーパージ畠−ト等を抑制し
制御性を向上させたことを特徴とする。
[IIII] In order to achieve this object, the present invention connects a sequential integrator and an integrator in series on the output side of a speed-type PID control calculation, and obtains a control output from a limiter. K, the initial value of the K (k+1)th integrator between the control output terminal and the integrator.
Integrator initial value 111 to be replaced with the operation output of control period m
A feature of the present invention is that the provision of 1B suppresses overflow, overflow, etc., and improves controllability.

〔発明の実施例〕[Embodiments of the invention]

以下に本発@〇−実−例を第3図を用いて説明する。速
度形pxo*j1部8は目標値jへ)および制御量J 
OC)を入力し、操作量の差分ΔU (k)を積分器9
に出力する。積分器9は操作量の差分Δυ伽)を入力し
、操作量U k)をリミ、り7に出力する。リミツタ7
ti操作量U伽)を人力し、操作出力ULへ)を制御対
象および積分器初期値調整部10に出力する。
An example of this invention will be explained below using FIG. 3. speed type pxo*j1 part 8 to target value j) and control amount J
OC), and the difference in the manipulated variable ΔU (k) is input to the integrator 9.
Output to. The integrator 9 inputs the manipulated variable difference Δυ) and outputs the manipulated variable Uk) to the limiter 7. Limituta 7
ti manipulated variable U 佽) is input manually, and the manipulated output UL) is outputted to the controlled object and the integrator initial value adjustment section 10.

積分器初期値調整部10は操作出力UL(k)を入力し
、操作出力υLへ)を積分器9の積分初期値と置換える
The integrator initial value adjustment unit 10 inputs the manipulated output UL(k) and replaces the manipulated output υL) with the initial integration value of the integrator 9.

次に゛、第3図に示した本発明の一実施fIIの動作を
説明する。本実施例では従来のディジタル制御装置と同
様、各制御周期毎に一連の動作を行い、この一連の動作
を繰返すことKよシ制御対象を制御している。ここでは
、従来例と同様に11目の制御周期での一連の動作につ
いて説明する。
Next, the operation of the embodiment fII of the present invention shown in FIG. 3 will be explained. In this embodiment, like the conventional digital control device, a series of operations are performed for each control period, and the object to be controlled is controlled by repeating this series of operations. Here, a series of operations in the 11th control cycle will be described as in the conventional example.

先ず、速度形PID制御演j1部8は目標値j伽)、制
御量C伽)を入力し、操作量U (k)の差分#伽)を
算出する速度形PID制御演算を行っている。以下にそ
の速[形PID制御演算について説明する。操作量U 
(k)の差分ΔU (k)は次式(4)で示される。
First, the speed-type PID control calculation unit 8 inputs the target value j) and the control amount C), and performs speed-type PID control calculation to calculate the difference #k) of the manipulated variable U (k). The speed PID control calculation will be explained below. Operation amount U
The difference ΔU (k) in (k) is expressed by the following equation (4).

ΔU(k)−U(k)−U (k−1)      ・
・・・・・・・・・・・・・・(4)ここで、上式(4
)に操作量U伽)を示す(2)式を用いると(4)式は
次のように変形できる。
ΔU(k)−U(k)−U(k−1) ・
・・・・・・・・・・・・・・・(4) Here, the above formula (4
) can be transformed into the following equation by using equation (2), which indicates the manipulated variable U 佽).

ΔU (k)か〔(・(k)−一(k−1))・・・・
・・・・・・・・(5) (5)式において、偏差・伽)を示す(1)式を用い、
更Kjoc)=j(k−1)−j(k−2)と仮定し、
制御r(に定義し直すと(5)式は次のように表わせる
ΔU (k) or [(・(k)-1(k-1))...
・・・・・・・・・(5) In equation (5), using equation (1) showing the deviation
Assume that Kjoc)=j(k-1)-j(k-2),
When redefining the control r(), equation (5) can be expressed as follows.

ΔU 0c)=KP(c(k−1)−e伽))+に、 
(j(k)−e伽)〕十Ko(2@(k−1)−@(h
−2)−e(k))・・・・・・・・・・・・(句 この(6)式で示される演算が速度形PID制御演算で
ある。結局、速度形PID制御演算部8では(6)式で
示される速度形PID制御演算を行い、操作量U(k)
の差分ΔU(k)を算出している。次に1積分器9では
積分器初期値であるに一1瞥目の制御周期の操作量U(
k−1)K:、速度形PID制御演算部8で算出された
操作量U (k)の差分ΔU (k)を加算し、操作量
U (k)を算出している。即ち、積分器9では次式(
7)の演算を行っている。
ΔU 0c)=KP(c(k-1)-eス))+,
(j(k)−e传)]tenKo(2@(k−1)−@(h
-2)-e(k)) (phrase) The calculation shown by equation (6) is the speed-type PID control calculation.In the end, the speed-type PID control calculation unit 8 Now, perform the velocity type PID control calculation shown by equation (6), and calculate the manipulated variable U(k)
The difference ΔU(k) is calculated. Next, in the first integrator 9, the operation amount U(
k-1) K: The difference ΔU (k) between the manipulated variables U (k) calculated by the speed type PID control calculation section 8 is added to calculate the manipulated variable U (k). That is, the integrator 9 uses the following equation (
7) is being calculated.

U伽)=Δυ斡)+U(k−1)      ・・・・
・・・・・・・・(7)次に、リミ、り7に操作量U伽
)を入力し、従来のy’イノタル制御装置と同様、(3
)式で示される通り制御出力U 、<k)を決定し出力
している0次に、本実施例の特徴である積分器初期値の
置換えについて説明する。k+1番目の制御周期におけ
る操作量U(k+1)は(7)式を用いる次式(8)の
ようになる。
U 伽)=Δυ斡)+U(k−1)・・・・
・・・・・・・・・(7) Next, input the manipulated variable U 佽) into limit and ri7, and as with the conventional y' innotal control device, (3
) Determining and outputting the control output U, <k) as shown in the equation 0. Next, the replacement of the integrator initial value, which is a feature of this embodiment, will be explained. The manipulated variable U(k+1) in the k+1st control period is expressed as the following equation (8) using equation (7).

U(k+1)=Δu(k+i)+U[有])  ・・・
・・・・・・・・・(8)積分器初期値調整部10は(
8)式において積分器初期値U (k)が操作出力UL
軸)になるように11目のfiIIJ御周期内に積分値
初期値0Itsえを行っている。
U (k + 1) = Δu (k + i) + U [exist]) ...
(8) The integrator initial value adjustment section 10 (
In equation 8), the integrator initial value U (k) is the operation output UL
The initial value of the integral value is set to 0Its within the 11th fiIIJ control period so that the initial value becomes 0Its.

即ち、k+111目の制御周期での操作量U(k+1 
)は結局次式のようになる。
That is, the manipulated variable U(k+1
) becomes as follows.

υ(k+1)=ΔU(k+1)+UL伽)   ・・・
・・・・・・・・・(9)本実施例では以上説明した一
連の動作を制御周期毎に行い制御量C伽)が目標値jへ
)K一致するよう制御対象を制御している。この場合、
積分器初期値はいかなる場合にもIJ ミツタフの制限
値Um!またはU。i、を超えることはない。即ち、目
標値jへ)の急変時においても積分値が過大または過小
となることがなく、制御量噛伽)が目標値j (k)に
対してオーバーシェードまたはアン〆−シェートが少な
く非振動性で応答速度の速い収束をすることが可能とな
る。目標値j伽)がステ、グ状に大きく増加した場合に
ついては第4図に示す通りである。
υ (k+1) = ΔU (k+1) + UL)...
(9) In this embodiment, the series of operations explained above is performed every control cycle to control the controlled object so that the controlled amount C) matches the target value j). . in this case,
In any case, the integrator initial value is IJ Mitsutav's limit value Um! Or U. It never exceeds i. In other words, even when there is a sudden change in the target value j), the integral value does not become too large or too small, and the controlled variable (k) is less likely to overshade or unshade with respect to the target value j (k), resulting in non-vibration. This makes it possible to converge with a fast response speed. The case where the target value j) greatly increases in a step-like manner is as shown in FIG.

また、速度形PID制御演算を用いているため、積分器
9の出力が即操作量υ(唖となっており、積分器初期値
を操作出力ULOc)で置換えるだけで容易に制御性の
改善が可能となっている。
In addition, since speed-type PID control calculations are used, the output of the integrator 9 is an immediate manipulated variable υ (instant), and controllability can be easily improved by simply replacing the integrator initial value with the manipulated output ULOc. is possible.

〔発明の効果〕〔Effect of the invention〕

以上述べたように1本発明によれば、制御量C(k)は
目標値J Oc)に対してオーバーシェードまた社アン
ダーシーートが少なく、非振動性で速やかな収束をする
ディジタル制御装置が得られる。
As described above, according to the present invention, the control amount C(k) has less overshading and undersheeting with respect to the target value JOc), and there is a digital control device that is non-oscillatory and quickly converges. can get.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のディジタル制御装置を示すブロック図、
第2図は従来のディジタル制御装置のス′テッグ応答図
、第3図は本発明の一実施例を示すプロ、り図、菖4図
は本発明の一実施例のステ。 !応答図である。 1・・・減li器、2・・・PID制御演算部、3,9
・・・積分器、4・・・微分器、5・・・加算器、6・
・・乗算器、7・・・9iツタ、8・・・速度形PID
制御演算部、lO・・・積分器初期値調整部。 (7317)代理人 弁理士 則 近 憲 佑(ほか1
名)
FIG. 1 is a block diagram showing a conventional digital control device.
Fig. 2 is a step response diagram of a conventional digital control device, Fig. 3 is a step diagram showing an embodiment of the present invention, and Fig. 4 is a step diagram of an embodiment of the present invention. ! It is a response diagram. 1... Li reducer, 2... PID control calculation unit, 3, 9
... Integrator, 4... Differentiator, 5... Adder, 6.
・・・Multiplier, 7...9i ivy, 8...speed type PID
Control calculation unit, lO...integrator initial value adjustment unit. (7317) Agent Patent Attorney Noriyuki Chika (and 1 others)
given name)

Claims (1)

【特許請求の範囲】[Claims] 目標値と制御量とを入力して速度形PID演算を行い操
作量の差分を出力する演算部と、前記操作量の差分を入
力して積分を行い、操作量を出力する積分器と、前記操
作量を入力しリミットをかけ操作出力として出力するリ
ミッタと、前記操作出力を入力し積分器に出力する積分
器初期値調l1mとを備え、この積分器初期値M警部は
、積分器Kk+1@目の制御周期の積分器初期値をki
11目の制御周期の操作出力で置換えることを特徴とす
るrイジタル制御装置。
an arithmetic unit that inputs a target value and a controlled variable, performs a speed type PID calculation, and outputs a difference in manipulated variables; an integrator that inputs the difference in manipulated variables, performs integration, and outputs a manipulated variable; The integrator initial value M is equipped with a limiter that inputs a manipulated variable, applies a limit, and outputs it as a manipulated output, and an integrator initial value adjustment l1m that inputs the manipulated output and outputs it to an integrator. The initial value of the integrator for the eye control period is ki
A digital control device characterized in that the operation output of the 11th control cycle is substituted.
JP2681482A 1982-02-23 1982-02-23 Digital controller Pending JPS58144907A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2681482A JPS58144907A (en) 1982-02-23 1982-02-23 Digital controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2681482A JPS58144907A (en) 1982-02-23 1982-02-23 Digital controller

Publications (1)

Publication Number Publication Date
JPS58144907A true JPS58144907A (en) 1983-08-29

Family

ID=12203748

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2681482A Pending JPS58144907A (en) 1982-02-23 1982-02-23 Digital controller

Country Status (1)

Country Link
JP (1) JPS58144907A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61210401A (en) * 1985-03-15 1986-09-18 Hitachi Ltd Process control device
EP0362801A2 (en) * 1988-10-05 1990-04-11 Kabushiki Kaisha Toshiba Digital control system
JPH0474201A (en) * 1990-07-16 1992-03-09 Shimadzu Corp Process controller

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61210401A (en) * 1985-03-15 1986-09-18 Hitachi Ltd Process control device
EP0362801A2 (en) * 1988-10-05 1990-04-11 Kabushiki Kaisha Toshiba Digital control system
JPH0474201A (en) * 1990-07-16 1992-03-09 Shimadzu Corp Process controller

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