JPS62287637A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enable a semiconductor wafer to be screened as it is by means of providing an input pad for commanding test mode setting. CONSTITUTION:A power supply 14 is connected to a power supply pad 11 by mounting a semiconductor wafer 12 on an electrode plate 13. When a pad 15 for commanding test mode setting is impressed with a negative voltage using a jig 16, a transistor 171 on a test mode throwing circuit 17 is turned on. Then, the level of an output signal line 172 from said circuit 17 is lowered to set up a burn-in mode; an input.output processing circuit 19 is actuated; a clock signal is transmitted by an oscillating circuit 21 to be inputted in an inner circuit (a). Thus, respective clips are screened before they are packaged.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Industrial Field of Application] This invention is directed to 1. Particularly, a method for manufacturing a semiconductor device that allows screening (burn-in) to be performed in the wafer state in the manufacturing process of semiconductor circuit devices. The present invention relates to integrated circuit devices.

[Prior Art] Screening (commonly known as burn-in), which tests semiconductor integrated circuits, is performed after the assembly process of semiconductor chips is completed.
Generally, the device is sealed in a package and then mounted on a printed circuit board or the like. For example, JP-A-55-1
As described in the i0067 publication, a semiconductor device is also configured to be suitable for executing such a test. In this case, burn-in is performed by using various external components to set the semiconductor circuit in a state similar to that in actual operation.

However, if this is done, there will be a limit to the quantity of verhein, and the cost of inspection and the cost of equipment for this inspection will increase.

[Problems to be Solved by the Invention] This invention has been made in view of the above points, and it is possible to effectively burn-in a semiconductor circuit device in a wafer state before it is separated into chips and further packaged. It is an object of the present invention to provide a semiconductor integrated circuit device that can perform burn-in efficiently in a state closer to actual operation.

[Means for Solving the Problems] That is, the semiconductor integrated circuit device according to the present invention is provided with an input band for a test mode setting command, and a test mode is set by a voltage specified to this pad. When a command is input, a test mode input circuit is set that generates a test mode command signal. Then, in the test mode setting state, a power supply is set to the integrated circuit section, and an operation command is given to the clock signal generation section and further to the output processing means, so that the internal circuit to which the power supply is set is put into test operation. It is something that

[Operation] In the semiconductor integrated circuit device as described above, a jig is used to supply a voltage signal for setting a test mode specified to the input pad in a wafer state before separation into chip states. By doing so, the semiconductor circuits formed on each chip can be inspected on a wafer-by-wafer basis, and screening after mounting can be omitted.

[Embodiments of the invention] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a circuit of a portion corresponding to one of the chips set to semiconductor uni/%, and includes a power supply pad 11 to which a power supply voltage is applied. This pad 11 is set, for example, on the back surface of the semiconductor wafer 12, and is connected to the power source 14 by being placed on the electrode plate 13 during burn-in, as shown in FIG. be.

In FIG. 2, (A) shows a semiconductor wafer 12, which includes a plurality of chips 121, 122,
..., and this semiconductor wafer 12
It is placed on the electrode plate 13 as shown in FIG. 2B, and an electrode film constituting the power supply pad 11 is formed on the back surface of the wafer 112.

On the front side of the semiconductor wafer 12, a pad 15 for test mode input is formed corresponding to each chip, and this pad 15 is provided with the electrode plate 13.
An electrode probe 161 is connected to the jig 1B, which is set to face the semiconductor urchin/\12 placed above.

That is, on this test mode setting pad 15,
When setting the test mode, for example, a special negative voltage is applied, and when a negative voltage is applied to this pad 15, the transistor 171 of the test mode input circuit 17
is turned on, and the power supply pad 11
Power is set to be supplied to the semiconductor circuit section 18 connected to the semiconductor circuit section 18 . This circuit g18 is a circuit portion necessary for the actual operation of this semiconductor integrated circuit.

In the test mode input circuit 17, the output signal line 172 is pulled up by a resistor 183, so that a high level signal is output to the output signal line 172 when the transistor 171 is in an off state. and,
By applying a negative voltage to the pad 15 and turning on the transistor 171, a low-level test mode (burn-in mode) setting command signal is output to the signal line L72.

The output signal from the output signal line 172 is supplied to the gate of the P-type MOS transistor 191 constituting the input/output processing circuit 19. When the signal on the signal line 171 becomes low level, the transistor 161 is turned on. As a result, the signal input pad 20 is pulled up. and,
This pad 20 is used to perform signal input/output processing in the internal circuit section of the semiconductor.

Further, the signal from the output signal line 172 is transmitted to the oscillation circuit 2.
1. This oscillation circuit 21 includes a NOR gate 21
1. Inverter 212, three-state inverter 21
3, resistance 214.215, yong! When the signal line 172 becomes low level, a clock signal is oscillated, and the clock signal is supplied to the clock input pad 22. This clock signal is then supplied to the semiconductor internal circuit section as an operating clock signal.

That is, in the semiconductor integrated circuit device configured as described above, the wafer 12 is subjected to the burraining process before being separated into chips, and the semiconductor wafer 12 is placed on the electrode plate 13 as shown in FIG. By placing it on top, the power supply pad 11 is connected to the power supply. In this state, when a negative voltage is applied to the test mode setting command pad 15 using an appropriate jig 16, the transistor 171 of the test mode input circuit 17 is turned on. Then, the output signal line 172 from the test mode input circuit 17 becomes low level, and the burn-in mode is set, the input/output processing circuit 19 becomes operational, the oscillation circuit 2 generates a clock signal, and the oscillation A clock signal is now input to the internal circuit.

That is, the power supply voltage is applied from the back side of the semiconductor wafer 12 in the state shown in FIG. By supplying the signal to each chip via the chip, the conditions necessary for burn-in the chip, such as pulling up input terminals and internally generating an operating clock signal, can be automatically executed.

Before each chip is packaged or when it is in the wafer state, a screening process generally called dynamic burn-in that closely resembles actual operation is performed.

[Effects of the Invention] As described above, in the semiconductor integrated circuit device according to the present invention, the operating state of each chip can be inspected in a state close to actual operation in the state of the semiconductor wafer before it is made into chips and packaged. This makes it possible to sufficiently simplify the semiconductor manufacturing process, especially the screening process. In particular, the above-mentioned screening can be easily performed up to a sufficiently large number of chips, and a great effect is exhibited in improving the reliability of this type of semiconductor integrated circuit device.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a circuit configuration diagram of a burn-in control section showing one chip part of a semiconductor integrated circuit device according to an embodiment of the present invention, and (A) of FIG. FIG. 2B is a diagram showing a semiconductor wafer undergoing burn-in, and is a side view illustrating the setting state of the wafer during burn-in. 11... Power supply pad, 12... Semiconductor wafer, 1
3... Electrode plate, 14... Power supply, 15... Pad for test mode command, 16... Jig, 17... Test mode input circuit, 18... Semiconductor circuit section, 19...・
・Input/output processing circuit, 20...Signal input pad, 21・
...Oscillation circuit.

Claims (1)

[Claims] A mode setting input pad for giving a voltage signal specified when setting a test mode, and a test mode command signal being generated with the specified voltage signal being applied to the pad. an internal integrated circuit section that sets the power supply voltage in the test mode setting state of this test mode entry circuit; and operation command means including an input/output processing means to be set, and when a voltage signal specifying a specified test mode is applied to the pad, and the test mode input circuit is in a test mode setting command state, the internal integrated circuit 1. A semiconductor integrated circuit device, wherein an inspection of the operating state of a component is performed.