JPS6228639B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a four-wire time division digital communication device.

Although time-division digital communication devices have an excellent feature of being able to accommodate a large number of communications by multiplexing communication channels, they have problems as described below.

A first conventional example will be explained using FIGS. 5 to 7. This conventional device has subscriber circuits 1, 2, 3,
4, a common line 30 and a control circuit 31. The control circuit 31 includes two decoders 32, 3
3. It consists of a control memory 34 and a counter 35 that performs counting at a constant period. Furthermore, the control memory 34
As shown in FIG. 6, there are two blocks 34-1,
Consisting of 34-2. Decoders 32 and 33 decode the outputs of memory blocks 34-1 and 34-2 and provide control signals to each subscriber circuit providing transmit and receive time slots. Now subscriber circuit 1
When performing two-way communication between subscriber circuits 1 and 4, there is only one common line 30 connecting subscriber circuits, so there are two communication time slots: one from subscriber circuit 1 to subscriber circuit 4, and one from subscriber circuit 4 to subscriber circuit 1. must be kept separate. In this case, as shown in FIG. 6, the cell of the control memory 34 that specifies a certain time slot contains the address #1 of the subscriber circuit 1 as the sender.
But if subscriber circuit address #4 is the recipient,
written. Also, #4 as sender to another cell to give one more time slot.
However, #1 is written as the recipient. FIG. 7 shows the configuration of the subscriber circuit used in this conventional example. This subscriber circuit consists of an interface section 10 accommodating a terminal, a transmitting NAND gate 36 connected to a common line 30, and a receiving NAND gate 37. Control terminals 38, 39 are each connected to one of the decoding outputs of decoders 32, 33 assigned to the subscriber circuit. Control signals are supplied to the control terminals 38 and 39 in different time slots to realize bidirectional communication. This first conventional example has a problem in that the multiplicity of bidirectional communication is only 1/2 of the multiplicity of the communication path.

Next, a conventional example in which the multiplicity of communication paths and the multiplicity of bidirectional communication can be made the same will be described. This second
A conventional example of this is shown in FIG. subscriber circuits 1, 2,
3 and 4 are mutually connected by two common lines 41 and 42. The control circuit 43 has four decoders 44, 45, 46, and 47.
45 outputs a transmission control signal and a reception control signal regarding the common line 41, and decoders 46 and 47 output a transmission control signal and a reception control signal regarding the common line 42. The outputs of these decoders are supplied to each subscriber circuit. In order to simplify the drawing, only the supply to the subscriber circuit 1 is shown in this figure. The control memory 48 in the control circuit 43 has four memory blocks 48-1, 48-2, 48-3, and 4.
8-4, and is read out periodically according to the operation of the counter 49. Memory block 4 in Figure 9
8-1 and 48-2 identify the sender and receiver of the common line 41, respectively, and the memory blocks 48-3 and
48-4 specify the sender and receiver of the common line 42, respectively. FIG. 9 shows a case where bidirectional communication is carried out between subscriber circuits 1 and 4 in a certain time slot. FIG. 10 shows a subscriber circuit in this conventional example. The transmitting NAND gate 51 and the receiving NAND gate 53 connect to the common line 41.
NAND gate 52 and receiving NAND gate 54 are connected to common line 42. Control terminals 55, 56,
57 and 58 are decoders 44, 45, and 4, respectively.
6 and 47, respectively. In this conventional example, two-way communication is possible in the same number as the multiplicity of the communication path consisting of the common lines 41 and 42, but control is required to identify the sender and receiver for each of the two common lines. The memory 48 requires twice the capacity of the control memory 35 of the first conventional example. Conversely, the number of output bits of each memory block gives the maximum number of subscriber circuits that can be accommodated, so if the capacity is the same as that of the control memory of the first conventional example, the number of subscriber circuits that can be accommodated is 1/ of the conventional example of 1
There is a problem that it becomes 2.

An object of the present invention is to provide a time-division digital communication device that accommodates a plurality of subscriber circuits, in which the multiplicity of bidirectional communication is made equal to the multiplicity of communication channels, and which can accommodate a larger number of subscriber circuits. It's about doing.

The time-sharing digital communication device of the present invention includes a first output circuit that outputs a digital signal at a logic level "1" in a non-communication state and a digital signal to be transmitted in a communication state; In the sending communication state, a second output circuit that sends out an inverted signal of the digital signal, a duplex subscriber circuit having one input circuit, and all the output terminals of the first output circuit are connected and the A first common line whose voltage logic level is the AND of the output logic levels of all the first output circuits and all the output terminals of the second output circuits are connected, and the voltage logic level is the logical product of the output logic levels of all the first output circuits. a second common line that is a logical product of output logic levels of two output circuits; and two input terminals connected to the first and second common lines, and the voltage logic level of the two input terminals is When the voltage logic level of only one of the two input terminals is "1", the voltage logic level "1" is output when both are "0", and the voltage logic level "0" is output when the voltage logic level of only one of the two input terminals is "1". a logic circuit that outputs a predetermined voltage logic level when both logic levels are "1"; a third common line that connects the output terminal of this logic circuit and all the input terminals of the input circuits of the subscriber circuit; and a control circuit that supplies a control signal that indicates a communication state and a non-communication state to each subscriber circuit, and each subscriber circuit is further distributed with the digital signal to be transmitted from the third common line. It is equipped with an exclusive OR circuit that inputs a digital signal and sends an output signal to the subscriber side.

Next, the present invention will be explained in detail with reference to the drawings.

In FIG. 1, which shows an embodiment of the present invention, the device of the present invention has subscriber circuits 1, 2, 3, and 4, and three common lines 5, 6, and 7 that commonly connect all these subscriber circuits. , first common line 5, second common line 6
The control circuit 31 includes a logic circuit 8 having NOR logic, which has two input terminals connected to the same line and an output terminal connected to the third common line 7 . The control circuit 31 used in this embodiment has the same configuration as the control circuit 31 shown in FIG. 5 used in the first conventional example.
The subscriber circuit described here is a digital voice communication device that converts a 2-wire signal from a subscriber into a 4-wire signal, limits the band, and performs analog-to-digital conversion to convert the resulting digital signal into a 4-wire signal. In a circuit that outputs to a divided communication channel, demodulates and reproduces a digital signal input from a time-divided communication channel into an analog signal, converts it into a two-wire signal, and sends it to a subscriber, or in a data communication device, the sending side subscriber Converts the data signal from the user terminal into a digital signal (for example, converts it into a digital signal by sampling) and outputs it to the time-division communication channel, and also converts the digital signal input from the time-division communication channel into the inverse of the above conversion. This refers to a circuit that is provided for each subscriber and inputs and outputs digital signals in a time-sharing manner, such as a circuit that performs digital signal processing, regenerates the data signal, and sends it to the receiving subscriber terminal device.

An example of the configuration of the subscriber circuit is shown in FIG. The subscriber circuit in this figure is an interface unit 1 that accommodates terminals.
0, transmitting NAND gate 1 which is the first output circuit
3. Transmission NAND gate 1 which is the second output circuit
4. Input circuit gate 15, inversion gate 1
2. It is composed of an exclusive OR circuit 11 and an OR circuit 16. Transmit NAND for all subscriber circuits
The outputs of the gates 13 and 14 are connected in common to a first common line 5 and a second common line 6, respectively, and are opened so that the voltage logic level of these common lines becomes the logical product of the output logic levels of all transmitting NAND gates. Connected by collector or tri-state. One input terminal of the gate 15 of all subscriber circuits is connected in common to the third common line 7.
The OR circuit 16 transmits the OR logic of the control signals supplied from the control terminals 17 and 18 to the NAND gate 13,
14 and gate 15. This control terminal 1
7 and 18 are connected to the control circuit 31 in the same way as the control terminals 38 and 39 of the subscriber circuit used in the conventional example shown in FIG. The transmitting NAND gate 13 sends the transmitting digital signal from the interface section 10 supplied via the inverting gate 12 to the common line 5, and the transmitting NAND gate 14 inverts the transmitting digital signal and inverts it to the common line 6. and send it. The exclusive OR circuit 11 inputs the transmitted digital signal and the digital signal on the common line 7 supplied via the gate 15, restores the transmitted digital signal of the other subscriber's circuit, and supplies it to the interface section 10. This restoration control will be described later.

Bidirectional communication between subscriber circuits 1 and 4 using the device of the invention will now be described.

First, we will explain how to provide communication time slots. FIG. 3 shows the configuration of the control memory 34 in the control circuit 31. This configuration is exactly the same as the configuration of the control memory 34 shown in FIG. The difference is that only one memory cell is used for one bidirectional communication. Addresses #1 and #4 of subscriber circuits 1 and 4 read out in a certain time slot are decoded by decoders 32 and 33, respectively, and sent to control terminal 17 of subscriber circuit 1.
A control signal is then supplied to the control terminal 18 of the subscriber circuit 4. Therefore, the transmission of both subscriber circuits 1 and 4
A control signal is supplied to the NAND gates 13, 14 and gate 15 via their respective OR circuits 16 to determine the communication state. As a result, subscriber circuit 1,
A digital signal is sent only from 4 to the common lines 5 and 6. The transmitting NAND gates 13 and 14 of subscriber circuits other than subscriber circuits 1 and 4 are in a non-communication state, that is, a transmission prohibited state in this time slot, and their output logic becomes "1". Let A and B be the transmitted digital signals of the common line 5.
The voltage logic level of the common line 6 is the AND of the transmitted digital signal A.B, and the voltage logic level of the common line 6 is the AND of the inverted signal of the transmitted digital signal.
Therefore, the output of the OR circuit 8 is A・B+・=A
It becomes B. This output digital signal C is distributed to all the subscriber circuits via the common line 7, but only the gates 15 of the subscriber circuits 1 and 4 are in the communication state, that is, the receiving state, and the exclusive OR circuit 1 of each
1. In the subscriber circuit 1, the exclusive OR circuit 11 is supplied with the transmission digital signal A and the digital signal C.
The transmitted digital signal B (=CA) is restored and supplied to the interface section 10. Similarly, the transmitted digital signal A from the subscriber circuit 1 is restored in the subscriber circuit 4 in the same time slot.

FIG. 4 shows another example of the logic circuit used in the present invention. In FIG. 4, logic circuit 21 has two input terminals, each connected to common lines 5 and 6, and an output terminal connected to common line 7. The logic circuit 21 includes an exclusive OR circuit 22 and an inversion gate 2
3, the voltage logic levels A and B of the common line 5 and the voltage logic levels A and B of the common line 6 are input, and the voltage logic level C'=A, B,
(=AB) is output to the common line 7. This output logic level is the same as when logic circuit 8 is used, and bidirectional communication is possible using one time slot, as in the embodiment of FIG.

In addition, in these embodiments, the control memory 34
Although the decoders 32 and 33 are provided in the control circuit 31, they may be distributed and arranged in each subscriber circuit. Alternatively, each subscriber circuit has
The OR circuit 16 may be provided centrally in the control circuit 31, and the control circuit 31 and each subscriber circuit may be connected by one control line.

As explained above, according to the present invention, bidirectional communication is performed using one time slot, and the control memory is the same as the conventional example shown in FIG. There is no need to increase the capacity as in the example. Therefore, the communication path multiplicity and the bidirectional communication multiplicity can be made the same without increasing the capacity of the control memory, and more subscribers can be accommodated.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the present invention, and FIG.
The figure shows the subscriber circuit and control memory used in this embodiment, and FIG. 4 shows another example of the logic circuit used in this embodiment. 5 and 8 are diagrams showing conventional examples, FIGS. 6 and 9 show control memories used in these conventional examples, and FIGS. 7 and 10 show subscriber circuits used in the conventional examples. show. In the figure, 1, 2, 3, 4 are subscriber circuits,
5, 6, 7, 30, 41, 42 are common lines, 8, 1
1, 12, 13, 14, 15, 16, 22, 2
3, 36, 37, 51, 52, 53, 54 are logic gates, 10 is an interface section, 31, 43
is a control circuit, 32, 33, 44, 45, 46, 4
7 is a decoder, 34, 48 is a control memory, 35,
49 indicates a counter.

Claims (1)

[Scope of Claims] 1. A first output circuit that sends out a logic level "1" in a non-communication state and sends out a digital signal to be transmitted in a communication state; In this state, a plurality of subscriber circuits each having a second output circuit that sends out an inverted signal of the digital signal, and one input circuit, and all output terminals of the output circuits of the first output circuit are connected and the voltage thereof is A first common line whose logic level is the logical product of the output logic levels of all the first output circuits and all the output terminals of the second output circuits are connected, and the voltage logic level thereof is the logical product of the output logic levels of all the second output circuits. a second common line that is the logical product of the output logic levels of the output circuits; and two input terminals connected to the first and second common lines, and the voltage logic levels of the two input terminals are both the same. When the voltage logic level is "0", a voltage logic level "1" is output; when the voltage logic level of only one of the two input terminals is "1", a voltage logic level "0" is output; a logic circuit that outputs a predetermined voltage logic level when both levels are "1"; a third common line that connects the output terminal of this logic circuit and all the input terminals of the input circuits of the subscriber circuit; and a control circuit that supplies a control signal to each subscriber circuit to indicate a communication state and a non-communication state, and each subscriber circuit further receives the digital signal to be transmitted and the digital signal distributed from the third common line. 1. A time division digital communication device comprising an exclusive OR circuit that inputs a signal and sends an output signal to a subscriber side. 2. The time division digital communication device according to claim 1, wherein the predetermined voltage logic level outputted by the logic circuit is a logic level "1". 3. The time division digital communication device according to claim 1, wherein the predetermined voltage logic level outputted by the logic circuit is a logic level "0".