JPS6228618B2 - - Google Patents

Info

Publication number
JPS6228618B2
JPS6228618B2 JP56042063A JP4206381A JPS6228618B2 JP S6228618 B2 JPS6228618 B2 JP S6228618B2 JP 56042063 A JP56042063 A JP 56042063A JP 4206381 A JP4206381 A JP 4206381A JP S6228618 B2 JPS6228618 B2 JP S6228618B2
Authority
JP
Japan
Prior art keywords
circuit
timing
limiter amplifier
output
difference
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56042063A
Other languages
English (en)
Japanese (ja)
Other versions
JPS57155859A (en
Inventor
Kazuo Yamaguchi
Motohide Takahashi
Toshitaka Tsuda
Takafumi Nakajo
Yoichi Nagata
Tsutomu Kamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP56042063A priority Critical patent/JPS57155859A/ja
Publication of JPS57155859A publication Critical patent/JPS57155859A/ja
Publication of JPS6228618B2 publication Critical patent/JPS6228618B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP56042063A 1981-03-23 1981-03-23 Timing circuit Granted JPS57155859A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56042063A JPS57155859A (en) 1981-03-23 1981-03-23 Timing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56042063A JPS57155859A (en) 1981-03-23 1981-03-23 Timing circuit

Publications (2)

Publication Number Publication Date
JPS57155859A JPS57155859A (en) 1982-09-27
JPS6228618B2 true JPS6228618B2 (enrdf_load_stackoverflow) 1987-06-22

Family

ID=12625635

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56042063A Granted JPS57155859A (en) 1981-03-23 1981-03-23 Timing circuit

Country Status (1)

Country Link
JP (1) JPS57155859A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01123714U (enrdf_load_stackoverflow) * 1988-02-15 1989-08-23

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01123714U (enrdf_load_stackoverflow) * 1988-02-15 1989-08-23

Also Published As

Publication number Publication date
JPS57155859A (en) 1982-09-27

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