JPS62285462A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the dispersion of a resistance value and the disconnection of a poly Si resistance element by surrounding the whole or one part of the element by an insulating layer, through which H2 is not passed, and a semi- insulating poly Si layer. CONSTITUTION:Semi-insulating poly Si 12 containing O is deposited on an Si substrate 10 through a layer insulating film 11. Connecting holes 12a, 11a are bored, and a thin-film 1 as a poly Si resistance element is laminated. A mask is executed and the element film l and the semi-insulating layer 12 are etched, and the surface is coated with an SiN layer 13. According to the constitution, the SiN layer prevents the intrusion of H, the instability of a resistance value by H and trouble (disconnection, etc.,) to the increase of resistance by the thin-film are removed, thus acquiring the resistance element having reliability.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having a polycrystalline silicon resistance element. The semiconductor device of the present invention can be used, for example, as a semiconductor LSI for SRAM.

[Summary of the invention]

The present invention provides a semiconductor device having a polycrystalline silicon resistance element, including a semi-insulating polycrystalline silicon layer containing oxygen that is in contact with at least a portion of the polycrystalline silicon resistance element, and a layer that covers other parts of the polycrystalline silicon resistance element. By surrounding all or part of the polycrystalline silicon resistance element with a semi-insulating polycrystalline silicon layer and an insulating layer that does not allow hydrogen to pass through, This prevents variations in the resistance value caused by intrusion into the polycrystalline silicon resistance element, as well as the occurrence of inconveniences when the polycrystalline silicon resistance element is disconnected.

[Conventional technology]

Conventionally, in large-capacity SRAM (static RAM), the pull-up (Pu 11up) for the memory cell has been used.
) elements are generally made of polycrystalline silicon (PolyS
A resistor according to i) is used. Since this resistance element directly controls the magnitude of the current flowing through the memory cell during standby, it is necessary to set this resistance value large in order to reduce the power consumption of the memory.

In order to increase the resistance value of a polycrystalline silicon resistance element, it is necessary to set a large ratio of resistance length/resistance cross-sectional area. However, this measure cannot be adopted because the increase in the resistance length goes against the demand for miniaturization of the cell size. Furthermore, as a means of reducing the resistance cross-sectional area, reducing the resistance width and thinning the film thickness can be considered, but since the resistance width is limited in size by the minimum processing dimension, there is a limit to the reduction.

Further, there is a problem in that thinning the film leads to a decrease in reliability due to the intrusion of hydrogen. That is, since a material containing a large amount of hydrogen H is used when forming the plasma nitride layer during the process, hydrogen H is always in a state where it is easy to penetrate into the polycrystalline silicon, and as a result, the resistance value fluctuates. However, there is a problem that it is difficult to ensure stability due to the thin film of polycrystalline silicon, and thinning of polycrystalline silicon may further exacerbate this problem. Furthermore, when the film is made thinner, the resistor becomes more likely to be disconnected, which may lower the yield.

Regarding the problem of hydrogen intrusion, for example, as shown in FIG. A solution has also been proposed in which hydrogen is stacked, but this method cannot prevent hydrogen from entering through the contact hole 4 and penetrating into the polycrystalline silicon 1 through the glabella insulating film 2. In addition, in the figure, reference numeral 5 indicates a semiconductor substrate such as Si, 6 indicates an upper interlayer insulating film, and 7 indicates a wiring made of A1 etc., but since the adhesion between the semiconductor substrate 5 such as Si and the wiring N7 is not good, this This is also a problem.

In addition, SIPO3, which is oxygen-doped polycrystalline silicon, is formed by mixing nitrogen oxide gas during CVD of polycrystalline silicon, and this is used as a resistor to prevent hydrogen from entering. However, this method causes problems such as the resistance value becoming too high, resulting in cell failure, the controllability and reproducibility of the resistance value being reduced, and contact with the underlying layer becoming difficult.

In addition, a structure in which a polycrystalline silicon resistance element is surrounded by a silicon nitride layer of Si, N, and a structure in which a polycrystalline silicon resistance element and a Si x N4 layer are successively laminated on phosphosilicate glass PSG as the glabellar insulating film 2 are also considered. However, the former has the problem that leakage occurs at the interface between the polycrystalline silicon resistive element and the 5izN layer, resulting in a decrease in resistance, and the latter has the problem that phosphorus diffuses onto the substrate and This has the problem of damaging the characteristics of the upper N layer, P layer, etc. In the latter case, it is conceivable to interpose another layer between the substrate and the substrate in order to prevent the diffusion of phosphorus, but this would complicate the process, increase costs, and be impractical.

[Problem that the invention seeks to solve]

As described above, in the prior art, there is a risk that hydrogen H° may enter the polycrystalline silicon resistance element due to the plasma used during the manufacturing process and destabilize the resistance value.

In particular, when the film is made thinner in order to increase the resistance value, hydrogen penetration is promoted, and there is a risk that the risk of disconnection increases and the yield decreases. Also,
If polycrystalline silicon is doped with oxygen to prevent hydrogen from entering, there is a risk that the resistance value will become too high or that the reproducibility of the resistance value will be lost.

The purpose of the present invention is to prevent hydrogen from penetrating into a polycrystalline silicon resistance element, thereby making it possible to obtain a stable high resistance value, and also to prevent inconveniences such as a decrease in reliability due to occurrence of wire breakage when the film is made thinner. An object of the present invention is to provide a semiconductor device that can solve these problems.

[Means for solving problems]

In the semiconductor device of the present invention, a semi-insulating polycrystalline silicon layer containing oxygen that is in contact with at least a portion of the polycrystalline silicon resistance element and hydrogen coated on other parts of the polycrystalline silicon resistance element pass through. The structure includes an insulating layer that prevents With this semiconductor device, the above object can be achieved.

[For production]

That is, the present invention can be embodied using, for example, so-called 5IPO3 as semi-insulating polycrystalline silicon containing oxygen. In this case, the semiconductor device includes semiconductor substrate layers stacked sequentially on a semiconductor substrate such as silicon, and an interlayer It consists of an insulating film, an SIPO3 layer that is a semi-insulating film, a polycrystalline silicon resistance element, and an SiN layer that is an insulating layer that does not allow hydrogen to pass through. The polycrystalline silicon resistance element and the SiN layer may be sequentially stacked. According to this configuration, it is possible to eliminate inconveniences such as variations in resistance value caused by hydrogen entering into the polycrystalline silicon resistance element and reduction in reliability due to disconnection.

〔Example〕

Hereinafter, one embodiment of the semiconductor device of the present invention will be described in detail.

FIGS. 1(a) and 1(b) are configuration explanatory diagrams of an embodiment of a semiconductor device of the present invention, in which each layer is sequentially stacked on a semiconductor substrate 10 (not shown) made of silicon or the like. The semiconductor substrate 10 and the glabella insulating film (SiO
□) 11 and 5tpo forming a semi-insulating polycrystalline silicon layer
The s interlayer insulating film 12, the polycrystalline silicon resistance element 1, and the SiN layer which is an insulating layer that does not allow hydrogen to pass through (for example, LP-
5iN) From 13. Interlayer insulation film 11 and 5IPO3
The polycrystalline silicon resistance element 1 is located in the contact holes lla and 12a formed across the I'i insulating film 12.
and a 5iN (silicon nitride) insulating layer 13 are sequentially laminated. The adhesion (contact) between the substrate 10 made of Si and the polycrystalline silicon 1 is extremely good. SiN layer 13 sandwiching polycrystalline silicon resistance element 1 at upper and lower positions
The 5IPOS layer 12 functions to prevent hydrogen intrusion, and the Si
The N layer (insulating N) 13 prevents hydrogen from entering into the polycrystalline silicon resistance element 1 from the contact hole 11 and from above and from the sides, and the S TPO3 layer 12 prevents hydrogen from entering from below.
Prevents hydrogen from entering. Furthermore, in this example, the SI PO3 layer 12 is provided only directly under the region where the polycrystalline silicon resistance element 1 exists.

Absolutely! 13 does not necessarily need to be in direct contact with polycrystalline silicon resistance element 1 . The 5IPO8 layer 12 is in contact with the polycrystalline silicon resistive element. SIPO
31J12 is polycrystalline silicon doped with 02, and the amount of oxygen doped is adjusted to such an extent that 5IPO3 becomes semi-insulating (if completely doped, it becomes silicon dioxide). In the present invention, S I POS having various ranges of oxygen doping depending on desired characteristics can be used, but the doping amount is, for example, 2 to 45 atm%.
A range of is preferred. The amount of oxygen doped is more preferably 5 to 4'Oatm%. By doping polycrystalline silicon with oxygen, it not only becomes semi-insulating (approximately one order of magnitude higher in resistance), but also adsorbs hydrogen. It acts as a stopper to prevent intrusion.

Next, a process for manufacturing the semiconductor device shown in FIGS. 1(a) and 1(b) will be described based on process diagrams shown in FIGS. 2(a) to 2(e).

First, FIG. 2 (a) shows the step (first step) of laminating a 5IPO3 layer 12, and in this step, a 5T
POS layer 12 (500-1000 people) will make a deposit (
deposited).

FIG. 2(b) shows a contact hole forming step (second step). In this step, contact holes 11a and 12a for making contact with the semiconductor substrate 10 are formed across the interlayer insulating film 11 and the 5IPO3 layer 12. be done.

Figures 2(c) and 2(d) show polycrystalline silicon resistance element 1 (
500 persons) from the upper surface of the 5IPOS layer 12 to the contact holes lla and 12a by the CVD method (third step). The thickness of the polycrystalline silicon resistance element 1 is normally 1000 to 2000, but in this embodiment it is thinned to about 500. Even if the film is made thin like this, there is semi-insulating S I PO3 on the bottom surface.
Since the layers 12 are in contact, it is easy to maintain contact with the semiconductor substrate even if the thin film is disconnected. In other words, when the silicon resistance element 1 is disconnected, if the underlying layer is also insulating, the conductivity will be completely lost, but even if the resistance is high, the conductivity is maintained because the 5IPO3 layer is semi-insulating. Ru. Even if the S I PO3 has a high resistance (semi-insulating), the resistance will not become excessive because the disconnection is usually in a minute portion.

FIGS. 2(e) and 2(f) show an etching process (fourth process) in which the thin-film polycrystalline silicon resistance element 1 and the 5IPO3 layer 12 are cut using the same mask. S I PO only directly below the remaining area
Three layers 12 are left.

Finally, a step (fifth step) of laminating a SiN layer (for example, LP-3iN) 13 is performed, and the state after this step is as shown in FIGS. 1(a) and 1(b). That is, 5 IPOs
The entire top and side surfaces of the three layers, as well as the exposed glabella insulating film 1
A film having an effect of preventing hydrogen intrusion throughout 1, for example 5
iN1j13 is doped by CVD. In addition,
Any film other than SiN film (
For example, it may be 5tposSpsc, etc.).

FIG. 3 is an explanatory diagram of a second embodiment of the device of the present invention, in which the same parts as those in the previous embodiment are denoted by the same reference numerals and redundant explanation will be omitted. This embodiment differs from the previous embodiment in that a contact hole lla is formed in 11. In the above embodiment,
The contact hole was formed before depositing 5IPO3 in order to obtain a good contact with the polycrystalline silicon resistance element 1, but as in the second embodiment, the contact hole was formed between the substrate 1 and the S I POS 12. There is no problem in terms of adhesion, etc., even if the S I PO3 layer 12 and the polycrystalline silicon resistance element 1 are brought into contact with each other.
can be deposited continuously in the same furnace,
It has the advantage of improving manufacturing workability and reducing costs.

In each of the above embodiments, SiN is disposed above and on the sides of the polycrystalline silicon resistance element, and an Sr pos layer 1 is disposed below.
2, but the entire polycrystalline silicon resistance element is
It may be surrounded by a layer of IPO312.

In addition, as the insulating layer 13 that does not allow hydrogen to pass through, other materials that perform the same function, such as phosphosilicate glass PSG, can be used.
may also be used.

As described above, in the device of the above embodiment, since it is surrounded by the resistor SiN layer 13 made of polycrystalline silicon and the 5IPO5 layer 12, it is difficult for hydrogen to penetrate in the vertical direction, the side direction, and from the contact hole. Therefore, even when the film is made thinner, fluctuations in resistance due to hydrogen penetration are less likely to occur. Further, since the slightly conductive 5IPO 513 is in contact with the lower surface of the thin-film polycrystalline silicon resistance element 1, even if a disconnection occurs, no performance problem occurs. That is, a thin film polycrystalline silicon resistance element l
Even if a disconnection occurs, the gap caused by the disconnection is about 1/300, that is, about 100 people, so it is possible to flow current through the semi-insulating 5TPOS layer 12. Further, since the contact with the semiconductor substrate is directly made by the polycrystalline silicon 1 in the contact hole, there is no possibility of contact failure which tends to occur when 5IPO3 is used as a resistor.

〔Effect of the invention〕

As described above, according to the semiconductor manufacturing method of the present invention, hydrogen enters into the polycrystalline silicon resistance element from the periphery of the polycrystalline silicon resistance element, the contact hole, etc., and the resistance value of the polycrystalline silicon resistance element is changed. It is possible to stabilize the wire, prevent it from becoming a hindrance to high resistance due to thinning, and prevent reliability from decreasing due to wire breakage.

[Brief explanation of the drawing]

FIGS. 1(a) and (b) are a front sectional view and a side sectional view showing the configuration of an embodiment of the present invention, and FIGS. 2(a) to Cf)
is an explanatory diagram of an example of a process for manufacturing the device of the present invention, and (a
) is the CVD process of the insulating layer, (b) is the contact hole forming process, (c) and (d) is the C of the polycrystalline silicon resistance element.
VD process, (e) and (f) show etching process. Third
The figure is a configuration explanatory diagram of another embodiment of the present invention. FIG. 4 is an explanatory diagram of the configuration of a conventional example. 1... Polycrystalline silicon resistance element, 2...
・Interlayer insulation film, 3...5iNl! , 4...
...Contact hole, 5...Semiconductor substrate, 6
... Upper interlayer insulating film, 7 ... Wiring, 1
0...Semiconductor substrate, 11...Interlayer insulating film, lla, 12a...Contact hole, 1
2...Semi-insulating polycrystalline silicon layer (SIPO5
layer), 13...Insulating layer (S layer) that does not allow hydrogen to pass through
tN layer).

Claims (1)

[Claims] 1. Passing through an oxygen-containing semi-insulating polycrystalline silicon layer in contact with at least a portion of the polycrystalline silicon resistance element and hydrogen coated on other parts of the polycrystalline silicon resistance element. 1. A semiconductor device comprising: an insulating layer that does not cause