JPS62283667A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To accurately position a low density layer in a semiconductor layer by patterning a polycrystalline layer to form a gate electrode, and then silicifying it. CONSTITUTION:A field oxide film 12 is formed on a P<+> type single crystal silicon substrate 11, and a gate oxide film 13 is formed on an element region. Then, a polycrystalline silicon layer 14 is deposited on the whole surface, a phosphorus is thermally diffused, and a gate electrode is formed with a photoresist 15 as a mask. Then, with the photoresist 15 as a mask phosphorus is ion implanted to an element region, the photoresist 15 is separated, and heat treated. Then, P<-> type regions 16a, 16b are formed. Then, after a titanium layer 17 is then formed on the whole surface, it is annealed. Then, a titanium silicide layer 18 is formed. Thereafter, when it is treated with aqueous solution of H2O2, only unreacted layer 17 is removed. Then, with a gate eleotrode 19 as a mask arsenic ions are implanted to an element region, heat treated to form N<+> type regions 20a, 20b. Thus, a low density layer is formed at an accurate position to accelerate the operating speed.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Object of the Invention] (Field of Industrial Application) This invention provides an MO8 type field effect transistor (MOS).
Ff? ) relates to a method of manufacturing a semiconductor device for improving the vicinity of the drain region.

(Prior Art) In S FETs, as devices become smaller, the electric field near the drain region becomes stronger, and +77 occurs during hot conditions, which adversely affects device characteristics.

Therefore, in order to alleviate such electric field, LDD (Li
ghtly Doped Drain) technique is used.

This technique alleviates electric field concentration by forming a low concentration impurity diffusion layer in the drain region near the channel region and extending the depletion layer toward the drain region. A MOS FIT with such an LDD structure is generally r-t'[
Techniques for forming 810□ spacers on the polar sidewalls (e.g. IE
DM Technical Digest, 198
3, P 392-P 395, “OPTIMIZED
AND RELIABJLDD 5TRUCTUR
E F'OR1umNMO8FET 8ASF:J
D 0NSUBSTRATE CURRENT ANA
LYSIS) or an overetching technique using isotropic etching of the gate polysilicon layer (I
EEE TRANSACTIONSON ELECTR
ON DEVICE, VOL, ED-27, N
o, 8.

AUGUST I 980, Pi 359~P 1
367, “Dssign and Character
istics of the Lightly Dop
edDrain-3ourcs (LDD) In
5ulated Gate f'i*ld -Effe
ct Tran31stor”).

Also, IEDM Technical Digest,
1982-P718-P721, "AHA
LE' MICRON MOSFET [JSING
DOUBLE IMPLANTED LDD” and IEDM
Tschnical Digest, 1985-P4
8~P51, ”HOT-ELECTRON
DEGRADATIONIN SUBMICRON V
The MDs rr of the above-mentioned LDD structure is also described in LSll, etc.

By the way, as mentioned above, the LDD structure MOS FET
In this case, the electric field is relaxed by forming a low concentration impurity diffusion layer on the drain side. However, with the miniaturization of devices, it is necessary to increase the substrate concentration for reasons such as preventing trench-through between the source and drain regions and controlling the threshold value. For this reason, the depletion layer extending in the channel direction at the end of the drain region becomes small, causing field concentration. As a result, carriers are accelerated by this electric field concentration, and hot carriers are generated by impact ionization or the like. In particular, in the N-channel MO8FET, holes flow through the substrate and cause fluctuations in the substrate potential, whereas electrons are injected into the date insulating film and cause electron traps and generation of St-5in2 interface states. causing a change in value and a decrease in transconductance.

Furthermore, since the drain region is surrounded by a highly doped substrate, the depletion layer between the drain region and the substrate does not grow, increasing the capacitance. As a result, this capacitance becomes a parasitic capacitance, which impedes high-speed operation and operation of the element.

Furthermore, when an LDD structure is formed using overetching of the sidewalls of StO□ and the date polycrystalline silicon layer,
Processing controllability is poor, and manufacturing variations in dimensions of the low concentration layer (N single layer), etc., adversely affect device characteristics.

Furthermore, in all of the above-mentioned manufacturing methods, ions are implanted to form a single N layer using almost the final gate electrode as a mask, so there is very little overlap between the gate electrode and the single N layer. Particularly in today's world where process temperatures are being lowered, the N layer hardly spreads, and it can be said that there is no overlapping. If the amount of overlap is small in this way, electrons trapped in the oxide film during operation will increase the resistance value in that region, which is disadvantageous in terms of device reliability.

(Problems to be Solved by the Invention) As described above, in the conventional method of manufacturing a semiconductor device, the operating speed decreases due to an increase in parasitic capacitance.

Manufacturing variations in the low concentration layer have a negative effect on device characteristics, and the overlap between the gate and the low concentration layer decreases, resulting in a decrease in device reliability.

Therefore, the present invention is intended to eliminate the above-mentioned drawbacks. It is possible to form a low concentration layer in a self-aligned manner at an accurate position, and to reduce the parasitic capacitance between the drain region and the semiconductor substrate, thereby increasing the operating speed. It is an object of the present invention to provide a method for manufacturing a semiconductor device, which can form an LDD structure with good controllability and high reliability.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention forms a polycrystalline silicon layer on a semiconductor substrate via a y-tooxide film, and After the polycrystalline silicon layer is patterned, impurities are introduced into the semiconductor substrate using the mask used in this patterning or the patterned polycrystalline silicon layer as a mask. Then, the turned polycrystalline silicon layer is silicided, and impurities are reintroduced into the semiconductor substrate using the silicide layer formed by this siliciding as a mask.

(Function) In the above manufacturing process, after patterning the polycrystalline silicon layer to form a gate electrode, silicidation is performed to form a silicide layer on the surface of the gate electrode and form a date electrode. Taking advantage of this increase in size, one layer of P or one layer of N with low spacing is formed in a self-aligned manner between the high concentration NW drain region and the high concentration P medium-sized semiconductor substrate.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. First, as shown in Figure 1 (&), the impurity concentration is 2.
A field oxide gi 12 is formed on the surface of the XLOan OP type single crystal silicon substrate 11 by a selective oxidation method using a silicon nitride film.
A date oxide film 13 with a thickness of 150× is formed in the element region of the substrate 1 surrounded by . Next, a polycrystalline silicon layer 14 with a thickness of 5000 mm is deposited on the entire surface, and phosphorus is thermally diffused to lower the resistance value. Thereafter, reactive ion etching (RIE) is performed on the polycrystalline silicon layer 14 using the photoresist 15 as a mask to form a gate electrode.

Next, using the photorenost 15 as a mask (or the patterned polycrystalline silicon layer 14t-
(using a mask) to accelerate phosphorus in the element region at a voltage of 100 k@
V, dose amount 2×10 and acceleration voltage 20
Two-stage ion implantation is performed under the conditions of 0 kaV and a dose of 2×I 012 cm−2. After that, Photorenost 1
5 is peeled off and heat treated. As a result, Figure 1 (b
), P-type regions 16 m and 16 b whose peak concentration is lower than the impurity concentration of the semiconductor substrate 11 are formed.

Next, as shown in FIG. 1(C), a titanium layer 17 having a thickness of 100× is formed on the entire surface of the semiconductor substrate 11 by a sputtering method. After this, when annealing is performed at 750° C., silicidation occurs selectively only in the region where the polycrystalline silicon layer 14 and the titanium layer 17 are in contact, and the titanium silicide layer 18 as shown in FIG. is formed with a thickness of 100OX.

Thereafter, when the semiconductor substrate 1zf7icH2o2-based aqueous solution is treated, only the unreacted titanium layer 17 is selectively removed, as shown in FIG. 1 (-). At this time, since silicidation occurs at the interface between the polycrystalline silicon layer 14 and the titanium silicide layer 17, the ff-) electrode 19 is a combination of the unreacted polycrystalline silicon layer 14 and the titanium silicide layer 18.
The photoresist layer 15 used as a mask for phosphorus ion implantation when forming the P- regions 16m and 16b described above is also larger (wider).

Next, using the date electrode 19 as a mask, arsenic was applied to the element region at an acceleration voltage of 40 keV and a dose of 5×I.
Ion implantation is performed under the conditions of 015art 2. and,
A sauce as shown in FIG. 1(f) after heat treatment.

N+ regions 20a and 20b are formed as drain regions.

Next, a 5i02 film is formed on the entire surface as an irradiation film, and a JO2 film is formed on the source, drain region and r-t electrode.
After selectively removing the sto2 film to form a contact hole, aluminum wiring is provided to form an N-channel fiMO8) runnostar.

According to such a manufacturing method, the source and drain regions 2
Since it is provided in the surface region of the 0th and 20bt-P- regions 16a and 16b, the depletion layer extends substantially toward the semiconductor substrate lJ side, and the parasitic capacitance between the drain region 20b and the substrate 11 can be reduced. Therefore, the operating speed can be increased. Also,
The P- regions 6h and 16b are formed by ion-implanting phosphorus into the substrate 11 using 7 Otres/15 used as a mask when etching the polycrystalline silicon layer 14,
In addition, since the N medium region as the drain region 20b is also formed by ion-implanting arsenic using the r-to electrode 19 as a mask, the drain region 20bt-P- region 16b
can be formed with good controllability.

Next, the operation of the above-mentioned N-channel type MO8FET will be explained while comparing it with the conventional one with reference to FIGS. 2(a) and 2(b). Here, (a) shows the conventional case, and (b) shows the case of the present invention. Ov is applied to 20& and the substrate 11. In the conventional case, since the impurity concentration in the semiconductor substrate 1 is high, the depletion layer in the drain region 20b does not grow slowly. On the other hand, in the MOS FET formed according to the present invention, since the drain region 20 & is provided in the low concentration impurity layer (P layer), the depletion layer 21
extends considerably toward the board 1 side. Furthermore, an inversion layer 22 induced by the gate voltage (5V) is formed on the channel surface. Furthermore, the potential at the pinch-off point 23 (pinch-off voltage V,) is influenced by the impurity concentration below it,
In the conventional case, V is low, and in the case of the present invention, V is high. Since 5V is applied to the drain region 20b, the electric field applied between the pinch-off point 23 of the depletion layer 22 on the surface and the drain region 20b is smaller in the case of the present invention.

In addition, in the case of the present invention, since the concentration near the drain region is low, the depletion layer 21 tends to extend toward the channel side, and the width of the depletion layer at the surface is wide, further reducing the electric field applied to both ends. Furthermore, the source region 20a is formed in the inversion layer 22.
Electrons running toward the drain region 20b are accelerated by the electric field in the depletion layer 21 on the surface, and generate hot carriers by impact ionization. However,
In the present invention, since the electric field in the depletion layer 21 is small, a highly reliable element that is unlikely to cause impact ionization can be obtained.

FIGS. 3(f) to 3(f) respectively show other embodiments of the present invention, and sequentially show manufacturing steps when forming an LDD structure MOS FET using the above-described manufacturing method.

First, as shown in the (=) figure, the impurity concentration is 0160
A field oxide film 2 is formed on the surface of the P-type nest crystal silicon substrate 24 of No. 3 by using a selective oxidation method using a silicon nitride film.
5, a date oxide film 26 with a thickness of 150× is formed in the element region of the substrate 11 surrounded by the field oxide film 25.
form. Next, a polycrystalline silicon layer 27 with a thickness of 5000 mm is deposited on the entire surface, and phosphorus is thermally diffused to lower the resistance value. after that.

7 Using the otrenost 28 as a mask, the polycrystalline silicon layer 27 is subjected to reactive ion etching (RIP) to form a date electrode.

Next, using the photoresist 2B (1) or the polycrystalline silicon layer 27) as a mask, ions of phosphorus are implanted into the element region at an acceleration voltage of 60 keV and a dose of 4×10"cvT 2, and then the photoresist 28 is peeled off. (b) The surface concentration is 5×1 as shown in the figure.
018apt-3 N- regions 29s and 29b are formed.

Thereafter, as shown in FIG. 3(c), a titanium layer 30 having a thickness of 1000× is formed on the entire surface of the semiconductor substrate 24 by the sintering method. After that, when annealing is performed at 750°C, silicidation occurs selectively only in the region where the polycrystalline silicon layer 27 and the titanium layer 30 are in contact, and the titanium silicide layer 31 as shown in FIG. It is formed with a thickness of .

Thereafter, when the semiconductor substrate 24 is treated with an H20□-based aqueous solution, the unreacted titanium layer 30 is removed as shown in FIG.
The gate electrode 32 is selectively removed to form the gate electrode 32.

Next, using the Y-toe electrode 32 as a mask, arsenic is applied to the element region at an accelerating voltage of 40V and a dose of 5X1015c1t.
Ion implantation is performed under the condition of V2. Then, heat treatment is performed to form N+ regions 33A and 33bt- as source and drain regions as shown in FIG.

Next, cover the entire surface with /4 tushipeshi, nM,! :L-(Si
After forming an O□ film and selectively removing 8102K on the source, drain region and date electrode to form a contact hole, aluminum wiring is applied and an N-channel MOS is formed.
Form a transost.

According to such a manufacturing method, the distance between the source and drain regions (channel length) in the LDD structure can be better controlled, and the transnostar characteristics can be stabilized. In other words, Si is applied only to the date side wall using the conventional RIP method.
In the method of leaving the O, film, a deposit of SlO□,
Step coverage and R of SiO2 during formation of
The sidewall width easily changes due to variations in the conditions during IE, resulting in a change in the channel length. In contrast, in the above-described manufacturing method, since silicidation of the polycrystalline silicon layer is used, the thickness of the titanium silicide layer can be accurately controlled only by controlling the temperature during reaction. Furthermore, since the silicide layer and the unreacted polycrystalline silicon layer together form the gate electrode, there is no offset from the N − region. It is said that the reliability of an LDD transistor is closely related to the overrough fj1 between the date electrode and the N-region, and by using the above-mentioned embodiments, it is possible to create an element with a large overrough fi, in other words, a device with straw reliability. can be formed.

In each of the above embodiments, the titanium layer is formed by silicidation, but silicidation using other metals such as molybdenum or tungsten may be used.

Further, after forming the P- region according to the first embodiment, a single layer of N is formed using the gate electrode as a mask, and a spacer such as 5102 is formed on the side wall of the gate, and an N layer is formed outside the single layer of N. You may do so.

Furthermore, in the embodiment described above, an N-channel type MO8FET
Although the manufacturing method has been described, a P-channel MO3FET can also be formed in the same manner, and it is also possible to have an 0MO8 configuration.

[Effects of the Invention] As explained above, according to the present invention, a low concentration layer can be formed in a self-aligned manner at an accurate position, and the parasitic capacitance between the drain region and the semiconductor substrate can be reduced to increase the operating speed. A method for manufacturing a semiconductor device can be obtained in which the LDD structure can be formed with good controllability and high reliability.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining the manufacturing method of a semiconductor device according to an embodiment of the present invention, and FIG. 2 shows the characteristics of the semiconductor device formed by the manufacturing method shown in FIG. 1 above and the conventional manufacturing method. FIG. 3 is a diagram for explaining and comparing the characteristics of the formed semiconductor device, and FIG. 3 is a diagram for explaining another embodiment of the present invention. 11... Semiconductor substrate, 13... Date oxide film, 14
... Polycrystalline silicon layer, 15... Photorenost (
mask), 16h, 16b...P-type region, 18...
-Titanium silicide layer, 20a, 20b...N type region. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 3 Figure 3

Claims (3)

[Claims] (1) A step of forming a polycrystalline silicon layer on a semiconductor substrate via a gate oxide film, a step of patterning this polycrystalline silicon layer, and a mask used for this patterning or the patterned polycrystalline silicon layer. a first impurity introduction step of introducing an impurity into the semiconductor substrate using as a mask, a step of siliciding at least a side wall portion of the patterned polycrystalline silicon layer, and a step of using the silicide layer formed by this silicidation as a mask. A method of manufacturing a semiconductor device, comprising: a second impurity introduction step of introducing an impurity into the semiconductor substrate. (2) the semiconductor substrate is of a first conductivity type;
2. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity introduced into the semiconductor substrate in the second impurity introduction step is of a second conductivity type. (3) The semiconductor substrate is of a first conductivity type, and the impurity introduced into the semiconductor substrate in the first impurity introduction step is of a second conductivity type, and the impurity concentration of the impurity diffusion layer formed by the introduction of this impurity is 2. The method of manufacturing a semiconductor device according to claim 1, wherein: is lower than the concentration of the semiconductor substrate.