JPS62282345A - Cache memory - Google Patents

Cache memory

Info

Publication number
JPS62282345A
JPS62282345A JP62125912A JP12591287A JPS62282345A JP S62282345 A JPS62282345 A JP S62282345A JP 62125912 A JP62125912 A JP 62125912A JP 12591287 A JP12591287 A JP 12591287A JP S62282345 A JPS62282345 A JP S62282345A
Authority
JP
Japan
Prior art keywords
directory
exclusive
cache memory
instruction signals
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62125912A
Other languages
Japanese (ja)
Other versions
JPH0693232B2 (en
Inventor
Kenji Sogawa
十川 健二
Kenji Kubota
窪田 憲治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62125912A priority Critical patent/JPH0693232B2/en
Publication of JPS62282345A publication Critical patent/JPS62282345A/en
Publication of JPH0693232B2 publication Critical patent/JPH0693232B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To properly update a directory by providing two kinds of directory exclusive instruction signals. CONSTITUTION:The directory monopoly instruction signal is divided into exclusive instruction signals 11-14 applying search operation and exclusive instruction signals 7-10 applying the revision of directly by read/write operation in a cache memory system comprising plural controllers 1-4 and a cache memory 5. Then the exclusive instruction signals 7-10 applying the revision of directory by the read/write operation are placed to the priority with high directory exclusiveness by using the exclusive instruction signals 11-14 always applying the searching. Thus, the consecutive exclusiveness of directory by the searching for two times or over is prevented and the revision of the directory by the read/write is finished in several tens of microseconds even in the worst case.

Description

【発明の詳細な説明】 工 発明の詳細な説明 〔産業上の利用分野〕 本発明はキャッシュメモリに係り、特にキャッシュメモ
リの内容書替え時のディレクトリメモリの更新に好適な
ディレクトリメモリの排他制御に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cache memory, and particularly to exclusive control of a directory memory suitable for updating the directory memory when rewriting the contents of the cache memory.

〔従来の技術〕[Conventional technology]

ディレクトリの動作として数十マイクロ秒必妄なサーチ
動作と数マイクロ秒で終了するり−ド/ライト動作があ
る。従来のキャッシュメモリでは、ディレクトリの専有
指示信号が1種しかなく、専有の優先順位は固定されて
おり、優先順位の高い制御装置2台からサーチ動作によ
る専有指示があり、優先順位の低い制御装置から、リー
ド/ライト動作による専有指示を出した場合、リード/
ライト動作終了までに百数十マイクロ秒必要となり。
Directory operations include search operations that take several tens of microseconds and read/write operations that complete in several microseconds. In conventional cache memory, there is only one type of directory exclusive instruction signal, and the priority of exclusive use is fixed. Two control devices with high priority receive exclusive instructions by search operation, and one control device with low priority If an exclusive instruction is issued by read/write operations from
It takes more than 100 microseconds to complete the write operation.

適正なディレクトリの更新が出来なくなる欠点があった
There was a drawback that the directory could not be updated properly.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、キャッシュメモリシステムにおいて、
適正なブイレフ) IJの更新を可能とするキャッシュ
メモリシステムを提供することにあム〔発明の概要〕 複数の制御装置と1つのキャッジ島メモリで構成したキ
ャッシュメモリシステムにおいて、ディレクトリ専有指
示の信号を、サーチ動作を行う専有指示信号と、リード
/ライト動作によりディレクトリの更新を行う専有指示
信号の2種に分け、常にサーチ動作を行う専有指示信号
より、リード/ライト動作によりディレクトリの更新を
行う専有指示信号を、ブイレフ) IJ専有の高い優先
順位に位置ずけることKより、サーチ動作によるディレ
クトリの専有が2回以上続(ことを防止し、織悪でもリ
ード/ライト動作洗よるディレクトリの更新を数十マイ
クロ秒で終了可能とする。
An object of the present invention is to provide a cache memory system with:
[Summary of the Invention] In a cache memory system configured with a plurality of control devices and one cage island memory, a signal for directing exclusive use of a directory is provided. The exclusive instruction signal is divided into two types: an exclusive instruction signal that performs a search operation, and an exclusive instruction signal that updates the directory through read/write operations. By placing the instruction signal at a high priority for IJ exclusive use, it is possible to prevent the directory from being monopolized by a search operation more than once, and to prevent directory updates caused by read/write operations even if there is a mistake. It can be completed in several tens of microseconds.

〔発明の一実施例〕[One embodiment of the invention]

以下、本発明の一実施例をディスクキャッシェの場合に
おいて、第1図、第2図により説明する。
An embodiment of the present invention will be described below with reference to FIGS. 1 and 2 in the case of a disk cache.

キャッシュメモリ5は4つのディスク制御装置1〜4に
よりアクセス可能であり、キャッシュメモリ5には4つ
のディスク制御装置1〜4配下のディスク駆動装置の情
報が格納されている。またキャッシュメモリ5のディレ
クトリにはキャッシュメモリ5の管理情報を格納してお
り、4つのディスク制御装置1〜4で排他制御により専
有使用される。4つのディスク制御装置1〜4は、ブイ
レフ) IJを専有使用するため、それぞれ、ディレク
トリを微マイクロ秒で終了するリード/ライト動作で使
用する短い専有指示信号7〜10と、ディレクトリを数
十マイクロ秒必要とするサーチ動作で使用する長い専有
指示信号11〜14を、キャッシュメモリ5のディレク
トリ専有制?MJ部6に出力する。また、キャッシュメ
モリ5のディレクトリ専有制御部6は、短い専有指示1
8号7〜10と長い専有指示信号11〜14の結果を専
有信号15〜1日により、それぞれのディスク制御装置
1〜4に報告する。ディレクトリ専有制御部6は、長い
専有指示信号11〜14より、短い専有指示信号7〜1
0を専有の優先順位1f!::高くしており、短い専有
指示信号7〜10がないことを見て、長い専有指示信号
11〜14を見に行(、長い専有指示信号11〜14の
いずれか1つによる専有が解除された場合も同様である
The cache memory 5 can be accessed by the four disk control devices 1 to 4, and stores information about the disk drive devices subordinate to the four disk control devices 1 to 4. The directory of the cache memory 5 stores management information of the cache memory 5, and is exclusively used by the four disk control devices 1 to 4 under exclusive control. In order to exclusively use the IJ, the four disk controllers 1 to 4 send short proprietary instruction signals 7 to 10, which are used for read/write operations that complete the directory in microseconds, and short proprietary instruction signals 7 to 10, which are used for read/write operations that complete the directory in a few tens of microseconds. Is the long exclusive use instruction signal 11 to 14 used in a search operation that takes seconds a directory exclusive use system of the cache memory 5? It is output to the MJ section 6. The directory exclusive control unit 6 of the cache memory 5 also provides a short exclusive instruction 1.
The results of No. 8 7-10 and long exclusive use instruction signals 11-14 are reported to the respective disk controllers 1-4 using exclusive signals 15-1. The directory exclusive control unit 6 selects shorter exclusive instruction signals 7 to 1 from longer exclusive instruction signals 11 to 14.
Priority 1f for exclusive use of 0! :: After seeing that there are no short exclusive instruction signals 7 to 10, I go to see the long exclusive instruction signals 11 to 14 (and the exclusive use by any one of the long exclusive instruction signals 11 to 14 is canceled). The same applies if the

ディスク制御装置ii1が短い専有指示信号7を出力し
、ディレクトリ専有制御部6より専有信号15を報告さ
れ、ディレクトリをリード/ライト動作で使用中に、デ
ィスク制御装置2,4に中央処理装置よりREAD命令
が来た時当該READ情報がキャッシュメモリ5に格納
されているかどうか判断するために、ディスク制御装置
2,4はディレクトリをサーチ動作で使用する長い専有
指示信号12 、14を出力し、専有信号16 、18
が報告されるのを待つ。またこの時ディスク制御装置3
がディスク駆動装置からキャッシュメモリ5にシーケン
シャルロードを実行していた場合、1トラツクロード後
、トラックスイッチのギャップ中にディレクトリの内容
を更新しなければならず専有指示信号が1種だと、先に
専有指示信号を出したディスク制御装置2,4にディレ
クトリを専有され、ディスク制御装置5がディレクトリ
を専有可能となるのは百数十マイクロ秒後となり、ディ
スク制駆動装置へ制御信号を出さなければならず、ディ
レクトリ更新のタイミングを逸してしま5゜こOよ5な
不具合をな(すため、ディスク制御装置3は、優先順位
の高い短い専有指示信号9を出力Uディスク制御装置1
のディレクトリ専有のあとへディレクトリを専有する。
The disk controller ii1 outputs a short exclusive use instruction signal 7, the exclusive use signal 15 is reported from the directory exclusive control unit 6, and while the directory is being used for read/write operations, the central processing unit sends READ to the disk controllers 2 and 4. In order to determine whether the relevant READ information is stored in the cache memory 5 when a command arrives, the disk controllers 2 and 4 output long proprietary instruction signals 12 and 14 that use the directory in a search operation, and 16, 18
Wait for it to be reported. Also, at this time, the disk control device 3
is executing a sequential load from the disk drive device to the cache memory 5, and after one track is loaded, the contents of the directory must be updated during the track switch gap. The directory is monopolized by the disk control devices 2 and 4 that have issued the exclusive instruction signal, and the disk control device 5 is able to monopolize the directory after a hundred and several tens of microseconds, unless it issues a control signal to the disk drive and drive device. In order to avoid this, the timing of directory update will be missed and a serious problem will occur.In order to avoid this, the disk control device 3 outputs a short proprietary instruction signal 9 with a high priority to the U disk control device 1.
Exclusive the directory after exclusive use of the directory.

このよ5に2種のディレクトリ専有指示信号を持つこと
により、適正にディレクトリの更新が可能となり、キャ
ッシュメモリ5に今ロードした、トラックが次のサーチ
動作のサーチ対照トラックとして使用可能となるため、
Φヤッシュメモリ5のヒツト率も高くなる利点がある。
By having two types of directory exclusive instruction signals in 5, it is possible to update the directory appropriately, and the track just loaded into the cache memory 5 can be used as a search target track for the next search operation.
There is an advantage that the hit rate of the Φ Yash memory 5 is also increased.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、ディレクトリの更新が待時間なく行な
えるため、例えばディスクキャッシュの場合、ディスク
駆動装置からキャッジ−メモリへのシーケンシャルロー
ドにおいても、1トラツクロード後のトラックスイッチ
のギャップ中に順次ディレクトリの更新が可能となり、
ディスク駆動活着の髄126 fi穴具にたふ−(乳今
キャッシュメモリにロードしたトラックが次のサーチ動
作のサーチ対照トラックとなるため、ヒツト率も高くな
る。
According to the present invention, the directory can be updated without any waiting time. Therefore, in the case of a disk cache, for example, even in sequential loading from the disk drive device to the cache memory, the directory can be updated sequentially during the gap of the track switch after loading one track. It is now possible to update
Since the track loaded into the cache memory becomes the search reference track for the next search operation, the hit rate also increases.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例のギャッシェメモリシステム
の当該ディレクトリ専有制御部の機能ブロック図、第2
図は同じくディンクトリ専有制御部の専有指示信号と専
有信号のタイムチャート図である。 1〜4・・・ディスク制御装置、 5・・・キャッシェメモリ、 6・・・ディレクトリ専有制?a部、 7〜10・・・短い専有指示f3号、 11〜14・・・長い専有指示信号、 15〜18・・・専有信号。
FIG. 1 is a functional block diagram of the directory exclusive control unit of the Gachet memory system according to an embodiment of the present invention, and FIG.
The figure is also a time chart of the exclusive use instruction signal and the exclusive use signal of the dinktree exclusive use control section. 1 to 4...Disk control device, 5...Cache memory, 6...Directory exclusive system? Part a, 7 to 10...Short proprietary instruction No. f3, 11 to 14...Long proprietary instruction signal, 15 to 18... Proprietary signal.

Claims (1)

【特許請求の範囲】[Claims] 1 複数の制御装置からアクセスされるキャッシュメモ
リと、キャッシュメモリの管理情報を格納し、前記複数
の制御装置から排他的に使用されるディレクトリにより
構成されるキャッシュメモリシステムにおいて、前記複
数の制御装置はディレクトリを専有する時間の長短に応
じた2種の専有指示信号を出力し、さらに前記ディレク
トリは前記複数の制御装置からの各々2種の専有指示信
号を検出し、どちらの専有指示信号が出力されているか
により、専有する制御装置の優先順位を決定しディレク
トリの専有を許可し、またディレクトリを専有したか否
かの結果を前記複数の制御装置に報告することを特徴と
するキャッシュメモリ。
1. In a cache memory system configured of a cache memory accessed by a plurality of control devices and a directory that stores management information of the cache memory and is used exclusively by the plurality of control devices, the plurality of control devices Two types of exclusive instruction signals are outputted depending on the length of time for exclusive use of the directory, and the directory further detects two types of exclusive instruction signals from each of the plurality of control devices, and which exclusive instruction signal is outputted. The cache memory is characterized in that the priority order of the exclusive control device is determined depending on whether the directory is exclusive, the directory is allowed to be exclusive, and the result of whether or not the directory is exclusive is reported to the plurality of control devices.
JP62125912A 1987-05-25 1987-05-25 Cache memory Expired - Lifetime JPH0693232B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62125912A JPH0693232B2 (en) 1987-05-25 1987-05-25 Cache memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62125912A JPH0693232B2 (en) 1987-05-25 1987-05-25 Cache memory

Publications (2)

Publication Number Publication Date
JPS62282345A true JPS62282345A (en) 1987-12-08
JPH0693232B2 JPH0693232B2 (en) 1994-11-16

Family

ID=14921993

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62125912A Expired - Lifetime JPH0693232B2 (en) 1987-05-25 1987-05-25 Cache memory

Country Status (1)

Country Link
JP (1) JPH0693232B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0480858A2 (en) * 1990-10-12 1992-04-15 International Business Machines Corporation Hardware primary directory lock

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0480858A2 (en) * 1990-10-12 1992-04-15 International Business Machines Corporation Hardware primary directory lock
US5339397A (en) * 1990-10-12 1994-08-16 International Business Machines Corporation Hardware primary directory lock

Also Published As

Publication number Publication date
JPH0693232B2 (en) 1994-11-16

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