JPS62281199A - Control circuit for nonvolatile static ram - Google Patents

Abstract

PURPOSE:To prevent data protected in an EEPROM from being destroyed at power source restoration by using a delay circuit and an AND circuit so as to suppress the generation of a control signal OE until the leading of a power source voltage is made stable. CONSTITUTION:A power source voltage delay circuit 4 consists of a delay element comprising an integration resistor 6 and an integration capacitor 7 and of a level converting circuit comprising a transistor (TR) 8, a photocoupler 9 and resistors 10, 11. An output B of the delay circuit 4 is suppressed to a low level by delay elements 6, 7 until a power source voltage rises and reaches a steady-state value and a control signal OE is suppressed to a low level independently of the control signal A. When the power source voltage reaches a steady- state value, the output B of the delay circuit 4 goes to a high level and the control signal OE is brought into a high level by the signal A from the control circuit 2 and supplied to a nonvolatile static RAM 1. Thus, no control signal OE is generated until the actual power source voltage reaches a steady-state value surely and the generation of the nonvolatile storage mode is prevented and the data in an Electrically Erasable and Programmable ROM (EEPROM) is protected.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] This invention relates to a non-volatile static RAM when the non-volatile static RAM is used to protect data when the system power is cut off. The present invention relates to a control circuit.

[Conventional technology]

The first figure is a block diagram showing the control circuit of the conventional non-volatile static II (AM). !ent
ral processing unit).

All of the above are powered by the same power supply +vcc.

Next, the operation will be explained. Table 1 shows an example of the operation mode of the non-volatile static RAM +1).

When controlling the non-volatile static RA and M fi+, the control signals shown in Table 1 (9 rows, 1 page, 1) are applied from the CPU +31 to the non-volatile static RAM +11 via the control circuit (2).

In addition, the control circuit (2) is provided with a power supply voltage drop detection circuit to generate a non-volatile accumulation mode when the power is cut off.
Data in static RAM is transferred to non-volatile memory.
ij! ;PROM (B) electrically Kr
asableand'Programmab1eRO
M) Protect data by incorporating gEP
When the CPU reads data written in the ROM, the recall mode and the RAM read mode are performed in sequence after the power is restored.

[Problem that the invention seeks to solve]

Since the conventional non-volatile static RAM control circuit is configured as described above, the off-side storage mode is activated in the process of restoring the power so that the CPU can read out the data that has been suspended in the EKPROM due to a power outage. There was a problem in that the data in the iFROM was destroyed due to this occurrence.

The aim of the present invention is to obtain a control circuit that can prevent the above-mentioned problems from occurring. The power supply voltage waveform at power-on is delayed, and the logical product (
AND) is supplied to the RAM.

[Effect]

In the control circuit of the non-volatile static RAM in this invention, the power supply voltage reduction is delayed at power-on (recovery) 118, and after ANDing with this, the control signal OE is sent to the RAM.
The control signal OE is not generated at 1, where the actual voltage actually settles to a steady value, and no r
The occurrence of the ol1 accumulation mode is prevented, and the data in the BEPROM can be preserved.

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment of the present invention, in which (4) is a power supply voltage delay circuit, and (5) is a control circuit (control signal A from the control circuit 21 and output B of the power supply voltage delay circuit (4)). This is an AND gate that performs an AND operation and then supplies the control signal OE to the nonvolatile static RAM ill.

The power supply voltage delay circuit (4) consists of delay elements such as an integrating resistor (6) and an integrating capacitor (7), and a level converter circuit consisting of a transistor (8), a photocoupler (9), and resistors t+ol and ltl.

With this configuration, the output B of the delay circuit (4) is kept at a low level by the delay elements f61 and +71 until the power supply voltage rises and settles to a steady state of 1, and the control signal OE remains unchanged regardless of the control signal A. can be kept to a low level.

When the tg' navigation pressure settles down to a steady value, the output 'B of the delay circuit (4) goes to a high level, and the control signal OB is set to a high level by the signal A from the control circuit (2) to maintain the non-inflatable state.
Can be supplied to one RAM itl.

As can be easily seen from the figure, the operation of the level converter circuit is such that the charging voltage of the integrating capacitor (7) causes the transistor (δ) to
In the old days, the transistor (8) was OFF and the photocoupler (91) was also OFF, so the output B was at a low level. When the voltage exceeds the above vmm, the transistor (8) and photocoupler (9) are turned on.
Since the photocoupler (9) also operates, the potential of the output B becomes high level, and the control signal Ω is output from the AND gate 5).
will be obtained.

The power supply voltage delay circuit (4) in the first embodiment described above uses a photocoupler (9) in order to adjust the level of the output signal B to the AND game (i5), but the power supply voltage delay circuit (4) as shown in FIG. In the pressure delay circuit (4A), the charging voltage of the integrating capacitor (7) may be taken out from the emitter resistor (12) as the emitter follower output of the transistor (8). At this time, the output voltage is VCC-
This becomes VEI, but if this is suitable for the human power level of the AND gate (5), such a simple circuit configuration can be used.

FIG. 3 is a waveform diagram showing the operation of the above embodiment, where the power supply voltage +
VCC rises as shown in the figure, but the power supply voltage delay circuit (4
) has an integral constant selected so that output B rises only after the power supply voltage +VCC has settled down. Therefore, even if the output A from the control circuit (2) has an output as shown by the dashed line while the output B is at a low level, the sharpening signal O as the output of the AND circuit (6) remains at a high level. Must not be.

In the above implementation 1 and 11, a transistor is used in the level conversion circuit.

Although we used photocouplers, other Noh! 1iIJ-z children, such as F'ET, comparator members, etc. may also be used.

〔Effect of the invention〕

As described above, in the present invention, the delay circuit and the AND circuit are used to suppress the generation of the control signal OE until the rise of the power supply voltage has subsided. Data protected by FJPRoM will not be destroyed when the source is restored, making it easier to use non-wandering static RAM.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, and FIG.
FIG. 3 is a circuit diagram showing only the essential parts of other embodiments, FIG. 3 is a waveform diagram showing the operation of these embodiments, and FIG. 3 is a block diagram showing a control system of a conventional non-volatile static RAM. In the figure, (1) is nonvolatile static RAM. (2) is the control circuit, (3) is (!PU, i4),
(4A) is a power supply voltage delay circuit, and (5) is an AND circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts. Ken Hayase

Claims (1)

[Claims] (1) Equipped with a power supply voltage delay circuit that delays the power supply voltage when the power is turned on and outputs an output signal after the power supply voltage has settled to a steady value, and is a non-volatile static RAM until the output signal of the power supply voltage delay circuit is output. static R within
A control circuit for a non-volatile static RAM, characterized in that a write operation mode from an AM to a non-volatile memory is suppressed from occurring.