JPS62279473A - Detecting circuit for edge of binary image - Google Patents

Abstract

PURPOSE:To decrease the capacity of a memory, and also, to remarkably shorten the processing time by storing only the lowest variation point in a screen, in an edge being a variation point of an image data, in the memory. CONSTITUTION:To an address end of a memory 5a, a coordinate position on a horizontal scanning line of a picture element, namely, a column address for indicating a store address is supplied cyclically, and also, to a data input end, a coordinate position in the vertical direction of the picture element, namely, a row address is always supplied. Whenever a timing signal W is inputted, the memory 5a stores the line address of that time in the address indicated by the row address of that time. Also, when the row address has been shifted, in case when the signal W has been generated, the row address is rewritten. Updating of this row address is executed until a frame scan of one is ended. Accordingly, in the end, the final row address related to each column is stored in the memory 5a. For instance, in case an object to be inspected has been inputted from a camera, only the lower edge in an image data is stored. Therefore, a small capacity of the memory 5a is enough, and the processing amount is decreased remarkably.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Industrial Application Field] The present invention is suitable for use in recognizing the shape and posture of an article on a belt conveyor, or inspecting the article, etc. This invention relates to an edge detection circuit for binary images. [Prior Art] Many applied fields of image processing require high-speed processing. For example, when inspecting products placed on a belt conveyor, image processing must be performed in real time and control signals must be output. FIG. 4 is a block diagram showing the conventional configuration of a binary image edge detection circuit used in this type of image processing. In the figure, l is a synchronous separation circuit. A video signal is supplied to the input end of the synchronization separation circuit 1 from a video camera (not shown). The synchronous separation circuit l is
A vertical synchronizing signal VD, a horizontal synchronizing signal 1-ID, and a video signal Vs are separated and extracted from the video signal. The video signal Vs is then converted into a binary image by the binarization circuit 2 and output as binary image data Vs'. The respective signals HD, VD, and Vs' are supplied to the memory manual control circuit 3. This memory input control circuit 3 writes the image data Vs' bit by bit into the frame memory 5 in synchronization with the clock pulse SC supplied from the oscillator 4. FIG. 5 is a block diagram showing the configuration of the memory input control circuit 3. As shown in FIG. In the figure, 6 is an address counter that specifies the row address (vertical address) of the frame memory 5, and 7 is an address counter that specifies the column address (horizontal address) of the frame memory 5 (hereinafter referred to as
(simply called a counter). The counter 7 is cleared by the horizontal synchronizing signal HD and clock pulse SC
count. The counter 6 also receives a vertical synchronizing signal V
It is cleared by D and counts the horizontal synchronization signal HD. Therefore, the column address corresponds to the coordinate position of each pixel (dot) on the horizontal scanning line, and the row address corresponds to the coordinate position of each pixel in the vertical direction. Further, the clock pulse SC is also supplied to the write enable terminal W, and the image data Vs' is supplied from the latch 8 to the data input terminal of the frame memory 5. Returning to FIG. 4, 9 is a memory output control circuit that reads out the image data Vs'' written in the frame memory 5 and supplies it to the computer IO. In such a configuration, as shown in FIG. Each time the clock pulse SC rises, the column address is updated, and the binary image data Vs'' is sequentially written into the frame memory 5 at the fall of the clock pulse SC. Therefore, all image data will be stored in the frame memory 5. Then, the point at which the binary image data changes (edge), that is, the point at which it changes from the "H" level to the "L" level, or the point at which it changes from the "L" level to the "H" level, is determined by the computer IO. be done. For example, in Figure 7 (a
) is input from the camera, and Δ
When measuring Δy, the same figure (b)
All image data is stored in the frame memory 5 as shown in FIG. 5, and only necessary data is extracted from the stored data by the computer 10. [Problems to be solved by the invention] By the way, in the conventional edge detection circuit described above,
Since all the image data is written in the frame memory 5, there is an inconvenience that the capacity of the frame memory 5 becomes large. For example, to store data of 256x256 pixels, 64 bits of memory are required. Along with this, there is a problem that the computer IO handles 64 human image data every time, which increases the processing time. The present invention was made against this background, and an object of the present invention is to provide an edge detection circuit for binary images that reduces memory capacity and processing time. [Means for Solving the Problems] In order to solve the above problems, the edge detection circuit for a binary image of the present invention stores the same number of address data as the number of pixels on the horizontal scanning line of the binary image. address supply means for cyclically supplying the coordinate position of the pixel on a horizontal scanning line to an address end of the memory; and data supply means for supplying the vertical coordinate position of the pixel to a data input end of the memory. , for each binary pixel,
writing means for detecting whether or not the pixel is a value representing the object, and writing and updating the vertical coordinate of the pixel at that time in the memory when the pixel is a value representing the object; Features. [Function] The binary image edge detection circuit of the present invention reduces the storage capacity of the memory by storing only the lowest changing point on the screen among edges that are changing points of image data. , reducing processing time. [Example] Hereinafter, an example of the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an edge detection circuit according to an embodiment of the present invention. In the drawings, parts similar to those of the conventional example having a flat surface are denoted by the same reference numerals, and the explanation thereof will be omitted. 11 is an inverter, 12 is a Nant gate, one input terminal of the Nant gate 12 receives a clock pulse SC inverted by the inverter 11, and the other input terminal of the Nant gate 12 receives a latch 8. The output terminal of the Nant gate I2 is connected to the write enable terminal W of the memory 5a. The input signal W to this write enable terminal W is input to the memory 5a. The memory 5a has a smaller capacity than the memory 5 in FIG. 5, and the output of the counter 7 is supplied to its address end, and the counter 6 is supplied to its data input end. The memory 5a is capable of storing the same number of address data as the number of pixels on the horizontal scanning line of the image data Vs''. Next, the effect will be explained. As shown in FIG. 2(b), the column address counter 7 is cleared when the horizontal synchronizing signal HD is at the LOW level, and when it is at the HIGH level, the column address counter 7 is cleared by the clock pulse S.
It counts up by 1 each time C rises. Also,
As shown in FIG. 2(a), the row address counter 6 is cleared when the vertical synchronization signal VD is at the LOW level, and when it is at the HrG level, it is cleared by 1 every time the horizontal synchronization signal HD rises. Count up one by one. For this reason,
A column address indicating the coordinate position of the pixel on the horizontal scanning line, that is, the data storage address of the memory 5a, is cyclically supplied to the address end of the memory 5a. Further, the vertical coordinate position of the pixel, that is, the row address as stored data, is always supplied to the data input terminal of the memory 5a. On the other hand, the timing signal W is generated as follows. First, considering the period from when the horizontal synchronizing signal HD becomes LOW level to when it becomes the next LOW level, that is, during one horizontal scan, binary image data Vs' is generated at the rising edge of clock pulse SC. But HfG! - When the level is reached, the latch 8 sets the image data V,” to HIGH.
Latch to level. Then, when the clock pulse SC becomes LOW level at the next time, the Nant gate 12
The input terminals of both become HIGH level, and the Nant gate I2 outputs the timing signal W. As shown in FIG. 2(b), this timing signal W is generated every time the clock pulse SC becomes LOW level as long as image data Vs'' is at HIGH level. Image data Vs'' is LOW. When the level is reached, the clock pulse SC is no longer generated. Every time the timing signal W is input, the memory 5a stores the current row address at the address indicated by the current column address. In the case of FIG. 2(b), the row address "l" is stored in the addresses of the memory 5a corresponding to the column addresses "4", "5", and "6". For example, when the row address moves to "2", the timing signal W is sent again at the column addresses "5" and "6".
If the row address "2" is generated, the row address "2" is rewritten to the address in the memory 5a corresponding to the column addresses "5" and "6". Such updating of the row address is performed using the vertical synchronization signal VD h
< This is repeated until the LOW level is reached, that is, until one frame scan is completed. Therefore, the final row address for each column will eventually be stored in the memory 5a. For example, when an inspection target as shown in Figure 3(a) is input from a camera, only the lower edge of the image data, that is, the data of the "1" part in the figure, is displayed as shown in Figure 3(b). It will be stored. The data stored in the memory 5a is processed by the computer. When the stored data is as shown in FIG. 3(b), the computer determines each part to be inspected from the column address and the row address data stored at that address, as in the case of FIG. 7(a). Measure the dimensions ΔX, helmet, y and Δy. By the way, since the data stored in the memory 5a is only the lower edge of the image data, the capacity of the memory 5a is small, and when compared with the conventional method, for example, 256
x256=64 bits needed, 256x
8 = 2 hits. This greatly reduces the amount of data processed by the computer, making it possible to speed up image processing. Note that, contrary to the case of the above-described embodiment, by inputting the row address from the counter 6 to the address end of the memory 5a and the column address from the counter 7 to the data input terminal, the storage in the memory 5a△ is performed. It is also possible for the data to be only the right edge of the image data. [Effects of the Invention] As explained above, the binary image edge detection circuit of the present invention is configured to store only the position data of the lower change points (edges) of the image data in the memory, so the memory capacity is limited. can be reduced. Moreover, the amount of data to be processed by the computer is significantly smaller than in the past, and the processing time of the computer can be significantly reduced.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of the main part of an embodiment of the present invention, Fig. 2 is a waveform diagram for explaining the operation of the embodiment, and Fig. 3(a) is the object to be imaged in the embodiment. A diagram showing an example of an object, and FIG. 3B is an explanatory diagram of a lower edge in image data of the object to be imaged. Fig. 4 is a block diagram showing a conventional example of an edge detection circuit for binary images, Fig. 5 is a block diagram showing the configuration of the main parts of the circuit, and Fig. 6 is a waveform diagram for explaining the operation of the circuit. , 7th
Figure (a) is a diagram showing an example of an object to be imaged, and Figure (b) is an explanatory diagram of a lower edge in image data of the object to be imaged. 5a...Memory, 6...Counter (data supply means), 7...
... Counter (address supply means), 8 ... Latch (detection means), 11 ... Inverter, 12
...Nant Gate (in the above, t 1.+2 is the writing means).

Claims (1)

[Scope of Claims] A memory capable of storing the same number of address data as the number of pixels on a horizontal scanning line of a binary image, and cyclically supplying the coordinate position of the pixel on the horizontal scanning line to an address end of the memory. address supply means; data supply means for supplying the vertical coordinate position of the pixel to a data input end of the memory; 1. An edge detection circuit for a binary image, comprising writing means for writing and updating the vertical coordinates of a pixel at that time in a memory when is a value representing a subject.