JPS62113288A - Edge detecting circuit for binary image - Google Patents

Abstract

PURPOSE:To reduce the capacity of a memory and to shorten a processing time by providing data supply means which supply position data on the position of a change point to the data input terminal of a memory and writing means which write the position data on the memory when the change point is detected. CONSTITUTION:Change point detecting means 11 and 12 which detect the change point of a binary image, data supply means 6 and 7 which supply position data on the position of the change point to the data input terminal of the memory 5a, and means 13-15 which write the position data on the memory when the change point is detected are provided. The memory is stored with the change point of image data, i.e. only an edge and the number of bits required to store one change point increases, but the number of picture elements of the change point is much less than the total number of picture elements, so the number of bits required to store all change points is less than the number of bits required to store all picture elements. Consequently, data which are processed by a computer decreases in number greatly and the processing time of the computer is shortened greatly and the capacity of the memory is decreased.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention provides a binary image edge detection circuit suitable for use in recognizing the shape and posture of an article on a belt conveyor, or inspecting the article. Regarding.

[Prior Art] Many applied fields of image processing require high-speed processing. For example, when inspecting products placed on a belt conveyor, image processing must be performed in real time and control signals must be output.

FIG. 3 is a block diagram showing the conventional configuration of a binary image edge detection circuit used in this type of image processing. In the figure, 1 is a synchronous separation circuit.

A video signal is supplied to the input terminal of the synchronization separation circuit I from a video camera (not shown). The synchronization separation circuit 1 separates and extracts a vertical synchronization signal VD, a horizontal synchronization signal 11D, and a video signal Vs from this video signal. The video signal Vs is then converted into a binary image by the binarization circuit 2 and output as binary image data vb.

The above signals HD, VD, and Vb are supplied to the memory manual control circuit 3. This memory manual control circuit 3 loads the image data vb one hit at a time into the frame memory 5 in synchronization with the clock pulse SC supplied from the transmitter 4.

FIG. 4 is a block diagram showing the configuration of the memory input control circuit 3. As shown in FIG. In the figure, 6 is an address counter that specifies the row address of the frame memory 5;
is an offset address counter (hereinafter simply referred to as a counter) that specifies the column address of the frame memory 5. '' The two-legged counter 6 is cleared by the horizontal synchronization signal 1-[D and counts clock pulses SC. Further, the counter 7 is cleared by the vertical synchronization signal VD and counts the horizontal synchronization signal HD. Therefore, the line address is! Each dot (pixel) of a horizontal line corresponds to a column address, and a column address corresponds to each horizontal line. Further, the clock pulse SC is also supplied to the write enable terminal W, and the image data vb is supplied to the data input terminal of the frame memory 5.

Returning to FIG. 3, 8 is a memory output control circuit which reads out the image data vb written in the frame memory 5 and supplies it to the computer 9.

In such a configuration, as shown in FIG. 5, the row address is updated every time the clock pulse SC rises, and the 2rti image data vb are sequentially written into the frame memory 5 at the fall of the clock pulse SC. go. Then, the change point (edge) of the binary image data, the point where it changes from the I-[" level to the "L" level, or the point where it changes from the "L" level to the "1(" level. is determined by the computer 9.

[Problems to be solved by the invention] By the way, in the conventional edge detection circuit described above,
Every time the clock pulse SC falls, the image data vb
Since the data is written to the frame memory 5, there is an inconvenience that the capacity of the frame memory 5 becomes large.

For example, to store data of 256x256 pixels, 64 bits of memory are required. Along with this, there is a problem in that the computer 9 handles 64 bits of image data each time, which increases the processing time.

The present invention was made against this background, and it is an object of the present invention to provide an edge detection circuit for binary images, which is capable of reducing memory capacity and processing time.

[Means for Solving the Problems] In order to solve the above problems, the present invention provides a change point detection means for detecting a change point in a binary image, and a change point detection means for detecting a change point in a binary image, and position data indicating the position of the change point as data in a memory. The apparatus is characterized in that it includes data supply means for supplying data to an input end, and writing means for writing the position data into the memory when detecting the change point.

[Operation] According to the above configuration, only changing points of image data, that is, edges are stored in the memory. In this case, the number of focus points required to memorize one change point increases, but since the number of pixels at a change point is a small fraction of the total number of pixels, the number of bits required to memorize all change points is is smaller than the number of bits required to write all pixels tα. Furthermore, since the computer can directly read the change points from the memory, processing time can be shortened.

[Example] Hereinafter, with reference to the drawings, a detailed explanation of the present invention will be given.
1 is a block diagram showing the configuration of an edge detection circuit according to an embodiment of the present invention. FIG. In the figure, 11 is image data v
This is a 2-bit shift register for detecting and shifting the change point (edge) of b.

Image data vb is input to the input terminal SA of the shift register 11.
On the other hand, the outputs QA and QB of each bit of the shift register II are supplied to each input terminal of the exclusive OR gate 12. Therefore, the output terminal A of the exclusive OR gate I2 becomes the "I-1" level only when an edge is detected. This is because the output terminal of the exclusive OR gate 12 becomes the "Summer 1" level only when either rI-1, LJ or rL, I(J) enters the shift register 11.

The output of the exclusive-OR gate 12 is applied to a second input of a NAND gate 13, which forms a NAND signal with the inverted signal of the clock pulse SC, which is applied via an inverter 14 to its first input. First, when the clock pulse SC is at the "L" level and the output is at the "I-1" level, a signal at the "L" level is output from the Nant gate 13, which is connected to the write enable terminal W of the memory 5a and the counter! 5 input terminal.

The memory 5a has a smaller capacity than the frame memory 5 shown in FIG. 3, and has a counter 15 at its address end.
The output of counter 6.7 is supplied to the data input terminal.
The output of is supplied as X data and Y data.

In such a configuration, the counter 6 is cleared by the horizontal synchronizing signal 1-ID and counts up the clock pulse SC. Further, the counter 7 is cleared by the vertical synchronizing signal VD, and counts up the horizontal synchronizing signal 1-ID. Therefore, the pixel address is always supplied to the data input terminal of the memory 5a.

In this state, the image data vb at time 1+ in FIG.
changes from “L” level to “H” level, time t2
Then, the image data vb is taken into the shift register 11 by the rising edge of the clock pulse SC, and the shift register I I (1) first output QA changes to the "■" level. At this time, since the second output terminal QB of the shift register If is at the "L" level, the output terminal A of the exclusive OR gate 12 is at the "I" level. At the next time t3, the clock pulse SC is at the "L" level. ” level, both the input power to the Nant gate 13 becomes the “1 (” level), so its output becomes the “L” level, and the “L” level is supplied to the write enable terminal W.
data and Y data are written into the memory 5a.

On the other hand, at time t4, due to the rising edge of the clock pulse sc, "I-■" is applied to the second pit of the shift register 11.
When a level signal is taken in, the output terminal QB becomes “T”.
Since both the inputs to the exclusive loop or gate 12 become "H" level, the output terminal A thereof becomes "HI" level. Therefore, the output of the Nant gate I3, that is, the signal supplied to the write enable terminal W is “H”.
” level, and writing is prohibited. Also, at this time t4, the output of the Nant gate 13 causes the counter I
5 is counted up by 1, and the designated address of the memory 5a is shifted by 1.

Next, when the image data vb changes from the "H" level to the "L" level at time t5 in FIG. changes to "11" level.

Then, at the next time t7, the clock pulse SC goes “L”.
When the level is reached, an "L" level signal is supplied to the write enable terminal W, and the X data and Y data at this time are read into the memory 5a. Further, at time t8, when the outputs of the exclusive or games 1 and 2 go to the "L" level, the write enable terminal W changes to the "I" level, and writing to the memory 5a is prohibited. Further, the counter 15 counts up by 1, and the address of the memory 5a is shifted by 1.

In this way, when the image data vb changes, the X data,
Only the Y data is sequentially written into the memory 5a. That is, the memory 5a is stored on an edge. Therefore, the computer 9 can know the edge position simply by reading data from the memory 5a.

[Effects of the invention] As explained above, this invention extracts only the changing points (edges) of image data and writes them into memory, so the amount of data to be processed by a computer is significantly less than in the past. Become. As a result, there is an advantage that the computer processing time can be significantly reduced. Additionally, memory capacity can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of essential parts of an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation of the embodiment, and FIG. 3 is a conventional edge detection circuit for binary images. FIG. 4 is a block diagram showing the configuration of the main part of the same commercial route, and FIG. 5 is a waveform diagram for explaining the operation of the same circuit. ζ +, J ヱ I+ 1!
? , J+ - book -4+ /
−=! Head-11L! - human means), 11
...Knot register, 12...Exclusive or game-1 (above, 11 and 12 are change point detection means), I3
. . . Nant gate, I 4 . . . Inverter, I 5 . . . Counter (in the above, 3 to 15 are writing means). Figure 1 Figure 2

Claims (1)

[Claims] a change point detection means for detecting a change point of a binary image; a data supply means for supplying position data indicating the position of the change point to a data input terminal of a memory; and a data supply means for supplying the position data to the memory when detecting the change point. 1. An edge detection circuit for a binary image, comprising a writing means for writing.