JPS62278473A - Semiconductor electronic circuit - Google Patents

Semiconductor electronic circuit

Info

Publication number
JPS62278473A
JPS62278473A JP61121090A JP12109086A JPS62278473A JP S62278473 A JPS62278473 A JP S62278473A JP 61121090 A JP61121090 A JP 61121090A JP 12109086 A JP12109086 A JP 12109086A JP S62278473 A JPS62278473 A JP S62278473A
Authority
JP
Japan
Prior art keywords
circuit
circuits
switches
signal
semiconductor electronic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61121090A
Other languages
Japanese (ja)
Inventor
Masayoshi Suzuki
鈴木 政善
Junichi Owada
淳一 大和田
Masaaki Kitajima
雅明 北島
Masaru Takahata
勝 高畠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP61121090A priority Critical patent/JPS62278473A/en
Publication of JPS62278473A publication Critical patent/JPS62278473A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To enable inspection with a relatively simple circuitry, by dividing an internal circuit of a semiconductor electronic circuit into several circuits to detect and judge power source currents from the divided circuits. CONSTITUTION:Circuits 2A-2Z have a common ground point 1B and a pair of power source side terminal thereof are connected to switches 3A-3Z, the other ends of which are connected to a current detection circuit 4. A power source 1 for providing voltage and current to the circuits is connected between a ground point 1A and the circuit 4. Respective signals are provided to the switches 3A-3Z from a control circuit 5 while a signal of the circuit 5 is provided to the circuit 4. Here, for example, when the operating condition of the circuit 2A is inspected, the switch 3A alone is closed by a control signal from the circuit 5 while the other switches 3B-3Z are kept open. Under such a condition, the circuit 2A is put into operation and the current flowing through the circuit 4 at that time is checked. This enables judgement on whether the circuit 2A operates normally.

Description

【発明の詳細な説明】 3、発明の詳細な説明 〔産業上の利用分野〕 本発明は半導体電子回路に関するものである。[Detailed description of the invention] 3. Detailed description of the invention [Industrial application field] The present invention relates to semiconductor electronic circuits.

〔従来の技術〕[Conventional technology]

従来試験あるいに診断を考慮したLSIの構底法につい
てに電子通信学会誌6/81 617頁「超LSIのた
めの試験機と試験技術」等に示すように、LSI内部に
試験が容易になるような回路を積砥的に付加する方法が
とられている。この方法で代表的なものにスキャンパス
法がある。
Regarding LSI construction methods that take conventional testing and diagnosis into consideration, as shown in the Journal of the Institute of Electronics and Communication Engineers, 6/81, p. 617, "Testing Machines and Testing Techniques for Ultra-LSIs," tests can be easily carried out inside LSIs. A method has been adopted in which circuits such as these are added in a cumulative manner. A typical example of this method is the scan path method.

これαL8Iffiのすべてのフリツプフロツプの前段
に本来の論理機能に影響を与えないような付加回路を設
は機能試験を実行するときにこれらの7リツプフロツプ
をシフトレジスタとして動hgせることにより、被試験
LSI(順序回路)を等価的に組合わせ回路に分割して
試験を容易にする方法である。
An additional circuit that does not affect the original logic function is installed in front of all the flip-flops of the αL8Iffi. By operating these 7 flip-flops as a shift register when performing a functional test, the LSI under test ( This method facilitates testing by equivalently dividing sequential circuits into combinational circuits.

〔発明が解決しようとする問題点] 上記従来技術汀試験のための回路規模が大きくなり、ま
た回路のどの部分が故障状態にあるかを容易に診断する
ことは困鮨であった。
[Problems to be Solved by the Invention] The scale of the circuit for the above-mentioned prior art test is large, and it is difficult to easily diagnose which part of the circuit is in a faulty state.

本発明の目的riL3I内部の回路を幾つかに分割して
試験、診断できる半導体電子回路を提案するにある。
An object of the present invention is to propose a semiconductor electronic circuit in which the internal circuit of riL3I can be divided into several parts for testing and diagnosis.

〔問題点を解決するための手段〕[Means for solving problems]

上記目的に、LSIの内部回路を幾つかの回路に分け、
それらの回路の電源11fiを検出判定することで達成
される。
For the above purpose, the internal circuit of the LSI is divided into several circuits,
This is achieved by detecting and determining the power supply 11fi of those circuits.

〔作用〕[Effect]

つ1り、LSI回路を幾つかの回路に分割してその電源
電流を検出し観測Tれば、回路が動作するとき特有の電
流が流れるため、この判定を行えば該当する回路の試験
診断ができる。
In other words, by dividing an LSI circuit into several circuits and detecting and observing the power supply current, a unique current flows when the circuit operates, so this judgment can be used to test and diagnose the relevant circuit. can.

第1図に本考案の原理を示す。回路2A、2B。Figure 1 shows the principle of the present invention. Circuits 2A and 2B.

・・・、2Zt:I共通の接地点IBを有しており、そ
の対の電源@端子にスイッチ3A、3B、・・・、3Z
に接続ばれており、スイッチの他端にまとめられてt流
検出回路4に接続されている。
..., 2Zt:I has a common grounding point IB, and switches 3A, 3B, ..., 3Z are connected to the power supply @ terminal of the pair.
are connected to the other end of the switch and connected to the t-current detection circuit 4.

回路に電圧、電流を与える電圧源11通常、電池等で代
表される)は接地点IAと検出回路4との間に印加され
る。スイッチ3A、3B・・・、 3Zには制御回路5
より信号がそれぞれ与えられ、制御回路5の信号は検出
回路4にも与えられている。
A voltage source 11 (usually represented by a battery, etc.) that provides voltage and current to the circuit is applied between the ground point IA and the detection circuit 4. Switches 3A, 3B..., 3Z have a control circuit 5
The signals from the control circuit 5 are also provided to the detection circuit 4.

今・回路2人の動作状態を検ffる場合にスイッチ3A
のみを制御信号によって閉じ、他のスイッチは開状態と
しておく。この状態でに回路2人のみに電圧#1の電圧
が印加され、他の回路2B。
Now, when checking the operating status of two circuits, switch 3A
Only one switch is closed by a control signal, and the other switches are left open. In this state, voltage #1 is applied only to the two circuits, and the other circuit 2B.

・・・、2Zに全てオフ状態となる。この状態で回路2
人を動作状態としく動作状態とするには外部等より回路
2人に対しクロックパルス等の信号を与えるか、あるい
に磁気、光等の結合手段によって信号を与えればよめ)
、そのときのt流検出回路4に流れる電流をチェックす
ることで、回路2人の動作が正常であるか否かが判定で
きる。
. . ., all are turned off at 2Z. In this state, circuit 2
To put a person in an operating state, it is best to give a signal such as a clock pulse to the two circuits from the outside, or give a signal by coupling means such as magnetism or light)
By checking the current flowing through the t-current detection circuit 4 at that time, it can be determined whether or not the two circuits are operating normally.

回路2Bを検査する場合にスイッチ3Bのみを閉状態と
し、他のスイッチを開として、上記の動作を行えばよい
。このスイッチの開閉に制御回路5の出力信号を変える
ことで行ない得る。
When inspecting the circuit 2B, the above operation may be performed with only the switch 3B closed and the other switches opened. This can be done by changing the output signal of the control circuit 5 to open and close this switch.

〔実施例〕〔Example〕

以下、本発明の一実施例を@2図により説明する。図中
、第1図中の主要部分と同じ機能のもの    ″に対
しては同一の番号を付してlる。第1図中の回路2人α
本例ではゲート回路13に、回路2B框フリツプフaツ
ブ回路14に、それぞれ対応している。スイッチ3A、
3Bは金属酸化膜電界効果トランジスタc以下MOSト
ランジスタと略す)38人、30Bを用いている。電流
検出に抵抗7を電圧源1に直列に接続し、抵抗の電圧を
検出することで実現Tる(このとき、抵抗値を低くして
電圧1の電圧がほとんどこの抵抗両端に加えられないよ
うに工夫Tる)。この検出された電圧vla判定回路6
に送られる。制御回路5はカウンタ8及びデコーダ9よ
り構成され、カウンタ8に入力端子10を有している。
Hereinafter, one embodiment of the present invention will be explained with reference to Figure @2. In the figure, parts with the same function as the main parts in Figure 1 are given the same numbers.
In this example, they correspond to the gate circuit 13 and the circuit 2B frame flip-flop circuit 14, respectively. switch 3A,
3B is a metal oxide film field effect transistor (hereinafter abbreviated as MOS transistor) 38 people and 30B are used. Current detection can be achieved by connecting resistor 7 in series with voltage source 1 and detecting the voltage across the resistor. ). This detected voltage vla determination circuit 6
sent to. The control circuit 5 includes a counter 8 and a decoder 9, and the counter 8 has an input terminal 10.

!!3図に第2図の実施例における各部の代表的波形で
ある。クロックパルスCP1i入力端子11に与えられ
る。信号81n端子lOに与えられるキャリパルスであ
り、このパルスの到来毎にカウンタ8の内容が1ずつ増
加(あるいに減少コし、デコーダ9の出力信号Gl、G
2が変わる。
! ! FIG. 3 shows typical waveforms of each part in the embodiment of FIG. 2. A clock pulse CP1i is applied to the input terminal 11. This is a carry pulse given to the signal 81n terminal IO, and each time this pulse arrives, the contents of the counter 8 increase (or decrease) by 1, and the output signals Gl, G of the decoder 9
2 changes.

信号1iti2rtゲ一ト回路13及びフリップ7aツ
ブ回路14を、それぞれ流れる電流である。
These are currents flowing through the signal 1iti2rt gate circuit 13 and the flip 7a block circuit 14, respectively.

時刻toにおいてはカウンタ8の内容がOとなっており
、このとき出力Gl、G2共0レベル(OV)であり%
スイッチ30A、308rXオフで開放状態である。ゆ
えにこのとき回路に流れるttv、aOであり、信号v
1にa回路13.14に流れる電流は表わtlない。時
刻tl でキャリパルスS1が1個加えられるとカウン
タはその内容を1だけ増やし、信号Glがルベル(数V
)となり、スイッチ30Aは閉状態となる。とれてより
、回路13が動作し、電Ritが抵抗7に流れ、これは
電圧v1となって判定回路6に送り込まれる。判定回路
ではカウンタ8よりの信号を参照して電流11が回路1
3の正常動作の電流波形かどうかを判定して(ゲート回
路の場合にクロックに同規して図中11のパルス電流が
流れる)合否判定信号NGを発生する。
At time to, the content of the counter 8 is O, and at this time, the outputs Gl and G2 are both at 0 level (OV) and %
When the switches 30A and 308rX are off, they are in an open state. Therefore, at this time, ttv and aO flowing in the circuit, and the signal v
1, the current flowing through the a circuits 13 and 14 is expressed as tl. When one calipulse S1 is added at time tl, the counter increments its contents by 1, and the signal Gl becomes level (several V).
), and the switch 30A is closed. As a result, the circuit 13 operates, and the electric current Rit flows through the resistor 7, which becomes voltage v1 and is sent to the determination circuit 6. The determination circuit refers to the signal from the counter 8 and determines whether the current 11 is in circuit 1 or not.
It is determined whether the current waveform is normal operation (in the case of a gate circuit, a pulse current 11 in the figure flows in synchronization with the clock) and a pass/fail determination signal NG is generated.

時刻t!において@2のキャリパルスが加わると今[t
lG I K代って02がルベルとなりスイッチ30B
を閉状態とする。それゆえ、時刻t2以降はフリップ7
aツブ回路特有の電流iz (クロック信号CPIの同
期の172のパルス状′を流涙形)が抵抗7に流れこれ
を、判定回路6で判定する。
Time t! When a cali pulse of @2 is added at , now [t
02 becomes Lebel instead of lG IK and switch 30B
is closed. Therefore, after time t2, flip 7
A current iz (172 pulses in synchronization with the clock signal CPI in a lachrymal shape) peculiar to the a-tub circuit flows through the resistor 7 and is judged by the judgment circuit 6.

但し、この場合にクロックパルスCPIがゲート回路1
3を通してフリップ7aツブ14に与えられないので、
別の平段でこのパルスを与える必要がある。例えば、図
中点線の配線を行っておき、別のクロックパルスCP2
を与える等の手段である。
However, in this case, the clock pulse CPI is
Since it is not given to the flip 7a knob 14 through 3,
It is necessary to give this pulse in a separate platen. For example, if the wiring indicated by the dotted line in the figure is done, another clock pulse CP2
It is a means of giving.

本実施例では相当複雑な回路でも実施できる特長がある
This embodiment has the advantage that it can be implemented even with a fairly complicated circuit.

第4図は本考案の別の実施例である。この例に回路15
,16.17.18をその電源側と接地側とで選択して
おり、スイッチ30A、30B。
FIG. 4 shows another embodiment of the invention. In this example, circuit 15
, 16, 17, and 18 are selected on their power supply side and ground side, and switches 30A and 30B.

40A、40Bがこの選択の機能を果す。例えば回路1
6を選択したい場合は端子31Aのゲート信号C8Iを
ルベルとしてスイッチ30Aを閉じ、端子41Aのゲー
ト[号CG1もルベルトしてスイッチ40Aを閉じ、回
路15に電圧を与える。この状態としておけば回路15
のみが動作状態となり、検査を行うたとができる。この
実施例でに回路の規模が大きくなった場合スイッチ、制
御回路の規模を少なくできるとの効果がある。
40A and 40B perform this selection function. For example, circuit 1
If it is desired to select 6, the gate signal C8I of the terminal 31A is used as a rubel to close the switch 30A, and the gate CG1 of the terminal 41A is also made a rubel to close the switch 40A and apply voltage to the circuit 15. In this state, circuit 15
It is possible to say that the only one is in an operating state and that an inspection has been performed. This embodiment has the advantage that when the scale of the circuit becomes large, the scale of the switch and control circuit can be reduced.

第5図に本考案の更に別の実施例を示T0本実施例では
回路選択用のスイッチを特に設けず既存の被検査回路の
一部の素子を用いて実現する。図においてこれまでの回
路2A、2B、・・・、2Z*MO8)ランラスタ2A
A、3A人、28B、3BB、・・・、・・・、2ZZ
、3ZZで構成される。このような回路は通常のMO8
IC,MO8LSI等の内部でよく用いられる。図にお
いてMOSトランジスタ3AA、38B、−,3ZZ等
1’!MO8トランジスタ2AA、28B、・・・、2
ZZ等の負荷用として動作し、通常負荷MOSトランジ
スタと呼ばれている。このトランジスタに図の点線のよ
うに電源側に結ばれて動P):fるが、本案では電源に
結ぶ前例端子20A、20B、・・・、202に選択用
の信号(これまでのGl、G2に相当する)を加え、こ
れまで通りの検査を実施し然る後に電源側に結ぶという
方法をとる。この方法でクスイッチを新たに設ける必要
がなくなる。
FIG. 5 shows still another embodiment of the present invention. In this embodiment, a circuit selection switch is not particularly provided, and the circuit is realized using some elements of an existing circuit to be tested. In the figure, the circuits 2A, 2B, ..., 2Z*MO8) Run raster 2A
A, 3A people, 28B, 3BB, ..., ..., 2ZZ
, 3ZZ. Such a circuit is a normal MO8
Often used inside ICs, MO8LSIs, etc. In the figure, MOS transistors 3AA, 38B, -, 3ZZ, etc. 1'! MO8 transistor 2AA, 28B,..., 2
It operates as a load such as ZZ and is usually called a load MOS transistor. This transistor is connected to the power supply side as shown by the dotted line in the figure, and in this case, the terminals 20A, 20B, ..., 202 connected to the power supply are connected to select signals (Gl, (corresponding to G2), perform the same inspection as before, and then connect it to the power supply side. This method eliminates the need to provide a new switch.

第6図に本考案の更に他の実施例を示T0この場合は回
路36A、36B1’!同一であり、回路上に並列の接
続となっている。スイッチ35A、35Bのいずれかを
閉じて検査する手法はこれまでと同じであるが、本実施
例ではこの検査の結果をふまえて、若し、36A、36
Bのどちらかが不良と判定された場合に、スイッチを常
に開状態として良品のみを使用することを特長としてい
る。例えば、36Aが正常、36Bが不良と判定された
場合にデコーダ回路9を制御して出力信号を設定してG
Al″11レベル、GB#’lOレベルとして固定し、
以後t’1t36Aのみを活用する。
FIG. 6 shows yet another embodiment of the present invention T0 in this case circuits 36A, 36B1'! They are identical and connected in parallel on the circuit. The method of testing by closing either switch 35A or 35B is the same as before, but in this embodiment, based on the results of this test, if 36A or 36
The feature is that if either one of B is determined to be defective, the switch is always open and only non-defective products are used. For example, if 36A is determined to be normal and 36B is determined to be defective, the decoder circuit 9 is controlled and the output signal is set.
Fixed as Al''11 level, GB#'1O level,
From now on, only t'1t36A will be used.

この方法にゲートアレイ等の回路に冗長ヰのある場合に
有効であり、同じ回路を2個並列にすることを必らずし
も必要としない。つまり、正常に動作している回路のみ
を用いて全体回路を構成できる特長を持ち得る。
This method is effective when there is redundancy in a circuit such as a gate array, and it is not necessarily necessary to connect two identical circuits in parallel. In other words, it has the advantage that the entire circuit can be configured using only normally operating circuits.

第7図に本考案の更に別の実施例を示す。この例でに回
路2A、2Bを活すのに特別の工夫をとっており、これ
までの実施例でに回路に対して電気的に動作のための入
力信号を加えていたが、この場合に光を用いて信号を加
える。ダイオード70A、70Bに発光用であり、これ
より放射された光束a仝闇を介して回路2A、2Bに加
えられる。通常回路2A、28μトランジスタ61゜6
2等のアクティブ素子を會んでいるのでこの接合に九を
照射丁れは外部よりりaツク等の信号を与えることがで
きる。この方法に入力信号印加のための特別な回路をI
C内に包含しなくともよいので回路構成が藺単になる。
FIG. 7 shows yet another embodiment of the present invention. In this example, special measures have been taken to utilize circuits 2A and 2B, and in the previous examples, input signals for electrical operation were added to the circuits, but in this case, Add signals using light. The diodes 70A and 70B are used for light emission, and the luminous flux a emitted from the diodes 70A and 70B is applied to the circuits 2A and 2B through the darkness. Normal circuit 2A, 28μ transistor 61°6
Since active elements such as 2 are connected, a signal such as ``a'' can be applied to this junction from the outside. This method requires a special circuit for input signal application.
Since it does not need to be included in C, the circuit configuration becomes simple.

〔発明の効果〕〔Effect of the invention〕

本発明によれば半導体電子回路内部を比較的簡単な回路
構成で検査診断できるので半導体素子の信穎度を上げ、
経済的にも多大の効果がある。
According to the present invention, the inside of a semiconductor electronic circuit can be inspected and diagnosed with a relatively simple circuit configuration, thereby increasing the reliability of semiconductor elements.
It also has great economic effects.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図に本発明の半導体電子回路の原理説明図、第2図
に本発明の半導体電子回路の実施例の回路図、第3図に
第2図の回路における代浅的波形説明図、第4図、第5
図、第6図、第7図にそれぞれ本発明の半導体電子回路
の他の実施例の回路図である。 l・・・電圧源、2人・・・回路、3人・・・スイッチ
、4・・・第 1 図 〆5 3A・・スイ1+ 4・電人&trgJ路
FIG. 1 is an explanatory diagram of the principle of the semiconductor electronic circuit of the present invention, FIG. 2 is a circuit diagram of an embodiment of the semiconductor electronic circuit of the present invention, FIG. Figure 4, 5th
6 and 7 are circuit diagrams of other embodiments of the semiconductor electronic circuit of the present invention, respectively. l...voltage source, 2 people...circuit, 3 people...switch, 4...Fig.

Claims (1)

【特許請求の範囲】[Claims] 1、半導体電子回路において、回路を幾つかに分割し、
その一部を該幾つかに分割された回路に直列に設けたス
イッチを制御回路よりの信号によって開閉せしめること
で動作せしめ、電圧源に流れる電流を検出回路により検
出し、その波形より該分割された回路の試験、診断、修
複を行うように構成したことを特徴とする半導体電子回
路。
1. In semiconductor electronic circuits, the circuit is divided into several parts,
A part of the voltage source is operated by opening and closing a switch connected in series with the divided circuit in response to a signal from the control circuit, and the current flowing through the voltage source is detected by the detection circuit, and the waveform of the divided circuit is detected by the detection circuit. A semiconductor electronic circuit characterized in that it is configured to test, diagnose, and repair a circuit.
JP61121090A 1986-05-28 1986-05-28 Semiconductor electronic circuit Pending JPS62278473A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61121090A JPS62278473A (en) 1986-05-28 1986-05-28 Semiconductor electronic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61121090A JPS62278473A (en) 1986-05-28 1986-05-28 Semiconductor electronic circuit

Publications (1)

Publication Number Publication Date
JPS62278473A true JPS62278473A (en) 1987-12-03

Family

ID=14802623

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61121090A Pending JPS62278473A (en) 1986-05-28 1986-05-28 Semiconductor electronic circuit

Country Status (1)

Country Link
JP (1) JPS62278473A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6239604B1 (en) 1996-10-04 2001-05-29 U.S. Philips Corporation Method for inspecting an integrated circuit by measuring a voltage drop in a supply line of sub-circuit thereof
US7812628B2 (en) 2006-12-13 2010-10-12 Renesas Electronics Corporation Method of on-chip current measurement and semiconductor IC

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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