JPS63313080A - Logic device - Google Patents

Abstract

PURPOSE:To detect whether or not a current leaks from an input buffer circuit by taking a measurement only once by connecting inputs of plural buffer circuits electrically in response to a signal from a test mode signal generator. CONSTITUTION:Signal output lines 6 of input buffer circuits composed of transistors (TR) 5 are connected to plural inputs of a logic circuit 10. When an input buffer circuit is tested, a test mode signal is supplied from a test mode signal generator 7. Transmission gates 9 consisting of N channel TRs and P channel TRs are connected among the signal input lines 1a-1n of the input buffer circuits and turned on throughout a test mode in response to the test mode signal from the test mode signal generator 7. At this time, the input signal lines 1a-1n are connected in parallel to one another, so whether or not there is a leak current is measured as to one optional input of the input buffer circuits, thereby knowing whether or not there is abnormality in a leak current test of all input buffer circuits.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic device, and particularly to a test circuit for an input buffer circuit.

[Prior Art] FIG. 2 shows an input buffer circuit including a conventional protection circuit for a logic integrated circuit, which is published, for example, on page 119 of the Mitsubishi Semiconductor Reliability Handbook (3rd edition). In the figure, 1a to 1n are signal input lines of the input buffer circuit, 2 is a @wearing resistor, 3 and 4 are protective clamp diodes, 5 is a transistor constituting an input cover sofa,
Reference numeral 6 indicates a signal output line of the input buffer circuit, and reference numeral 10 indicates a logic circuit.

Next, the operation will be explained. In conventional testing of logic integrated circuits, as one means of testing whether the components of the input buffer circuit function correctly, an LSI tester is used to measure the steady state as seen from each signal input line 1a to 1n. A method is used to detect the presence or absence of leakage current. For example, if the signal input line 1a is V, level or higher and VC
When a voltage below the level is applied, there will be no IR current flowing into or flowing out from the signal input line 1a if the components of the input buffer circuit are normal.

However, if there is any failure or abnormality in the components of the input buffer circuit, this can be detected as a leakage current seen from the signal input line 1a.

Generally, a logic integrated device has a plurality of signal input lines 1a to 1.
To detect leakage current, the above test is repeated in order for each signal input line 1i11a to 1o, but if leakage current is detected for at least one signal input line, then Since logic integrated circuits can be considered defective, the normal procedure is to end the test when the first leakage current is detected. Therefore, in order to know that the logic integrated circuit to be tested is a good product with respect to the leakage current test, it is necessary to detect the leakage iI current for all n signal input lines.

[Problems to be Solved by the Invention] Conventional logic device circuits and their testing methods are performed as described above, and therefore are equipped with only one or several ammeters for measuring leakage current. Popular type SI
How to use an LSI tester to perform tests using a tester?
! ! Switch the connection of the flow meter and connect each signal input line 1a to 1n.
This method has the problem of requiring a large amount of work and therefore a large amount of labor and time since the measurements must be repeated.

This invention was made to solve the above-mentioned problems, and in a logic integrated circuit equipped with a plurality of input buffer circuits, it is possible to determine the presence or absence of stagnation If current in all input buffer circuits with just one measurement. The objective is to obtain a logical device capable of detecting.

[Means for Solving the Problems] This logic device according to Marumei has an input buffer between the respective inputs of a plurality of input buffer circuit means connected to a plurality of inputs of a logic circuit means that performs a logic operation. A switching means is provided which becomes conductive in response to a signal from a test mode signal means of the buffer circuit means.

[Operation] The logic device according to the present invention provides a signal between the inputs of the plurality of input buffer circuit means connected to the plurality of inputs of the logic circuit means that performs a logical operation from the test mode signal means of the input buffer circuit means. When testing the input buffer circuit means, the switching means conducts between the respective inputs of the input buffer circuit means in response to the test mode signal. By measuring the presence or absence of leakage current for any single input buffer circuit means, it is possible to know whether there is an abnormality in the wetting current test of all input buffer circuit means, and the labor of the operator can be reduced. It becomes possible.

[Embodiment of the Invention] FIG. 1 is a diagram of an input buffer circuit including a protection circuit for a logic integrated circuit showing an embodiment of the invention. In the figure, 1a to 1n and 2 to 6 are the same as the conventional one shown in FIG. 2, and their explanation will be omitted. In FIG. 1, 7 is a test mode signal generator, 8 is an inverter, and 9 is an N
This is a transmission gate composed of a channel transistor and a P-channel transistor.

Next, the operation will be explained. First, the signal from the test mode signal generator 7 is set to H level to set the test mode. At this time, the N-channel transistor and the P-channel transistor constituting the transmission gate 9 are both in a conductive state, so that the input signals 1a to 1n of the input buffer circuit are connected in parallel with each other. Next, 1a
to 1n, for example, connect any one input line 1a to V
level, connect an LSI tester, and check for steady leakage. Next, the voltage is set to Vc level, and the presence or absence of leakage current is similarly checked.

If there is a leakage current in at least one input buffer circuit, it should be detected in the above measurement, and if it is not detected, it can be determined that the measuring device is good for the wetting current test.

[Effects of the Invention] As described above, according to the present invention, the test mode signal of the input buffer circuit means is connected between the respective inputs of the plurality of input buffer circuit means connected to the plurality of inputs of the logic circuit means. Since the switching means is provided to conduct in response to a signal from the means, the amount of work required to test the leakage current of the input buffer circuit means is reduced, thereby reducing the labor and time of the operator.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an input section of a conventional logic device. In the figure, 1a to 1n are signal input lines of the input buffer circuit, 2 is a protective resistor, 3 and 4 are clamp diodes, 5 is a transistor constituting an input cover sofa, and 6
1 is a signal output line of the input buffer circuit, 7 is a test mode signal generator, 8 is an inverter, 9 is a transmission gate, and 10 is a logic circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (2)

[Claims] (1) logic circuit means for performing a logical operation and having a plurality of inputs; a plurality of input buffer circuit means connected to the plurality of inputs of the logic circuit means and each having an input; a logic device comprising means for providing a test mode signal during testing of input buffer circuit means; and switching means connected between said inputs of said input buffer circuit means and conducting during said test mode in response to said test mode signal. . (2) The switching means includes a parallel circuit of a first switching element and a second switching element that operate in response to mutually opposite phase inputs, and the means for providing the test mode signal is configured to receive the test mode signal. 2. The logic device according to claim 1, further comprising means for rendering both said first and second switching elements conductive when .