JPS62277883A - Video signal processing circuit - Google Patents

Abstract

PURPOSE:To simplify a circuit constitution by using a frequency characteristic adjustment and phase compensation circuit so as to apply frequency characteristic adjustment and phase compensation of a trap circuit thereby making a phase compensation circuit and a frequency characteristic adjusting circuit in common. CONSTITUTION:A luminance signal is fed to a subcarrier trap circuit 25 and the output of the trap circuit 25 is fed to a frequency characteristic adjustment and phase compensation circuit 27 including a gain control amplifier. A frequency characteristic adjusting and phase compensation circuit 27 has a flat gain characteristic and a delay characteristic to apply the phase compensation of the trap circuit 25 at recording and the phase compensation of the trap circuit 25 at recording is applied. The circuit 27 applies charpness control at reproduction and the phase compensation to the trap circuit 25. Thus, the frequency characteristic adjustment circuit and the phase compensation circuit for the sharpness control are used in common thereby reducing the circuit scale.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a video signal processing circuit suitable for use, for example, in frequency characteristic adjustment and phase compensation of a VTR.

[Summary of the invention]

In a video signal processing circuit suitable for use, for example, in frequency characteristic adjustment and phase compensation of a VTR, the present invention supplies a luminance signal to a trap circuit for suppressing subcarriers, and uses the output of this trap circuit to adjust frequency characteristics including a gain control amplifier. This frequency characteristic adjustment and phase compensation circuit adjusts the frequency characteristics for sharpness control, for example, and also performs phase compensation for the trap circuit, thereby simplifying the circuit configuration and increasing integration. This is to make it easier.

[Conventional technology]

In conventional VTRs, as shown in FIGS. 7 and 8, in order to suppress chroma signal components remaining in the separated luminance signal during recording, unnecessary signal components contained in the reproduced luminance signal are suppressed during reproduction. In order to suppress this, a trap circuit whose center frequency is the color subcarrier frequency fsc is provided.

In other words, FIG. 7 shows the configuration of a conventional VTR during recording. In FIG. 7, for example, N
A TSC composite color video signal is supplied, and this color video signal is separated into a luminance signal Y and a chroma signal C by a comb filter 302. Separated luminance signal Y
is supplied to the trap circuit 303, and the chroma signal C is supplied to the chroma signal processing circuit 301. A chroma signal processing circuit 301 converts the chroma signal C into a low frequency converted chroma signal of, for example, 74.3 K11z.

The trap circuit 303 is a trap circuit whose center frequency is the color subcarrier frequency fsc, for example, 3.58 Ml(z).The chroma signal component remaining in the luminance signal separated by the trap circuit 303 is suppressed.

By the way, as shown in FIG. 9, the characteristics of the trap circuit 303 are such that the gain becomes minimum at the frequency fsc, and the delay characteristics become non-linear near the frequency fsc. Therefore, it is necessary to perform nine-phase compensation to compensate for the delay characteristics. Note that in FIG. 9, G indicates gain characteristics, and D indicates delay characteristics.

The output of the trap circuit 303 is supplied to a phase compensation circuit 304. The phase compensation circuit 304 compensates for the delay characteristics of the trap circuit 303.

The phase compensation circuit 304 has a flat gain characteristic and a delay characteristic that compensates for the delay characteristic of the trap circuit 303. As this phase compensation circuit 304, for example, one shown in Japanese Patent Application No. 60-9266 can be used.

The output of the phase compensation circuit 304 is supplied to the FM modulation circuit 307 via the clamp circuit 3.5 and the emphasis circuit 306. The FM modulation circuit 307 performs FM modulation on the luminance signal Y, and the FM modulated luminance signal is supplied to the mixing circuit 308 . The mixing circuit 308 includes a chroma signal processing circuit 301
A low frequency converted chroma signal is supplied. Mixing circuit 308
The FM-modulated luminance signal and the low-frequency converted chroma signal are frequency-division multiplexed. The output of the mixing circuit 308 is supplied to the rotary head 310 via a recording amplifier 3091 rotary transformer (not shown) and recorded on the magnetic tape.

FIG. 8 shows the configuration during playback. In FIG. 8, a reproduced FM modulated luminance signal is supplied to the input terminal 311,
A reproduced low frequency converted chroma signal is supplied to an input terminal 312 . The reproduced FM modulated luminance signal supplied to the input terminal 311 is supplied to the FM demodulation circuit 313 and is FM demodulated.

The demodulated luminance signal Y is supplied to a square filter 315 via a de-emphasis circuit 314, and the output of the comb filter 315 is supplied to a trap circuit 316. The comb filter 315 and the trap circuit 316 This is provided to remove unnecessary components included in the signal.In other words, since the luminance signal Y does not include the chroma signal component, the signal in the band of the chroma signal component included in the reproduced luminance signal is These unnecessary noises are caused by the comb filter 315 and the trap circuit 316.
will be removed.

The trap circuit 316 is a trap circuit whose center frequency is the color subcarrier frequency rsc.

As mentioned above, the delay characteristics of this trap circuit 316 are non-linear, so it is necessary to compensate for the delay characteristics.

The output of the trap circuit 316 is supplied to a phase compensation circuit 317, and phase compensation for the delay characteristics of the trap circuit 316 is performed. The output of the phase compensation circuit 317 is supplied to a sharpness control circuit 319 via a noise canceller 318. The sharpness control circuit 319, for example,
By raising the high-frequency component of z, the edges of the video signal are emphasized and the outline is emphasized. If this sharpness control is performed too strongly, the S/N ratio will deteriorate. Therefore, the sharpness ill 711 amount can be adjusted by a control signal from the terminal 320.

The output of the sharpness control circuit 319 is the yc7H combination circuit 3
21. On the other hand, the low frequency converted chroma signal from the input terminal 312 is supplied to the chroma signal processing circuit 322,
3. Color subcarrier frequency from low-pass converted chroma signal.
58 MHz chroma signal. This chroma signal C is supplied to a YC't';: combination circuit 321. yc
The mixing circuit 321 mixes the H degree signal Y and the chroma signal C, and the output thereof is taken out from the output terminal 323.

By the way, in the conventional VTR described above, the comb filter 302, the comb filter 315, and the trap circuit 303
The trap circuit 316, the phase compensation circuit 304, and the phase compensation circuit 317 can each have similar configurations. Therefore, if these are made common and used selectively during recording and reproduction, the circuit configuration can be simplified.

[Problem that the invention seeks to solve]

As described above, in the conventional VTR, after the phase compensation circuit 317 compensates for the delay characteristics of the trap circuit 316 during playback, the sharpness control circuit 319 performs sharpness control. This sharpness control circuit 31
As mentioned above, 9 is a frequency characteristic adjustment circuit that increases the gain of, for example, 2 MHz. Conventionally, the frequency characteristic adjustment circuits used as the sharpness control circuits 3 and 9 cannot set their delay characteristics appropriately.

If it is possible to use a sharpness control circuit 319 that can obtain constant delay characteristics no matter how the frequency characteristics are set, this can perform phase compensation of the trap circuit 316, and the phase compensation circuit 317 and sharp male control By making the circuit 319' common, the circuit configuration can be changed to N@.

Therefore, it is an object of the present invention to provide a video signal processing circuit in which a phase compensation circuit and a frequency characteristic adjustment circuit are shared, and the circuit configuration can be simplified.

[Means for solving problems]

This invention supplies a luminance signal to a trap circuit 25 for subcarrier suppression, supplies the output of the trap circuit 25 to a frequency characteristic adjustment and phase compensation circuit 27 including a gain control amplifier, and supplies the output of the trap circuit 25 to a frequency characteristic adjustment and phase compensation circuit 27 that includes a gain control amplifier.
This is a video signal processing circuit configured to perform frequency characteristic adjustment in step 7 and also perform phase compensation of the trap circuit 25.

[Effect]

As the frequency characteristic adjustment and phase compensation circuit 27, a circuit whose delay characteristic is approximately constant even if its frequency characteristic is varied is used. During recording, the frequency characteristic adjustment and phase compensation circuit 27 has a flat gain characteristic and a delay characteristic that compensates the phase of the trap circuit 25. Thereby, phase compensation of the trap circuit 25 during recording is performed.

During playback, is the frequency characteristic adjustment and the gain characteristic of the phase compensation circuit 27 set to sharpness? ff1l It is varied according to ffi. The frequency characteristic adjustment and phase compensation circuit 27 is
Even if the frequency characteristics are varied, the phase characteristics remain approximately constant. Therefore, during playback, sharpness control is performed by the frequency characteristic adjustment and phase compensation circuit 27, and
Phase compensation for the trap circuit 25 is performed.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. This one embodiment is done according to the following order.

a, Configuration of one embodiment, Frequency characteristic adjustment and phase compensation circuit in one embodiment C1 Specific configuration of frequency characteristic adjustment and phase compensation circuit d, Specific configuration of switch circuit, fixed current and variable current circuit 5gm control circuit a, Configuration of one embodiment In this embodiment, sharpness control and phase compensation of the trap circuit are performed using a frequency characteristic adjustment and phase compensation circuit shown in FIG. This frequency characteristic adjustment and phase compensation circuit can obtain constant delay characteristics and phase characteristics no matter how the frequency characteristics are set. The specific structure of this frequency characteristic adjustment and phase compensation circuit will be described in detail later.

FIG. 1 shows an embodiment of the present invention.

In FIG. 1, 21 and 22 are switch circuits that can be switched between recording and reproduction. During recording, the terminals 21A and 21B of the switch circuit 21 are connected, and the terminals 22A and 22B of the switch circuit 22 are connected.

During playback, the terminal 21C of the switch circuit 21 and the terminal 21
B is connected, and the terminal 22C of the switch circuit 22 and the terminal 2
2B is connected.

During recording, a composite color video signal of, for example, the NTSC system is supplied to the input terminal 23, and this color video signal is supplied to the comb filter 24 via the switch circuit 21.

A comb filter 24 separates this color video signal into a luminance signal Y and a chroma signal C. The separated luminance signal Y is supplied to a trap circuit 25, and the chroma signal C is supplied to a chroma signal processing circuit 26. The chroma signal processing circuit 26 converts the chroma signal C into a low frequency converted chroma signal of, for example, 743 KHz.

The trap circuit 25 is a trap circuit whose center frequency is the color subcarrier frequency, for example, 3.58 MHz.

The chroma signal component remaining in the luminance signal separated by the trap circuit 25 is suppressed.

The output of the trap circuit 25 is supplied to a frequency characteristic adjustment and phase compensation circuit 27. During recording, a fixed current from a fixed current circuit 28 is supplied to the frequency characteristic adjustment and phase compensation circuit 27 via the switch circuit 22. and,
Due to the fixed current of the fixed current circuit 28, the frequency characteristic adjustment and phase compensation circuit 27 has characteristics such that its gain characteristic is flat and its delay characteristic compensates for the delay characteristic of the trap circuit 25. That is, the gain characteristic is flat, and the delay characteristic is, for example, the center frequency fo (f
o ~3.58 M)+2), Q is 0.5 ~
0°6, the center frequency of the equalizer is 3. It is set to about OMIIz.

The delay characteristic of the trap circuit 25 is compensated by the frequency characteristic adjustment and phase compensation circuit 27. The output of the frequency characteristic adjustment and phase compensation circuit 27 is connected to the clamp circuit 31. The signal is supplied to an FM modulation circuit 33 via an emphasis circuit 32.

The luminance signal Y is FM modulated in the FM modulation circuit 33, and this F
The M-modulated luminance signal is supplied to a mixing circuit 34. The mixing circuit 34 is supplied with a low frequency converted chroma signal from the chroma signal processing circuit 26 . The FM modulated luminance signal and the low-frequency converted chroma signal are frequency division multiplexed in the mixing circuit 34, and the output of the mixing circuit 34 is sent to the recording amplifier 355.
The signal is supplied to a rotating head 36 via a rotating transformer (not shown) and recorded on a magnetic tape.

During reproduction, the input terminal 37 is supplied with a reproduced FM modulated luminance signal, and the input terminal 38 is supplied with a reciprocated low-frequency converted chroma signal.

The reproduced FM modulated luminance signal from the input terminal 37 is supplied to the FM demodulation circuit 39, and the luminance signal Y is demodulated. This luminance signal Y is supplied to a comb filter 24 via a de-emphasis circuit 40° switch circuit 21. The output of the comb filter 24 is supplied to a trap circuit 25. The comb filter 24 and the trap circuit 25 remove unnecessary noise in the chroma signal component band included in the reproduced luminance signal.

The output of the trap circuit 25 is supplied to a frequency characteristic adjustment and phase compensation circuit 27. During reproduction, a variable current from a variable current circuit 29 is supplied to the frequency characteristic adjustment and phase compensation circuit 27 via the switch circuit 22. A sharpness control signal is supplied to the variable current circuit 29 from a terminal 30. The current straightness of the variable current circuit 29 is controlled by this sharpness control signal. The frequency characteristics of the frequency characteristic adjustment and phase compensation circuit 27 are changed by this current value. As a result, the high frequency components of, for example, 2 and 1z are lifted, and sharpness control is performed.

Note that if this sharpness control is applied too strongly, the S/
The N ratio deteriorates. Therefore, it is necessary to set this sharpness control to an appropriate strength using a sharpness control signal from the terminal 30. At the same time, the delay characteristic and phase characteristic of the trap circuit 25 are compensated by the frequency characteristic adjustment and phase compensation circuit 27. As described above, even if the frequency characteristics of the frequency characteristic adjustment and phase compensation circuit 27 are changed, the delay characteristics thereof hardly change. Therefore, the frequency characteristic adjustment and phase compensation circuit 27 can compensate for the delay characteristic of the trap circuit 25, and also change the frequency characteristic according to the sharpness intensity to perform sharpness control.

The output of the frequency characteristic adjustment and phase compensation circuit 27 is connected to the clamp circuit 31. The signal is supplied to a YC mixing circuit 42 via a noise canceller 41. On the other hand, the chroma signal from the input terminal 38 is supplied to the chroma signal processing circuit 43, and the reproduced low-frequency converted chroma signal has a color subcarrier frequency of 3.58 M.
llz chroma signal. This reproduced chroma signal is supplied to the YC mixing circuit 42. The detection signal Y and the chroma signal C are mixed in the YC mixing circuit 42, and the output thereof is derived from the output terminal 44.

In this way, in this embodiment, during recording and playback,
Comb filter 24. By making the trap circuit 25 common, the circuit size can be reduced, and by having the frequency characteristic adjustment and phase compensation circuit 27 perform sharpness control and phase compensation, the circuit size can be further reduced. It is.

b. Frequency characteristic adjustment and phase compensation circuit in one embodiment As described above, in this one embodiment, sharpness control and phase compensation of the trap circuit are performed by the frequency characteristic adjustment and phase compensation circuit 27. FIG. 2 shows the configuration of this frequency characteristic adjustment and phase compensation circuit.

In FIG. 2, numerals 1, 2, and 3 are amplifiers each having a basic configuration of a differential circuit. The amplifier 1 is configured such that its mutual contactance gm can be arbitrarily set by the output of the gm control circuit 4.

Non-inverting input terminals of amplifier 1 and amplifier 2 are connected to input terminal 5, and amplifier 1. Amplifier 2. When the inverting input terminal of the amplifier 3 is connected to the output terminal 8, the inverting output terminal of the amplifier 1 is connected to the output terminal 8.

A non-inverting output terminal of amplifier 2 is connected to a non-inverting input terminal of amplifier 3, and a non-inverting output terminal of amplifier 3 is connected to output terminal 8. A capacitor 6 is connected between the input terminal 5 and the output terminal 8. A capacitor 7 is connected between the non-inverting output terminal of the amplifier 2 and ground.

The gm control circuit 4 is configured to set the mutual conductance gm of the amplifier 1 based on its current value. A fixed current circuit 28 and a variable current circuit 29 are connected to the gm control circuit 4 via a switch circuit 22. When terminal 22B and terminal 22A of switch circuit 22 are connected, gm control circuit 4 and fixed current circuit 28 are connected. At this time, the mutual conductance gm of the amplifier 1 is kept constant.

When the terminals 22B and 22C of the switch circuit 22 are connected, the 'gm control circuit 4 and the variable current circuit 29 are connected. At this time, the mutual conductance gm of the amplifier 1 is arbitrarily set by varying the current of the variable current circuit 29.

The frequency characteristics of the frequency characteristic adjustment and phase compensation circuit 27 are varied by changing the mutual conductance gm of the amplifier 1 in this way. Even when the frequency characteristics are varied in this way, the delay characteristics hardly change. This will be explained below.

The transfer function of the frequency characteristic adjustment and phase complement m circuit 27 shown in FIG. 2 is determined as follows.

In Figure 2, the mutual conductance gm of amplifier 1 is 1/r:l, the mutual conductance gm of amplifier 2 is 1/r2, and the mutual conductance gm of amplifier 3 is 1/r:l.
/r1, the capacitance of capacitor 6 is 01, and the capacitance of capacitor 7 is 02. The input signal is Vin, the output signal is ■0, and the signal v at the intermediate point Y
When y, it is obtained as rz jωC2.

Therefore, Q and ω. is, ■style, ■2, ωo
”□...■ V C1r+C2r2.

However, it is assumed that r<r□.

Here, if we transform the formula 0, we get 1+jωczrz(1-)+(jω)”Car ICz
rzrko... ・■.

Equation 0 is: jωc, r2(1−−−) + (j (IJ)”
C1r+C2r2□...■ 1+j ωczrz(1--)+(jω)"cIr+c
zrz formula and jωczrz(12) □ ・ ・ ・■ 1+jωctrz (L ) + (jω)2C
+r+Czrz"1 It is expressed as the sum of the equation.The equation 0 shows the characteristics of an equalizer with a constant gain.The equation 0 shows the characteristics of a bandpass filter.Therefore, this frequency characteristic adjustment and The phase compensation circuit has characteristics that combine the characteristics of an equalizer and those of a bandpass filter.

If rs=2r+ (then the 0 formula becomes 0.

Therefore, at this time, it has the characteristics of only an equalizer.

When r is set to a large value, equation 0 takes a negative value. At this time, a dip occurs at the center frequency.

If C3 is set small, the value obtained by equation 0 becomes large, and the peak at the center frequency becomes large.

In this way, the frequency characteristics are set by changing the mutual conductance gm (gm=1/r3) of the amplifier l.

In other words, this frequency characteristic adjustment and phase compensation circuit
As shown in the equivalent block diagram in the figure, the large chi S number Vin is supplied to the equalizer 12 and the bandpass filter 13,
This is equivalent to adding the output of the equalizer 12 and the output of the bend bus filter 13 using the adder 14. In order to change the frequency characteristics of the bandpass filter 13, the terminal 1
When the mutual conductance 1/r of the amplifier 1 is changed by supplying a control signal to the bandpass filter 13, the delay characteristics of the bandpass filter 13 are changed. At this time, when the mutual conductance 1/r3 of the amplifier 1 is changed, the delay characteristic of the equalizer 12 changes so as to compensate for the delay characteristic of the bandpass filter 13. As a result, the output delay characteristics hardly change at all times.

Hereinafter, specific numerical values will be substituted to show the characteristics in each case, and it will be shown that the delay characteristics and phase characteristics are approximately constant.

FIGS. 4A to 4F show the respective characteristics in the cases shown in the table below. The Q of the circuit is determined by 'l+'2-r3, and the center frequency f0 is determined by rl and C2.

In this example, r.

is 3468Ω, C2 is 31050Ω, center frequency f0
is set to 2FIHz.

As is clear from the graphs shown in Figures 4A to 4F,
The delay characteristics and phase characteristics are approximately constant no matter how the frequency characteristics are changed by changing the mutual conductance gm (=1/r3>) of the amplifier 1.

Specific Structure of C0 Frequency Characteristic Adjustment and Phase Compensation Circuit FIG. 5 shows a specific structure when the frequency characteristic and phase compensation circuit 27 in an embodiment of the present invention is integrated into an integrated circuit. 6th
The figure shows that the characteristics of this frequency characteristic adjustment and phase compensation circuit 27 are switched between recording and reproduction, and during recording, the characteristics of the frequency characteristic adjustment and phase compensation circuit are kept constant using a constant current.
This is a specific configuration of the switch circuit 22 and fixed current circuit 28, the variable current circuit 29, and the gm control circuit 4, which adjust the frequency characteristics and vary the frequency characteristics of the phase compensation circuit using a variable current based on sharpness control during reproduction.

In FIG. 5, numerals 51, 52, and 53 are amplifiers each having a basic configuration of a differential circuit. These amplifiers 51-53 are of modified Gilbert type.

These amplifiers 5, 1, 52, and 53 correspond to amplifiers 1, 2, and 3 in FIG. 2 described above, respectively. Further, capacitors 54 and 55 in FIG. 5 correspond to capacitors 6 and 7 in FIG. 2, respectively.

The amplifier 51 is composed of transistors 56 and 57 whose emitters are commonly connected. transistor 56
and a transistor 58 whose emitter of 57 serves as a current source.
．． 59, and transistors 58', 5
The emitter of 9 is connected to the ground terminal 50 via a resistor 60.

The collector of the transistor 56 is connected to the collector of a PNP transistor 61 serving as a current source, and is also connected to one end of the capacitor 54.

The emitter of the transistor 61 is connected to +Vc through the resistor 62.
It is connected to the power supply terminal 49 of c. A collector of transistor 57 is connected to power supply terminal 49 .

The bases of the transistors 61 are commonly connected to the bases of the transistors 63, and this connection point is commonly connected to the bases of the transistors 199 in FIG. Ru. The collector of transistor 63 is connected to the collector of transistor 66, and transistor 67
connected to the base of The emitter of transistor 66 is connected to ground terminal 50 through a resistor. A collector of transistor 67 is connected to power supply terminal 49 . The emitter of the transistor 67 is connected to the ground terminal 5 via a resistor 69.
0, the emitter of transistor 67 and the base of transistor 66 are commonly connected, and this connection point is connected to the bases of transistors 58 and 59.

Transistors 63 and 61 are connected in a current mirror to transistor 199 in FIG.
The current flowing through transistor 99 determines the current flowing through transistor 63 and the current flowing through transistor 61. Further, the current flowing through the transistor 63 determines the current flowing through the transistor 66, and the current flowing through the transistors 58 and 59 which are connected to the transistor 66 in a current mirror manner. Therefore, transistor 19 in FIG.
As the current through transistor 9 changes, the current through transistor 61 and the current through transistors 58, 59 change.

The base of the transistor 56 is connected to the emitter of the transistor 71 via a resistor 70, and the diode 7
7 to the collector of a transistor 78 which operates as a current source. The emitter of transistor 78 is connected to ground terminal 50 via resistor 79. A collector of transistor 71 is connected to power supply terminal 49 . The base of the transistor 71 is connected to the other end of the capacitor 54, and is also connected to a PNP type transistor transmitter. The emitter of transistor 72 is connected to the collector of transistor 73 as a current source. The emitter of transistor 73 is connected to power supply terminal 49 via resistor 74 . A collector of transistor 72 is connected to terminal 50.

A non-inverting input of amplifier 51 is supplied to the base of transistor 56. This input is connected to emitter follower transistor 72. It is supplied via an emitter follower transistor 71. Transistor 73 drives emitter follower transistor 72. Transistor 78 drives eminota follower transistor 71. Amplifier 5
The inverting input of 1 is provided to the base of transistor 57.

The inverted output of amplifier 56 is taken from the collector of transistor 56. Transistor 61 operates as an active load.

The amplifier 52 is composed of transistors 81 and 82 whose emitters are commonly connected. transistor 81
The emitters of and 82 are connected to Tj, the collector of a transistor 83 as a current source.

The emitter of transistor 83 is connected to ground terminal 50 via resistor 84. The base of transistor 83 is connected to terminal 85.

A collector of transistor 81 is connected to power supply terminal 49 . The collector of transistor 82 is PN as a current source.
connected to the collector of P-type transistor 86, and
Connected to the base of transistor 87. A capacitor 55 is connected between the base of the transistor 87 and the connection tth. The emitter of transistor 86 is connected to power supply terminal 49 via resistor 88 .

The base of transistor 81 is connected to the base of transistor 56.゛The base of the transistor 82 is the resistor 89
is connected to the emitter of transistor 90 via diode 91, and to the collector of transistor 78 via diode 91. A collector of transistor 90 is connected to power supply terminal 49. The base of transistor 90 is connected to output terminal 92.

A non-inverting input of amplifier 52 is supplied to the base of transistor 81. Since the base of transistor 81 is commonly connected to the base of transistor 56, this input, like amplifier 51, is connected to emitter follower transistors 72 . It is supplied via an emitter follower transistor 71. The inverting input of the amplifier 52 is connected to the transistor 82.
supplied to the base of This input is provided via emitter follower transistor 90. The non-inverting output of amplifier 52 is taken from the collector of transistor 82. Transistor 86 operates as an active load.

The amplifier 53 is composed of transistors 93 and 94 whose emitters are commonly connected. The emitters of transistors 93 and 94 are connected to the collectors of transistors 95 and 96, which act as current sources. transistor 95
．． The emitter of 96 is connected to the ground terminal 50 via a resistor 97. The bases of transistors 95 and 96 are connected to terminal 8.
Connected to 5.

A collector of transistor 93 is connected to power supply terminal 49 . The collector of the transistor 94 is connected to the collector of a PNP type transistor 98 which operates as a current source and is read directly to the output terminal 92. transistor 9
It is connected to the power supply terminal 49 via a resistor 99 of 8.

The base of transistor 93 is connected through a resistor 100 to the emitter of transistor 87, and through a diode 101 to the collector of transistor 102 as a current source. The emitter of transistor 102 is connected to ground terminal 50 via resistor 103. The base of transistor 94 is connected to the emitter of transistor 105 via resistor 104, and the diode 10
6 to the collector of the transistor 102. A collector of transistor 105 is connected to power supply terminal 49. The base of transistor 105 is connected to output terminal 92.

A non-inverting input of amplifier 53 is supplied to the base of transistor 93. This input is provided via emitter follower transistor 87. The inverting input of amplifier 53 is supplied to the input terminal of transistor 94. This input is provided via emitter follower transistor 105. The non-inverted output of amplifier 53 is taken out from the collector of transistor 94. Transistor 98 operates as an active load.

Terminal 85 is connected to the base of transistor 107, and the emitter of transistor 107 is connected to ground terminal 50 via a resistor 108. The collector of transistor 107 is connected to the collector of transistor 109 and to the base of transistor 110. The emitter of the transistor 109 is connected to the power supply terminal 4 via the resistor 111.
Connected to 9. The base of transistor 109 is connected to transistor 73. Transistor 86. Commonly connected to the base of transistor 98. The emitter of transistor 110 is connected to power supply terminal 49 via resistor 112 and to the base of transistor 109. A collector of transistor 110 is connected to ground terminal 50.

A DC voltage Vr, for example 0.9V, is supplied to the terminal 85. This allows the transistor 8 to operate as a constant current source.
3. Transistors 95, 96. transistor 107
is driven. The current flowing through the transistor 107 drives the transistors 109, 110, and the transistors 73, 86, and 98 connected in a current mirror with the transistor 109, 110.

The bases of the transistors 78 and 102 are the transistor 11
Connected to the base of 3. The emitter of transistor 113 is connected to ground terminal 50 via resistor 114. The collector of transistor 113 is connected to terminal 106 via resistor 115 and to the base of transistor 118. The emitter of transistor 118 is connected to ground terminal 50 via resistor 17 and also to the base of transistor 113. transistor 1
18 collectors are connected to a power supply terminal 49.

A DC voltage Vrz is applied to the terminal 116, for example (4,2V-V■)
is supplied (■1 = voltage between base and emitter). This DC voltage causes a current to flow through the resistor 115, and as a result,
Transistor 113 and transistor 118 are driven. Then, due to the current flowing through the transistor 113,
A transistor 78 connected to this in a current mirror is driven.

121 is an input amplifier. This input amplifier 121 is
It is composed of two differential circuits: a differential circuit consisting of transistors 122 and 123, and a differential circuit consisting of transistors 124 and 125.

These two differential circuits are switched and used during recording and reproduction. The output of this input amplifier is taken out from emitter follower transistor 133. This output is fed back to the bases of transistors 123 and 125. Therefore, this input amplifier 121 is an amplifier with a gain of 1.

The emitters of transistors 122 and 123 are connected to the collector of transistor 126. transistor 12
The emitters of transistors 4 and 125 are connected to the collector of transistor 127. The emitters of transistors 126 and 127 are commonly connected, and this connection point is connected to ground terminal 50 via resistor 128. The base of transistor 126 is commonly connected to the base of transistor 167 in FIG. The base of transistor 117 is commonly connected to the base of transistor 169 in FIG.

The collector of transistor 122 and the collector of transistor 124 are commonly connected, and this connection point is connected to transistor 1.
31 collectors. The collectors of transistor 123 and transistor 125 are commonly connected, and this connection point is connected to the collector of transistor 132 and to the base of transistor 133. Also, a resistor 129 for phase compensation is connected between this connection point and the ground.
and a capacitor 130 are connected. transistor 13
1 and the base of transistor 132 are commonly connected, and this connection point is connected to the emitter of transistor 131. The emitter of transistor 131 is connected to power supply terminal 49 via resistor 134. transistor 132
The emitter of is connected to the power supply terminal 49 via a resistor 135.

A collector of transistor 133 is connected to power supply terminal 49. The emitter of transistor 133 is connected to the collector of transistor 136 as a current source, and is also connected to the base of transistor 72. Further, the base of the transistor 123 and the base of the transistor 125 are commonly connected, and this connection point is connected to the emitter of the transistor 133. The emitter of transistor 136 is connected to ground terminal 50 via resistor 137. The base of transistor 136 is transistor 78,102.113
Commonly connected to the base of

The base of the l-transistor 122 is connected to a terminal 139 via a resistor 138 and to an input terminal 141 via a resistor 140. A DC bias voltage of 2.5V, for example, is supplied to the terminal 139. transistor 12
4 is connected to the input terminal 141.

During recording, current is passed through transistor 127, and a differential circuit consisting of transistors 124 and 125 operates. At this time, the signal from the input terminal 141 is fed directly to the base of the transistor 124.

During reproduction, current is passed through transistor 126, and a differential circuit consisting of transistors 122 and 123 operates. At this time, the signal from the input terminal 141 is transmitted to the resistor 141.
The signal is attenuated and supplied to the base of the transistor 122.

During playback, sharpness control is performed, so the gain may reach the full range. Therefore, the input gain is changed during recording and playback to effectively obtain a dynamic range.

Regarding switching of transistors 126 and 127,
This will be explained later.

The input terminal 141 is supplied with the 1-variant signal output from the trap circuit 25 in FIG.
It is output from the emitter of 3. The output of the emitter follower transistor 133 is the emitter follower transistor 7
2.

A signal input to the base of the emitter follower transistor 72 is supplied from the emitter of the transistor 72 via the emitter follower transistor 71 to the base of the transistor 56 which is the non-inverting input terminal of the amplifier 51, and is also supplied to the non-inverting input terminal of the amplifier 52. It is supplied to the base of the transistor 81 which is a terminal. The output signal from the output terminal 92 is supplied to the base of a transistor 94 which is an inverting input terminal of the amplifier 53 via an emitter follower transistor 105, and is also supplied to the base of a transistor 94 which is an inverting input terminal of the amplifier 52 via an emitter follower transistor 90. 82 and the base of the transistor 57 which is the inverting input terminal of the amplifier 51. A capacitor 54 is connected between the collector of the transistor 56, which is the inverting output terminal of the amplifier 51, and the emitter of the emitter follower transistor 72, and the output of the collector of the transistor 56 is outputted to the output terminal 92. The output of the collector of the transistor 82, which is the non-inverting output terminal of the amplifier 52, is connected to the amplifier 3 via an emitter follower transistor 87.
The non-inverting input terminal of the transistor 93 is supplied to the base of the transistor 93. Between the collector of transistor 82 and ground,
A capacitor 55 is connected. The output of the collector of transistor 94, which is the non-inverting output terminal of amplifier 53, is supplied to output terminal 92.

Therefore, the circuit configuration consisting of these amplifiers 51, 52, 53 and capacitors 54, 55 is similar to the configuration shown in FIG.

The transconductance gm of amplifier 51 is determined by controlling the current flowing through transistor 61 and the current flowing through transistors 58 and 59.

This current is controlled by the current flowing through transistor 199 in FIG.

d, switch circuits, fixed current and variable current circuits.

In the specific configuration of the gm control circuit in FIG. 6, PNPN upper type transistors 151 and 15
The emitters of the two transistors are commonly connected, and this connection point is connected to the collector of the transistor 153. The base of transistor 151 is connected to terminal 139. This terminal 1
39 contains the base voltage Vg, for example 2. lV is supplied.

The base of transistor 152 is connected to terminal 140. The terminal 140 has a low level of, for example, 1.6■ during recording.
is supplied, and a high level, for example, 2.6■ is supplied during reproduction.

The emitter of transistor 153 is connected to power supply terminal 49 via resistor 154. The base of transistor 153 is connected to the base of transistor 155 and to the emitter of transistor 156. The emitter of the transistor 155 is connected to the power supply terminal 49 via the resistor 157.
connected to.

The emitter of transistor 156 is connected to power supply terminal 49 via resistor 158. The collector of transistor 155 is connected to the collector of transistor 159 and to the base of transistor 156. A collector of transistor 156 is connected to ground terminal 50.

The emitter of transistor 159 is connected to ground terminal 50 via resistor 160 . The base of transistor 159 is connected to the base of transistor 161 and to the emitter of transistor 162. A collector of transistor 162 is connected to power supply terminal 49.

The emitter of transistor 162 is connected to ground terminal 50 via resistor 163. The emitter of transistor 161 is connected to ground terminal 50 via resistor 165.

The collector of transistor 161 is connected via resistor 164 to terminal 116 to which DC voltage Vr2 is supplied.

This voltage Vr causes a current to flow through the resistor 164, and this current causes a current to flow through the transistor 161. This current causes a current to flow through the transistor 159 connected to the transistors 161 and 162 in a current mirror, and a current flows through the transistor 155.1-transistor 153.
Transistor 153 is activated.

The collector of transistor 151 is connected to the collector of transistor 167 and to the base of transistor 168. The collector of transistor 152 is connected to the collector of transistor 169 and to the base of transistor 170. transistor 1
The emitter of 67 is connected to the ground terminal 50 via a resistor 171. The emitter of the transistor 169 is the resistor 172
It is connected to the ground terminal 50 via. transistor 16
The collector of 8 is connected to the power supply terminal 49.

The emitter of transistor 168 is connected to ground terminal 50 via resistor 173 and to the base of transistor 167. A collector of transistor 170 is connected to power supply terminal 49.

The emitter of transistor 170 is connected to ground terminal 50 via resistor 174 and to the base of transistor 169.

During recording, a low level is supplied to the terminal 140. As a result, transistor 152 is turned on and transistor 151 is turned off. When transistor 152 turns on,
Current flows through transistor 169. During playback, a high level is supplied to the terminal 140. As a result, transistor 151 is turned on and transistor 152 is turned off. When transistor 151 is turned on, transistor 16
A current flows through 7.

The base of transistor 1670 is connected to the base of transistor 175 and to the base of transistor 126 in FIG.

The base of transistor 169 is connected to the base of transistor 127 in FIG. During playback, a current flows through the transistor 167, which causes a current to flow through the transistor 126, which is connected to this as a current mirror.
In FIG. 5, a differential circuit consisting of transistors 122 and 123 operates. During recording, a current flows through the transistor 169, which causes a current to flow through the transistor 127 which is connected to the transistor 169 in a current mirror, and the differential circuit consisting of the transistors 124 and 125 in FIG. 5 operates.

The collector of the transistor 175 is connected to the power supply terminal 49 via a resistor 176, and the collector of the transistor 177
connected to the base of The emitter of transistor 175 is connected to ground terminal 50 via resistor 178. A resistor 179 is connected between the collector of transistor 175 and ground terminal 50.

A collector of transistor 177 is connected to power supply terminal 49. The emitter of transistor 177 is transistor 1
Connected to the base of 80,181.182. The collectors of transistors 180 and 181 are commonly connected, and this connection point is connected to power supply terminal 49. The emitters of transistors 180', 181, and 182 are connected in common, and this connection point is connected to the collector of transistor 183 as a current source.

The emitters of transistors 184 and 185 are commonly connected, and this connection point is connected to the collector of transistor 183. The base of the transistor 183 is a DC voltage Vr,
For example, it is connected to a terminal 85 of 0.9V. The emitter of transistor 183 is connected to ground terminal 50 via resistor 187.

The bases of transistors 184 and 185 are common FD'd
and this connection point is connected to the emitter of transistor 188. The collector of transistor 188 is power supply terminal 4
Connected to 9. The base of transistor 188 is terminal 1
39. The emitter of transistor 188 is connected to the collector of transistor 189 as a current source. The emitter of transistor 189 is connected to ground terminal 50 via resistor 190.

The collectors of transistors 184 and 185 are connected to the emitters of transistors 191 and 192, respectively, and the collectors of transistor 184 and transistor 185 are connected to each other.
A 1° resistor 193 is connected between the collector and the collector. The base of the transistor 191 is connected to the power supply terminal 49 and the ground terminal 50.
This connection point is connected to a sharpness control terminal 196. The base of the transistor 192 is
A resistor 1 connected between the power supply terminal 49 and the ground terminal 50
97 and 198 are connected in series.

The collector of transistor 191 is connected to the collector of transistor 199 and to the base of transistor 200. The emitter of transistor 199 is connected to power supply terminal 49 via resistor 201. The base of transistor 199 is the same as transistor 61 in FIG.
and 63, and is connected to the base of transistor 2
Connected to the emitter of 00. The emitter of transistor 200 is connected to power supply terminal 49 via resistor 202. A collector of transistor 200 is connected to ground terminal 50.

During recording, a low level is supplied to the terminal 140, so as mentioned above, the transistor 152 is turned on and the l.
Transistor 151 is turned off. When transistor 151 is turned off, transistor 175 is turned off. For this reason,
Resistors 176 and 17 are connected to the base of transistor 177.
A high level is supplied from connection point 9.

When a high level is supplied to the base of transistor 177, the emitter potential of transistor 177 becomes higher than the emitter potential of transistor 188, transistors 180, 181, and 182 are turned on, and transistor 184 is turned on.
, 185 are turned off.

Therefore, R'IA I flowing through the transistor 199
.

is passed through transistor 182. Therefore, the current flowing through the transistor 199 is ■. is a fixed current.

During reproduction, a high level is supplied to the terminal 140, so as described above, the transistor 151 is turned on and the transistor 152 is turned off. When transistor 151 is turned on, current flows through transistor 167 and transistor 175 is turned on.

Therefore, a low level is supplied to the base of the transistor 177.

When a low level is supplied to the base of the transistor 177, the potential of the emitter of the transistor 177 becomes lower than the potential of the emitter of the transistor 188, turning off the transistors 180, 181, and 182, and turning off the transistor 184.
, 185 are turned on.

When the transistors 184 and 185 are turned on, a current ■ flows through the I transistor 199. flows through the transistor 184 and also flows through the resistor 193. Therefore, current I0 is equal to current 1.0 through transistor 184. and the current 12 flowing through the resistor 193. The current 12 flowing through the resistor 193 changes based on the potential difference between the emitter potential of the transistor 191 and the emitter potential of the transistor 192. therefore,
When the voltage applied to the sharpness control terminal 196 derived from the base of the transistor 191 is changed, the resistance 1
The current 12 flowing through 93 changes, and the current flowing through transistor 199 ■. is made variable.

In this way, the current I0 flowing through transistor 199 is
It is fixed during recording, and variable during playback based on the voltage applied to the sharpness control terminal 196.

The base of transistor 199 is commonly connected to the bases of transistors 61 and 63 in FIG. 5, forming a current mirror circuit. Therefore, transistor 1
Based on the current flowing through transistors 61 and 6
Current flows through 3.

Current flowing through transistor 199 ■. Since transistors 61 . are fixed during recording, transistors 61 .
A fixed current is passed through 63 and transistors 58 and 59,
It is assumed that the mutual conductance gm of the amplifier 51 is constant.

At this time, the gain characteristics are flat and constant. During playback, the current I0 flowing through the transistor 199 is varied based on the voltage applied to the sharpness control terminal 196, so that the current I0 flowing through the transistor 199 is varied based on the voltage applied to the sharpness control terminal 196.
and the current flowing through the transistors 58 and 59 is varied,
The mutual conductance gm of the amplifier 51 is varied.

Therefore, the gain characteristics are varied. Even when the gain characteristics are varied in this manner, the delay characteristics and phase characteristics remain approximately constant.

〔Effect of the invention〕

According to this invention, the frequency characteristic adjustment and phase compensation circuit 2
At step 7, sharpness control is performed, and phase compensation for the delay characteristics of the trap circuit 25 is performed. Since the frequency characteristic adjustment and phase compensation circuit 27 always has a constant delay characteristic even if its frequency characteristic is changed, it is possible to perform sharpness control and phase compensation of the trap circuit 25 in this way. In this way, the frequency characteristic adjustment circuit and phase compensation circuit for sharpness control can be shared, so the circuit scale can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of this invention, FIG. 2 is a block diagram of a frequency characteristic adjustment and phase compensation circuit in an embodiment of this invention, and FIG. 3 is a block diagram of frequency characteristic adjustment in an embodiment of this invention. and an equivalent block diagram of the phase compensation circuit,
4A to 4F are graphs used to explain the frequency characteristic adjustment and phase compensation circuit in one embodiment of the present invention, and FIG. 5 is the connection of the frequency characteristic adjustment and phase compensation circuit in one embodiment of the present invention. 6 shows a switch circuit, a fixed current circuit and a variable current circuit, gm
A connection diagram of the control circuit, Fig. 7 is a block diagram of a conventional VT'R during recording, Fig. 8 is a block diagram of a conventional VTR during playback, and Fig. 9 is a graph used to explain the conventional VTR. . Explanation of main symbols in the drawings 21. 22 = switch circuit, 23. 37. 38: input terminal, 24: <L-type filter, 25 Nidrap circuit, 27: frequency characteristic adjustment and phase compensation circuit,
28; Fixed current circuit; 29: Variable current circuit. Agent Patent Attorney Masato Sugiura Figure 3 Figure 4 A Figure 4 B Figure 4 C Figure 4 E

Claims (1)

[Claims] Supplying the luminance signal to a trap circuit for subcarrier suppression,
A video signal in which the output of the trap circuit is supplied to a frequency characteristic adjustment and phase compensation circuit including a gain control amplifier, and the frequency characteristic adjustment and phase compensation circuit adjusts the frequency characteristic and also performs phase compensation of the trap circuit. processing circuit.