JPS62277727A - Manufacture of wiring pattern - Google Patents
Manufacture of wiring patternInfo
- Publication number
- JPS62277727A JPS62277727A JP61121531A JP12153186A JPS62277727A JP S62277727 A JPS62277727 A JP S62277727A JP 61121531 A JP61121531 A JP 61121531A JP 12153186 A JP12153186 A JP 12153186A JP S62277727 A JPS62277727 A JP S62277727A
- Authority
- JP
- Japan
- Prior art keywords
- glass mask
- substrate
- transparent conductive
- wiring pattern
- conductive film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000011521 glass Substances 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- 239000010410 layer Substances 0.000 abstract description 14
- 239000000428 dust Substances 0.000 abstract description 5
- 230000003749 cleanliness Effects 0.000 abstract description 4
- 230000005611 electricity Effects 0.000 abstract description 4
- 238000000059 patterning Methods 0.000 abstract description 4
- 230000003068 static effect Effects 0.000 abstract description 4
- 238000004544 sputter deposition Methods 0.000 abstract description 3
- 239000004925 Acrylic resin Substances 0.000 abstract description 2
- 229920000178 Acrylic resin Polymers 0.000 abstract description 2
- 239000011241 protective layer Substances 0.000 abstract description 2
- 238000007650 screen-printing Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 239000004071 soot Substances 0.000 abstract 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052593 corundum Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 229910001635 magnesium fluoride Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 229910001845 yogo sapphire Inorganic materials 0.000 abstract 1
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000001179 sorption measurement Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000000839 emulsion Substances 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
Landscapes
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
３、発明の詳細な説明
産業上の利用分野
本発明は、半導体集積回路の製造あるいは液晶ディスプ
レイ装置の液晶パネルの製造工程等において利用される
微細な配線パターンを、基板上唇形成する配線パターン
の製造法に関するものである。Detailed Description of the Invention 3. Detailed Description of the Invention Industrial Application Field The present invention is directed to the production of fine wiring patterns used in the manufacturing process of semiconductor integrated circuits or the manufacturing process of liquid crystal panels of liquid crystal display devices. The present invention relates to a method of manufacturing a wiring pattern for forming an upper lip.
従来の技術
一般に半導体集積回路の製造やディスプレイ表示装置の
液晶パネル等の製造工程において、基板上に所定の配線
６パターンを形成する方法として、フォｌ−ＩＪソグラ
フ工法が行なわれている。この従来のフォ） ＩＪソグ
ラフ工法は、第２図イに示すように、フォトレジスト層
（紫外線感光樹脂）３を、全面に導電層２が形成された
コピー基板（Ｓｉウェハー、ガラス等）１上に一定厚み
に塗布し、次いで、マスクアナライザー装置を用いて、
ガラスマスク６に形成されている配線パターン５ａを露
光現像し、第２図口に示すように前記配線パターン５ａ
に応じた形状のフォトレジスト層３を形成し、次にハに
示すように導電層２をエツチングした後、二に示すよう
にフォトレジスト層３を除去し、バターニングを完了す
る。この際、＠記ガラスマスク５ば、所定の配線パター
ン６ａ等の写真技術により、ガラス表面にポジ型あるい
は、ネガ型で形成したものであり、ガラスマスク５に形
成されている配線パターン５ａをコピー基板１上に露光
する際、その両者の正確な位置合せが必要であり、マス
クアナライザーと呼ばれる装置を用いて、位置合せ（ア
ライメント）を行なっている。2. Description of the Related Art In general, in the manufacturing process of semiconductor integrated circuits and liquid crystal panels of display devices, the Fol-IJ sographic method is used as a method for forming six predetermined wiring patterns on a substrate. As shown in Fig. 2A, this conventional IJ photolithography method involves depositing a photoresist layer (ultraviolet photosensitive resin) 3 on a copy substrate (Si wafer, glass, etc.) 1 on which a conductive layer 2 is formed on the entire surface. Apply it to a certain thickness, then use a mask analyzer device,
The wiring pattern 5a formed on the glass mask 6 is exposed and developed, and as shown in the opening of FIG.
After forming a photoresist layer 3 having a shape corresponding to the pattern shown in FIG. At this time, the glass mask 5a is a positive or negative type formed on the glass surface by photographic technology such as a predetermined wiring pattern 6a, and the wiring pattern 5a formed on the glass mask 5 is copied. When exposing the substrate 1 to light, it is necessary to accurately align the two, and alignment is performed using a device called a mask analyzer.
発明が解決しようとする問題点
ところが、このアライメントの際、ガラスマスクとコピ
ー基板間に、若干のギャップ（約２０〜５００μｍ）を
あけていないと、ガラスマスクと基板が衝突したり、擦
れたりする為、アライメントができない。又、アライメ
ント装置の多くは、ガラスマスクと基板の平行をとる為
に少なくとも一度基板が、ガラスマスクに押しつけられ
、その後所定のギャップ１０をとる。しかし、この時ガ
ラスマスクのパターン形成面（表面）に、基板が押しつ
けられるわけであるから、ガラスマスク表面に傷がつく
という問題が生じる。又、アライメント終了後、紫外線
露光する場合、光源が平行光発生装置ならば、問題ない
が、発散光を使用して、ギャップを持たせたまま露光す
るプロミシキティー露光またはギャップ露光の場合は、
所定のパターンが、ガラスマスクどおりコピーされず、
またパターンのエッヂ切れも悪くなる。ちなみに平行光
発生装置と発散光発生装置は、４００Φ光源で、金額に
して、約６〜６倍の値段差がある。Problems to be Solved by the Invention However, during this alignment, if a slight gap (approximately 20 to 500 μm) is not left between the glass mask and the copy substrate, the glass mask and the substrate may collide or rub. Therefore, alignment cannot be performed. Furthermore, in most alignment devices, the substrate is pressed against the glass mask at least once to ensure parallelism between the glass mask and the substrate, and then a predetermined gap 10 is created. However, since the substrate is pressed against the pattern-forming surface (front surface) of the glass mask at this time, a problem arises in that the surface of the glass mask is scratched. Also, when exposing to ultraviolet light after alignment, there is no problem if the light source is a parallel light generator, but in the case of promiscuous exposure or gap exposure, which uses diverging light and exposes with a gap,
The specified pattern is not copied as per the glass mask,
In addition, the edges of the pattern will not be sharply cut. By the way, there is a price difference of about 6 to 6 times between a parallel light generator and a diverging light generator for a 400Φ light source.
問題点を解決するための手段
本発明の配線パターンの製造法は、このような従来の問
題点を解消する為にガラスマスクの配線パターン表面（
エマルジョン面）に、３〜５μｍの保護層を形成し、さ
らに静電気によるはい塵の吸着を低減する為に、透明導
電膜層を数十〜数百人形酸し、露光時にこのガラスマス
クを基板表面に当接せしめたものである。Means for Solving the Problems The wiring pattern manufacturing method of the present invention solves the conventional problems as described above.
A protective layer of 3 to 5 μm is formed on the emulsion surface (emulsion surface), and in order to further reduce the adsorption of dust due to static electricity, several tens to hundreds of transparent conductive film layers are acidified, and this glass mask is applied to the substrate surface during exposure. It is brought into contact with the
作 用
これにより、少なくとも、ガラスマスクパターン表面を
傷つけることなく、しかも、露光光源に発散光光源を用
いて密着露光した場合でも、パターン表面に傷が付かず
、また通常のギャップ露光よりも２桁以上の密着度によ
り、正確なバターニングが可能となる。又、透明導電膜
形成により、静電気によるばい塵の吸着が少なくなり、
従来クラス１００以下のクリーンルームでのフォトリソ
グラフ工程は、大幅に緩和され、製造効率が高く、歩留
り、精度の向上ができる優れた配線パターンの製造法を
提供することかで・きる。As a result, at least the surface of the glass mask pattern is not damaged, and even when a diverging light source is used as the exposure light source for close exposure, the pattern surface is not damaged, and the pattern surface is two orders of magnitude better than normal gap exposure. The above degree of adhesion enables accurate patterning. In addition, the formation of a transparent conductive film reduces the adsorption of dust due to static electricity.
The conventional photolithography process in a clean room of class 100 or below can be significantly relaxed, and by providing an excellent wiring pattern manufacturing method that can improve manufacturing efficiency, yield, and precision.
実施例
以下、本発明の一実施例の製造法を図面を参照して説明
する。第１図は、本発明に使用されるガラスマスクの一
実施例を示すもので、所定の配線パターン５ａが形成さ
れたガラス基板５の表面上に、７ り！ｊ ル樹脂、Ａ
ＩＯＭｑＦ２．５ｉ０２ 等２３’
の紫外線透過膜をハードコート層８として、４，６ＩＩ
ｒｎの厚みにスパンタリング、スピナーコート、ディッ
ピング、スクリーン印刷等の工法により形成している。EXAMPLE Hereinafter, a manufacturing method of an example of the present invention will be explained with reference to the drawings. FIG. 1 shows an embodiment of the glass mask used in the present invention, in which a predetermined wiring pattern 5a is formed on the surface of a glass substrate 5. j Le resin, A
IOMqF2.5i02 etc. 23' ultraviolet transmitting film is used as hard coat layer 8, 4,6II
It is formed to a thickness of rn using methods such as sputtering, spinner coating, dipping, and screen printing.
さらにこのハードコート層８の上に透明導電膜９を約２
００人（面積抵抗４００Ω／口、光透過率９０％以上）
スパッタリングにて形成しているうこのガラスマスクを
用で、フォトリソグラフ工法の露光工程において、前記
透明導電膜９をコピー基板に当接せしめた状態での発散
光光源を使用した密着露光を通常のクリーン度（クラス
１００以下）より低下したクリーン度（クラス１ｏ、ｏ
ｏｏ）の場所で行ない、パターニングを行なった結果、
クラス１００のクリーン度で平光光源と、コーティング
なしのガラスマスクを用いてのギャップ露光（ギヤノブ
量３０μｍ）の結果と同等なパターン精度が得られ、さ
らに、通常ガラスマスクの使用限界より数十倍の回数の
露光工程を行なっても、パターン切れ等の不良は起こら
なかった。Further, on this hard coat layer 8, a transparent conductive film 9 is coated for about 20 minutes.
00 people (area resistance 400Ω/mouth, light transmittance 90% or more)
Using a glass mask formed by sputtering, contact exposure using a diverging light source with the transparent conductive film 9 in contact with the copy substrate is carried out in the exposure process of the photolithography method. Cleanliness (class 1o, o) lower than cleanliness (class 100 or lower)
As a result of patterning at location oo),
With class 100 cleanliness, pattern accuracy equivalent to the result of gap exposure (gear knob depth 30 μm) using a flat light source and an uncoated glass mask is obtained, and it is several tens of times higher than the usage limit of a normal glass mask. No defects such as pattern breakage occurred even after multiple exposure steps.
発明の効果
以上のように、本発明の配線パターンの製造法ハ、ガラ
スマスクのパターン表面に、ハードコート層と透明導電
膜層を形成し、その透明導電膜層を基板に当接せしめた
状態で、露光工程を行うものである為、平行光光源を使
用せずとも、発散光光源で露光に行う事が可能となり、
又、ガラスマスクの長寿化がはかれ、さらに静電気によ
るばい塵の吸着がなくなり、通常のフォトリングラフ工
法に必要なりリーン度を確保せずとも、同等なバターニ
ング精度が得られ、作業性向上に太いに効果がある。さ
らに、パターンが各層に保護されているので、溶剤、超
音波洗浄が可能となる副効果も現われ、ガラスマスクの
汚染に対しても、実用上きわめて有利なものである。Effects of the Invention As described above, the method for producing a wiring pattern of the present invention (c) involves forming a hard coat layer and a transparent conductive film layer on the pattern surface of a glass mask, and bringing the transparent conductive film layer into contact with a substrate. Since the exposure process is performed in this way, it is possible to perform exposure with a diverging light source without using a parallel light source.
In addition, the lifespan of the glass mask has been extended, and the adsorption of dust due to static electricity has been eliminated, and the same patterning accuracy can be obtained without having to ensure the lean degree required for the normal photoringraph method, improving work efficiency. It is effective for thickening. Furthermore, since the pattern is protected by each layer, it has the side effect of being able to be cleaned with solvents and ultrasonic waves, which is extremely advantageous in practice in terms of preventing contamination of the glass mask.
第１図は本発明の配線パターンの製造法に使用されるが
ガラスマスクの一実施例の断面図、第２図イ１ロ、ハ、
二は一般的なフォトリングラフ工法の各工程図である。
１・・・・・・コピー基板、２・・・・・・導電層、３
・・・・・・フォトレジスト、５・・・・・・ガラス基
板、６ａ・・・・・配線パターン、８・・・・・ハード
コート層（アクリル樹脂等）、９・・・・・・透明導電
膜（ＩＴＯ膜等）。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名５゛
−−クラス基、ネ〃ミ
Ｓα゛−ｍｊｌ＆八°タ八ツ
ターン１ 図
８・−八’）ｊｖ−Ａ９゛−望Ｅ１月！！
噛と月ｌFIG. 1 is a cross-sectional view of an embodiment of a glass mask used in the wiring pattern manufacturing method of the present invention, and FIG.
2 is a diagram of each process of the general photorin graph construction method. 1... Copy board, 2... Conductive layer, 3
...Photoresist, 5...Glass substrate, 6a...Wiring pattern, 8...Hard coat layer (acrylic resin, etc.), 9... Transparent conductive film (ITO film, etc.). Name of agent: Patent attorney Toshio Nakao and one other person
8.-8') jv-A9゛-desired January! !
bite and moon
Claims (1)
層と透明導電膜層がこの順序で形成されたガラスマスク
を、基板表面に導電層とフォトレジスト層が形成された
コピー基板に、前記透明導電膜とフォトレジスト層が当
接するよう配置した状態で露光することを特徴とする配
線パターンの製造法。A glass mask, in which a predetermined wiring pattern layer, a hard coat layer, and a transparent conductive film layer are formed in this order on a glass substrate, is placed on a copy substrate, in which a conductive layer and a photoresist layer are formed on the surface of the substrate, and the transparent conductive film is placed on the copy substrate. A method for manufacturing a wiring pattern, which comprises exposing a photoresist layer to light while the photoresist layer is in contact with the photoresist layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61121531A JPS62277727A (en) | 1986-05-27 | 1986-05-27 | Manufacture of wiring pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61121531A JPS62277727A (en) | 1986-05-27 | 1986-05-27 | Manufacture of wiring pattern |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62277727A true JPS62277727A (en) | 1987-12-02 |
Family
ID=14813539
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61121531A Pending JPS62277727A (en) | 1986-05-27 | 1986-05-27 | Manufacture of wiring pattern |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62277727A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001053021A (en) * | 1999-08-16 | 2001-02-23 | Nec Corp | Semiconductor thin film manufacturing equipment |
-
1986
- 1986-05-27 JP JP61121531A patent/JPS62277727A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001053021A (en) * | 1999-08-16 | 2001-02-23 | Nec Corp | Semiconductor thin film manufacturing equipment |
| US6680460B1 (en) | 1999-08-16 | 2004-01-20 | Nec Corporation | Apparatus for producing a semiconductor thin film |
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