JPS6227565B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a crystal oscillation circuit comprising a feedback circuit having a crystal oscillator, a complementary field effect transistor (referred to as IGFET), and a resistor.

Conventionally, LSIs (Large Scale Integrated Circuits) for electronic wristwatches made up of complementary IGFETs include a crystal oscillation circuit as shown in FIG. 1 and a crystal oscillation circuit as shown in FIG. In Figures 1 and 2, 1 is an amplifier circuit, 2 is a feedback circuit, and if the amplification factor of the amplifier circuit is α and the attenuation factor of the feedback circuit is β, it is necessary that αβ≧1 for oscillation to be sustained. The phase shift amount of the amplifier circuit is 180 degrees, and the phase shift amount of the feedback circuit is the desired 360 degrees.
It has a phase shift amount of 180 degrees to give a phase shift of 180 degrees. Q ₁ is a P-channel IGFET, and Q ₂ is an N-channel IGFET, and Q ₁ and Q ₂ form an inverter that reverses the phase shift. The resistor connected in series with the transistor is a frequency stabilizing resistor, C _D is a temperature compensation capacitor, C _G is a frequency adjustment capacitor, Q _Z is a crystal oscillator, and the resistor R ₁ , capacitors C _D , C _G and A feedback circuit 2 having a phase shift of 180 degrees is formed by the vibrator _QZ . R _f is a feedback resistor and sets the DC bias level of the inverter so that the input voltage and output voltage are equal. This DC bias level is 1/2 of the supply voltage, ie, V _SS /2, and is located in the high gain region of the inverter characteristics.

In the conventional crystal oscillation circuit shown in Fig. 1, the minimum oscillation start voltage V _ST is approximately P-channel type IGFET.
It is determined by the threshold voltage S _TP of the N-channel IGFET and the threshold voltage V _TN of the N-channel IGFET, and the value is approximately equal to the sum of IV _Tp I and V _TN , and the current consumption of this crystal oscillator circuit is approximately V _SS
-(IV _Tp l + V _TN ). This is P channel IGFET Q ₁ and N channel IGFET
This is because a normal current flows through Q ₁ and Q ₂ when Q ₂ is ON at the same time. Therefore, the current consumption, that is, the power consumption, changes greatly due to variations in the threshold voltage and fluctuations in the power supply voltage. Therefore, the permissible range of threshold voltage variation is determined by the oscillation start voltage at which the upper limit of the sum of lV _Tp l and V _TN is minimum, and the difference between lV _Tp l and V _TN is
The lower limit of the sum is determined by the watch's allowable power consumption. Therefore, the conventional crystal oscillation circuit shown in FIG. 1 has the disadvantage that current consumption increases in proportion to an exponential function of V _SS -(lV _Tp l +V _TN ).

Furthermore, Fig. 2 shows a conventional example of a crystal oscillation circuit that is a low-power version of the crystal oscillation circuit shown in Fig. 1. R ₂ and R ₃ are current limiting resistors, and the oscillation start voltage V _ST is controlled by the influence of the backgate effect. box office. In other words, if ΔV _Tp is the change in threshold voltage V _Tp due to the back bias effect of the P-channel IGFET, and ΔV _TN is the change in threshold voltage V _TN due to the back bias effect of the N-channel IGFET, then immediately before the start of oscillation , Q ₁ and Q ₂ are ON at the same time, and if the flowing current is I, then R ₂
A voltage drop occurs between the source electrode of Q ₁ and the back gate voltage of IR ₂ relative to the substrate potential.
V _Tp increases by ΔV _Tp . Also N channel type
A back gate voltage of IR ₃ is applied to the potential of the P well where the source electrode of IGFET Q ₂ is the substrate, and V _TN
increases by ΔV _TN . Therefore, the oscillation start voltage is |V _Tp |+|ΔV _Tp |+V _TN +ΔV _TN +IR ₂ +
The disadvantage was that the voltage was much higher than the oscillation starting voltage of the crystal oscillator circuit shown in Figure ₁ , and was greatly affected by the backgate effect.

However, since the crystal oscillator circuit shown in Fig. 2 is subject to current limiting action by R ₂ , variations in the threshold voltage |V _Tp |, V _TN and the supply voltage V _SS
This has the advantage that the variation in current consumption is small compared to the current consumption of the crystal oscillation circuit shown in FIG.

As detailed above, the conventional crystal oscillation circuits as shown in FIGS. 1 and 2 have the above-mentioned drawbacks.

The purpose of the present invention is to eliminate the above-mentioned drawbacks, and to achieve low power consumption and small variation in power consumption.
The object of the present invention is to provide a crystal oscillation circuit having a low oscillation starting voltage, which is not adversely affected by the backgate effect or voltage drop caused by a current limiting resistor.

Examples of the present invention will be shown and explained below.

Figure 3 shows an embodiment of the present invention, where Q ₁ and Q ₃ are P-channel IGFETs, Q ₂ and Q ₄ are N-channel IGFETs, Rf is a feedback resistor R ₂ , and R ₃ is a current limiting resistor. , _R1 is a resistor, C _D is a temperature compensation capacitor, C _G is a frequency adjustment capacitor, Q _Z is a crystal oscillator, 3 is an inverter, and A is a control input terminal. The source electrode of P-channel IGFET Q ₁ is connected to the ground potential GND (V _DD ), and the drain electrode of Q ₁ is connected to one end of resistor R ₂ and the P-channel IGFET.
Connect to the source electrode of Q ₃ , and connect the drain electrode of Q ₃ to
The other end of _R2 , one end of the feedback resistor Rf, and the output terminal O
and one end of resistor R ₁ and N-channel IGFET Q ₂
Connect to the drain electrode of Q ₂ source electrode
Connect the substrate electrode of Q ₂ and one end of resistor R ₃ to the drain electrode of N-channel IGFET Q ₄ , connect the source electrode of Q ₄ to the substrate electrode of Q ₂ and the other end of R ₃ , and connect it to the power supply terminal V _SS. Connecting. Connect the other end of _R1 to one end of the temperature compensation capacitor C _D and the crystal oscillator Q _Z
The other end of Q _Z is connected to one end of the frequency adjustment capacitor C _G , the other end of Rf, the gate electrode of Q ₁ and the gate electrode of Q ₂ , and the other end of C _D and the other end of C
The other end of _G is connected to the ground electrode, and the control input terminal A is
The gate electrode of Q ₄ is connected to the input of inverter 3, and the output of 3 is connected to the gate electrode of Q ₃ .

FIG. 4 shows a specific example of connection to the control input terminals in FIG. 3, where I is the input terminal of the frequency dividing circuit, 4 and 5 are inverters, and
2, 13, 14, 15, 16, 17, 18, 1
9 and 20 are binary flip-flops (or trigger flip-flops) in which the output signal Q is inverted when the φ input changes from "1" to "0";
21 and 22 are binary flip-flops with reset input signal terminals, 23 and 24 are NAND gates, _R4 is a resistor, _C1 is a capacitor, and B
is a control signal output terminal connected to A in FIG. The input terminal I of the frequency divider circuit is connected to O in FIG.
The output of is connected to the φ input of 6. Q output of 6 is 7
The output of 6 is connected to the input of 7.
Similarly from 7 to 8, 8 to 9, 9 to 10, 1
0 to 11, 11 to 12, 12 to 13, 13
Connect from 14, 14 to 15, 15 to 16, 16 to 17, 17 to 18, 18 to 19, 19 to 20, 20 to 21, 21 to 22.
Also, one end C terminal of resistor _R4 is the input of NAND gate 24, one end of capacitor _C1 , and the reset input terminal of the binary flip-flop with reset input.
The output terminal of 24 is connected to the B terminal and the input of NAND gate 23, the output of 23 is connected to the input of 24, and the output of 22 is connected to the input of 23.
Control signal output B is connected to terminal A in FIG.

In Figure 3, the level of control input terminal A is
When the GND (V _DD ) level is "1" level, the N-channel IGFET Q ₄ is turned on. Further, the output level of 3 becomes the V _SS level, that is, the "L" level, and the P channel IGFET Q ₃ is turned on. for R ₂
Make Q ₃ 's ON resistance sufficiently small, and set Q ₄ 's resistance to R ₃ .
_Q3 gate width/
By setting the gate length and the gate width/gate length of Q ₄ , the current flowing through Q ₁ and Q ₂ will flow to Q 3 with almost no current flowing to R ₂ , and almost no current will flow to R ₃ and will flow to R _{4 .}
flows to Also, the gate width/gate length of Q ₃ and Q ₄
By setting the voltage to be much larger than that of Q ₁ and Q ₄ , almost no voltage drop occurs between the drain and source of Q ₃ and between the drain and source of Q ₄ .
So Q ₃ bypasses the current to R ₂ and Q ₄ bypasses R ₃
resistors R ₂ and R ₃ to bypass the current for
The existence of can be ignored. Therefore, the output impedance of the amplifier seen from the output terminal O is
The voltage at which oscillation starts is smaller than when Q ₃ and Q ₄ are not present, and the voltage at which oscillation starts is lower than that in the case where there are no bypass IGFETs Q ₃ and Q ₄ , and a resistor is connected in series with the IGFET between the power supply terminals, as shown in Figure 2. The threshold voltage V Tp and N of the P channel IGFET are lower than the oscillation start voltage of a conventional crystal oscillator circuit, and the threshold voltage V _Tp and N of the P channel IGFET are lower by that amount.
Channel IGFET threshold voltage V _T
Since _N can be increased, the maximum allowable value of V _Tp and the maximum value of V _TN will become larger.
The manufacturing variations in V _Tp and V _TN can be increased by that much, yield is improved, and low-cost LSIs can be supplied. Also, if the manufacturing variations are the same as before, V _Tp , V _TN
The center value and minimum value of can be increased. Also, when the control input terminal A is at the GND (V _DD ) level, that is, the “L” level, the N channel
IGFET Q ₄ is CFFed, the output of Q 3 becomes “H” level, and the P channel IGFET is also turned OFF. Further, the voltage difference between the oscillation start voltage V _ST and the oscillation sustaining voltage minimum value V _HOL is 0.15 V, and there is a relationship of V _ST V _HOLD +0.15. After confirming that oscillation has started, by setting the A terminal to "L" level, both Q ₃ and Q ₄ are turned OFF, and both Q ₁ and Q ₂ are turned ON.
Since the current that flows when _the resistors _{R 2} and _{R 3 are} in _the
The variation in the running current is small even with variations in the current, and the variation in the running current is small even with variations in the power supply voltage. Therefore, a crystal oscillation circuit with low power consumption can be provided.

Figure 5 shows the waveforms and power consumption of each part in Figures 3 and 4, where a is the potential of V _SS and b is R ₄
and C ₁ , c is the waveform of the Q output of 21, d is the waveform of the output of 22, e is the waveform of the B terminal, that is, the A terminal, and f is the output terminal O and I of the oscillation circuit. The waveform g is a diagram representing the power consumption in the oscillation circuit.

When the V _SS power is first turned on, the waveform at point C drops to the V _SS level, that is, the "L" level, as shown in Figure 5b, due to the action of the capacitor _C1 , but the charge accumulated at point C through _R4 is discharged
It attempts to reach the GND level, that is, the "H" level, with a time constant of C ₁ R ₄ . When point C is at “L” level
The output B of the NAND 24 goes to the "H" level, and the Q outputs of the flip-flops 21 and 22 with reset inputs are reset when the reset input is at the "L" level, that is, the Q output goes to the "L" level and the output goes to "H". At this time, the Q output of 21 becomes "L" level, the output of 22 becomes "H" level, and the output of NAND 23 becomes "L" level.
The output of the NAND 24 remains at the "H" level even if the point C becomes the "H" level. Therefore, since control input terminal A is connected to B terminal, Q ₄ is ON, 3
The output becomes "L" level and _Q3 turns ON. Therefore, _Q4 serves to bypass resistor _R3 , and _Q3 serves to bypass resistor _R2 , so the oscillation start voltage is lowered, and oscillation occurs at a correspondingly lower power supply voltage. Also, at this time, the current current flows bypassing the current limiting resistors R ₂ and R ₃ , so the power consumption increases as shown in the T _ON period g in FIG. 5. However, once oscillation starts, the oscillation output O is connected to the input terminal I of the frequency divider circuit, and the frequency is divided by the binary flip-flops 6 to 20 and the binary flip-flops 21 and 22 with reset input terminals, and the crystal oscillator is
If you use one with a resonant frequency of 32.768KHz, there are 16 stages of binary flip-flops from 6 to 21〓〓〓〓
Therefore, the Q output of 21 has a frequency of 32768 x 2 ^-16 = 1/2Hz. Also, the output of 22 has a frequency of 1/4Hz.
Therefore, 2 seconds after oscillation starts, the output of 22 changes from "H" level to "L" level.
The output of NAND23 becomes "H" level, and at this time, the potential at point C is already at "H" level.
By setting the time constant of C ₁ R ₄ , NAND
The output B terminal of 24 becomes "L" level, that is, the A terminal also becomes "L" level, and the N channel
IGFET Q ₄ turns OFF, and the output of inverter 3 becomes “H” level, and P channel IGFET Q ₃ also turns OFF.
Since it is turned OFF, the normal current flowing in the current amplifier circuit becomes a small current limited by current limiting resistors R ₂ and R ₃ , and flows from Q ₁ to R ₂ , from R ₂ to Q ₂ , and from Q ₂ to R ₃ . . As a result, the power consumption in the oscillator circuit becomes considerably smaller due to the constant current, so the power consumption becomes smaller as shown in the T _OFF period of g in FIG. 5, and the oscillation continues as it is. Oscillation sustaining voltage V _HO at this time
Since _{the LD} has a lower oscillation start voltage when the current limiting resistor is bypassed, oscillation is sustained.

As described above, by using the crystal oscillation circuit of the present invention, it is possible to lower the oscillation start voltage and to manufacture an LSI for a wristwatch with low power consumption. Furthermore, for LSIs that require long-time retention characteristics such as IGFET clocks that use a clock gate, it is better to make V _T as high as possible to avoid the tailing region of the IGFET.

In the conventional crystal oscillator circuit as shown in Fig. 2, the oscillation start voltage increases due to the backgate effect caused by the current limiting resistor, and the oscillation starting voltage increases because the current limiting resistor is not bypassed at the start of oscillation. This does not happen with the present invention.
Therefore, |V _Tp | and V in the conventional crystal oscillator circuit
|V _Tp | and V of the crystal oscillator circuit of the present invention from the sum of _TN
Since the sum of _TN can be increased, the upper limit of |V _Tp | and V _TN can be raised, and it has a clock gate logic circuit that operates dynamically, making it extremely suitable for LSIs that have strict retention requirements and require a retention time. It is effective for

In addition, the current limiting resistor R ₂ of the conventional example shown in Fig. 3
Even if a P-channel type IGFETQ ₃ for bypass is connected in parallel to the current limiting resistor R ₃ , and an N-channel IGFETQ ₄ for bypass is connected in parallel to the current limiting resistor R 3, the same operation as in the embodiment shown in Fig. 3 will occur. can be made to In addition, for the control circuit shown in Fig. 4, a wristwatch switch is connected to the A terminal shown in Fig. 3, a resistive element is connected between the A terminal and the V _SS power supply, and when the switch is turned on, the GND (V _DD ) so that the switch is normally in the OFF state, and when it is OFF, the potential is V _SS , so when the oscillation starts, the switch is connected to
By turning on the switch, oscillating, and turning off the switch when the display shows a predetermined display, it is possible to provide an LSI for wristwatches with a low oscillation start voltage and low power consumption. Furthermore, since the threshold voltage can be increased and the upper limit of the threshold voltage of the manufacturing process can be increased, LSIs with high yield can be manufactured.

[Brief explanation of the drawing]

Figure 1 is a diagram showing an example of a conventional crystal oscillation circuit.
2 is a diagram showing an example of another conventional crystal oscillation circuit, FIG. 3 is a diagram showing an embodiment of the present invention, FIG. 4 is a diagram showing a specific example of the control circuit used in FIG. FIG. 5 is a diagram showing waveforms and power consumption of each part in FIGS. 3 and 4. In the figure, Q ₁ and Q ₃ are P channel IGFETs,
Q ₂ and Q ₄ are N-channel IGFETs, R ₁ to R ₃ and Rf are resistors, Q _Z is a crystal resonator, and C _D and _CG are capacitors. 〓〓〓〓

Claims (1)

[Claims] 1. In a crystal oscillator circuit including an amplifier circuit composed of complementary transistors and a feedback circuit connected to the output terminal of the amplifier circuit, a first
One end of a first transistor of one conductivity type is connected through a resistor, the other end of the first transistor is connected to an output end, and a second transistor of an opposite conductivity type is connected to the output end through a second resistor. one end of the second transistor is connected, the other end of the second transistor is connected to the other end of the power supply, a third transistor of one conductivity type is connected in parallel with the first resistor, and the second transistor A fourth transistor of a reverse conductivity type is connected in parallel with the resistor, and the third transistor is connected in parallel with the resistor.
A crystal oscillation circuit characterized in that the fourth transistor and the fourth transistor are turned on at the same time by controlling each with a true complement signal at the time of starting oscillation.