JPS62275374A - Memory cartridge - Google Patents

Abstract

PURPOSE:To prevent destruction of the contents of a volatile memory in spite of the loading/unloading action of a memory cartridge, by permitting a memory access action within the memory cartridge only when the memory access enable/ unable signals received via plural connection terminals satisfy simultaneously the access enable levels. CONSTITUTION:When a RAM cartridge 11 is loaded or unloaded, the rubbing noises are produced at the contact of a connector 10. In this case, a CPU 1 is set under a halt state with the transistors 86 all turned off and the 3 inputs of a NOR gate 115 pulled up by a resistance 114 respectively in terms of the contact state of the connector 10. However it is usually impossible that a RAM chip 111 is set active for a period during which the chip 111 can receive satisfactorily an access. Thus the logical product of those 3 inputs is secured to the rubbing noises. As a result, the contents of the chip 111 are never destroyed by the rubbing noises of the connector content when the cartridge 11 is loaded to and unloaded from the connector 10.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a storage cartridge that is configured to be detachably attached to an electronic device, and particularly relates to a storage cartridge that uses volatile memory. The present invention relates to a storage cartridge that significantly reduces the possibility that the contents of the memory will be damaged during activation or deactivation.

[Prior Art] In recent years, there has been an increase in the number of devices in which volatile semiconductor memories are configured in the form of cartridges that are removable from the main bodies of devices, and the cartridges can be removed and stored when not in use. However, since conventional electronic devices of this type use a mechanical contact system for the attachment/detachment mechanism, the peripheral driver circuit of the volatile memory becomes unstable due to the contact sliding noise generated when the cartridge is attached or removed. This often resulted in the destruction of the memory contents of the storage cartridge.

[Problems to be Solved by the Invention] The present invention has been made in view of the above-mentioned drawbacks, and its purpose is to provide a simple structure and a volatile solution, regardless of the operation of attaching and detaching the storage cartridge. An object of the present invention is to provide a storage cartridge that can prevent the contents of the memory from being destroyed.

[Means for Solving the Problems] In order to solve the above-mentioned problems, the storage cartridge of the present invention includes a connection means for removably connecting a signal line between an electronic device and the storage cartridge, and a connection means for connecting the signal line between the electronic device and the storage cartridge; Memory access in the storage cartridge is enabled only when a plurality of connection terminals that receive memory access permission/denial signals from slave devices and memory access permission/denial signals received via the plurality of connection terminals simultaneously satisfy a permission level. You can rent control means to do so.

[Function] In this configuration, the connecting means detachably connects the signal line between the electronic device and the storage cartridge 1, and at least two or more connection terminals of the connecting means receive a memory access permission signal from the electronic device. receive. The control means enables memory access in the storage cartridge only when the memory access enable/disable signals received via the plurality of connection terminals simultaneously satisfy the enable level.

In this way, stable operation of the memory in the storage cartridge is guaranteed by taking advantage of the fact that sliding noise is rarely generated at a plurality of connection terminals at the same time even when the storage cartridge is attached to and removed from an electronic device.

[Examples] Examples of the present invention will be described in detail below with reference to the accompanying drawings. Figure 1 shows an electronic typewriter (hereinafter referred to as ETW)
FIG. 2 is a detailed block diagram of the printer section of the ETW. In the figure, 1 is a central processing unit (CPU), which will be described later.
Read program instructions from M2, perform calculations, judgments, etc. necessary for the typewriter function according to them, and display the display 5,
Controls the keyboard 4, printer controller 7, etc. 2 is a read-only memory (ROM), and the CPU
A system program for I to operate, a character code necessary for printing, a dot pattern (character generator CG) corresponding to the character code, a time table necessary for printing and motor operation, etc. are stored. 3 is a RAM, which is a read/write memory in which the CPtJl stores data during command execution, calculation results, character codes input from the keyboard 4, data manually input from the voltage detector 12, etc., which will be described later. . Reference numeral 4 denotes a keyboard, which is an input device for inputting various key data necessary for printing characters and for document i collection. Reference numeral 5 is a display that displays key data entered from the keyboard 4, information that the ETW is in operation, and other information necessary for the operator (
messages, symbols, etc.).

7 is a printer controller, as shown in FIG. 2, it includes a pulse motor output latch 70, a carriage motor driver 71, a paper feed motor driver 72,
Thermal head output latch 73, thermal head heater driver 74, thermal head up/down output latch 75, thermal head up/down DC motor driver 76, left margin limiter detection capo
It consists of a door 7 and the like, and controls the printer 6 in response to control signals from the CPU 1.

6 is a printer, which includes a carriage control motor 60, a paper feed control motor 61, a printing mechanism section 62, a DC motor 63 for thermal head up/down, a thermal head up/down mechanism 64, a thermal head 65, and a carriage left margin position detection sensor 66. Consists of etc.
Printing, thermal head up/down, paper feeding, etc. are performed according to instructions from the printer controller 7.

Reference numeral 8 denotes an external cartridge attachment/detachment controller which sets a control signal indicating whether or not data can be accessed to the RAM cartridge to a negative level prior to attaching or detaching the external RAM cartridge 11 to or from the ETW main body. Reference numeral 91 denotes a door switch, which is in an ON state while the door cover is opened to install or remove the RAM cartridge 11, and is in an OFF state while it is closed. A connector 10 is fixed to the ETW main body, and connects and supports an external RAM cartridge 11 in a detachable manner.

11 is an external RAM cartridge of the embodiment, and RA
Save the input character code etc. in the same way as M3 and use ETW
It can be attached to and detached from the main body freely.

In addition, the RAM backup battery 1 is installed so that the memory contents in the RAM cartridge 11 will not be erased even after the RAM cartridge 11 is removed.
12 are built-in.

Reference numeral 12 denotes a voltage detection circuit, which can detect voltage levels of two systems to be described later. 13 is a power supply circuit, and a battery 1
From the voltage of 6, two systems of constant voltage are generated: the voltage necessary for logic circuits such as CPU, ROM2, RAM3, etc., and the voltage for thermal heating. The voltage for thermal head heating can be changed by the print density setting volume 14, and thereby the print density can be adjusted. The voltage for the various motors is supplied directly from the battery. 15 is a power switch. 16 is a battery, which is an operating energy source for this ETW. A timer counter 17 can be loaded with a predetermined value, and counts up or down at certain fixed time intervals. The CPU 1 reads and writes the contents of the counter 17 as necessary.

Sl is a common bus for CPU 1, and is connected to CPU I and RO.
This is a group of signal lines for transmitting information with M2, RAM 3, printer controller 7, etc. S2 is C
External interrupt signal to PUI, the signal level is 0''
An interrupt is generated to the CPU when the signal changes from (LO level) to 1'' (HI level). S3 is the temporary stop control signal (HALT signal) line for CPU 1, and when this control line is "0" The CPU is operating and stops when it becomes "1".S4 is the 0N10F of the door switch 9.
This is a signal line that notifies the cartridge attachment/detachment controller 8 of the F signal. S5 is the RAM in the RAM cartridge 11 prior to the attachment or removal operation of the RAM cartridge 11.
This is a signal line that controls the M chip enable signal. A plurality of signal lines S5 are provided. Alternatively, the connector may have a plurality of terminals. S6 is a signal line that includes some signals necessary for connecting and operating the RAM cartridge 11 to the main body, among the signal lines of the bus S1. S
7 is a battery voltage line, and S8 is a thermal heating voltage line, and the voltage levels of these voltages are monitored by the voltage detection circuit 12. S9 is a logic power supply voltage line.

FIG. 3 is a detailed circuit diagram showing the inside and peripheral circuits of the CPUI, RAM cartridge attachment/detachment controller 8, and external RAM cartridge 11 shown in FIG. 1. In the figure,
81 is a pull-up resistor that maintains the logic level at HIG when the contact of the door switch 91 is OFF (lid 92 is closed). 82 is a Schmitt circuit for reducing chattering of the door switch 91. be.

Resistor 83 and capacitor 84 together with the manual threshold of NAND gate 85 form a CR circuit for signal delay. 86 indicates I't for the RAM cartridge 11.
This is a drive transistor for the AM chip enable terminal. In this embodiment, a plurality of drive transistors and their output lines are used to ensure reliability of control. 87
is the output port, which under the control of the CPUI is set to O″ and 1″
Outputs the logic level of 88 is an AND gate.

As shown in FIG. 3, the RAM cartridge 11 has a structure in which it cannot be installed or removed without first opening the door cover 92 of the cartridge storage section. The door switch 91 is turned on when the door cover 92 is opened, and turned off when the door cover 92 is closed. Therefore, the level of S4 becomes “O” when opened, and “1” when closed.
"become.

Therefore, when mounting or removing the RAM cartridge 11, S
Level 4 is always “O”.

The RAM cartridge 11 includes a RAM chip 111 and a RAM backup lithium battery 1 for retaining the contents of the RAM chip 111 when the cartridge is removed.
12, a power isolation diode 113 that operates when the cartridge is removed, and a RAM chip enable signal S5 to prevent data from being written to the RAM chip 111 when the cartridge is installed or removed. During this period, the pull-up resistor 114 is kept at '1' and the chip enable terminal CE of the RAM chip 111 is
It consists of a NOR gate 115 that keeps I at a LOW level (inaccessible state). Here, NOR gate 11
5 makes the RAM chip 111 accessible only when all inputs are at LOW level, so the NOR gate 11
5 functions as an AND circuit for noise signals.

Two of the three inputs of the NOR gate 115 are provided directly from the drive transistor 86 via the connector 10, and the remaining one is the chip enable signal 81' that the CPU controls to access the RAM cartridge 11 and the drive transistor. It is given by the AND output with the signal from 86. This control line is used when you do not want to access data even if the RAM cartridge 11 is installed and in normal use.

Now, in the tree ETW, when the power switch 15 is turned on, each fffl voltage of the power lines S7 to S9 rises, and the CPU
1 first performs various initialization processes. In the initialization process, for example, the work area in the RAM 3 is cleared, the initial display is displayed on the display 5, the carriage of the printer 6 is moved to the left margin position, and the thermal head is moved up. When the initialization process is completed, input from the keyboard 4 becomes possible, and the CPU i displays the key data input from this on the display 5, or controls the printer 6 through the printer controller 7, and performs printing operations. I do.

FIG. 4 is a timing chart of the RAM cartridge attachment/detachment operation, and FIG. 5 is a flowchart showing the control for the RAM cartridge attachment/detachment operation and its operation transition. E
Attachment and detachment of the RAM cartridge 11 to and from the TW is started by opening the door cover 92 (step 5too).

When the door cover 92 is opened, the door switch 91 changes to QN, and the level of S4 changes from "1" to "0" (step 5).
tot). Also, this will change the level of 52 from 0" to '
1'' and an interrupt is placed on the CPUI (step 510).
2). Chattering occurs when the door switch 91 is turned on, but it is eliminated by the Schmitt circuit 82. Even if the interrupts are not removed sufficiently, there is no problem because the CPUI performs processing to disable multiple interrupts in the first processing input to the interrupt routine. In this ETW, CPU bus S1 is connector 10
Since it is directly connected to the bus of the RAM chip 111 through the
Even if the M chip 111 is not being accessed, there is a possibility that the CPU will run out of control due to sliding noise of the connector terminal due to, for example, an attachment or detachment operation. For this reason, it is necessary to halt (temporarily stop) the CPUI during the attachment or detachment operation. In the interrupt routine, the CPU 1 first performs processing for this purpose (halt preprocessing). For example, if the printer is in operation, will it be stopped? If the RAM chip 111 is being accessed, will it be stopped? , (step 5103).Next, the output of the output port 87 is changed from "0" to "
1". Then, the AND circuit 88 changes the level of S3 from o7 to "1", and the CPU 1 enters the halt mode (step 5104). In the halt mode, the bus s
1 is in a high impedance state. door switch 91
The series of interrupt routine processing time to from when the CPU 1 is turned on until the CPU 1 enters the halt mode is on the order of several ms, which is a time that can be ignored compared to human sensations and operations.

On the other hand, the level of S5 is determined by the action of the CR delay circuits 83 to 85, as shown in FIG.
After reaching N, it changes from "0" to "1" with a delay of tx (this time is also negligible compared to human sensory movements), and the CEI input of the RAM chip 111 becomes inactive (LO level). be done. That is, RAM chip 1
11 is blocked (step 5105). In this case, since it is set so that tx>to, access to the RAM chip 111 is not prohibited before the CFIUI enters the halt mode. Next, the RAM cartridge 11 is manually attached or detached (step 5IO6).

At this time, sliding noise is generated at the contacts of the connector 10. Looking at the contact status of connector 1o at this point, the CPU
I is in a true state, all transistors 86 are turned off, and the three voltages of the NOR gate 115 are pulled up by the resistor 114. Therefore, the logic level of inputs other than these three manual inputs becomes unstable due to the sliding noise of the connector contacts. Furthermore, even when the NOR gate 115 is operated by three people, if the sliding noise is large, its output may become active. However, no matter how irregular the characteristics of this sliding noise may be, it is usually impossible for three people to be active at the same time and for a sufficient period of time for the RAM chip 111 to be accessed. Therefore, by taking the logical product of the three human forces against the sliding noise, it is possible to determine that the sliding noise of the connector contacts causes the RAM chip 111 to
The contents of the file will not be destroyed.

Now, when this attaching or detaching operation is completed and the door cover 92 of the cartridge storage section is closed (step 5107),
The door switch 91 is turned OFF and the level of S4 is “
0” to “1”. Also, due to this, 32.S3.
The level of S5 changes from "1" to 0, and at the same time the CPUI's halt mode is released, access to the RAM chip 111 becomes possible.The CPU then changes the output of the output port 87 from "1" to "0". o'' and terminates the interrupt routine (step 5108).

[Effects of the Invention] As described above, according to the present invention, memory access in the storage cartridge is enabled only when the memory access enable/disable signals received through a plurality of connection terminals simultaneously satisfy the enable level. , even if the RAM cartridge is roughly installed and removed, the contents of the RAM in the cartridge will not be destroyed.

[Brief explanation of drawings]

Figure 1 is a block diagram of an electronic typewriter to which the RAM cartridge of the embodiment is applied. Figure 2 is a detailed block diagram of the ETW printer section. Figure 3 shows the CPU and RAM cartridge of Figure 1. A detailed circuit diagram showing the internal and peripheral circuits of the attachment/detachment controller 8 and the external RAM cartridge 11, FIG. 4 is a timing chart of the RAM cartridge attachment/detachment operation, and FIG. 5 is a control for the RAM cartridge attachment/detachment operation and its operation transition. In the diagram, 1...CPU, 2...ROM, 3...RA
M. 4... Keyboard, 5... Display, 6... Printer, 7... Printer controller, 8... Detachable controller, 91... Door switch, 10... Connector, 11... RAM cartridge, 12... voltage detection circuit, 13... power supply circuit, 15... power switch, 16... battery.

Claims (1)

[Claims] A storage cartridge configured to be detachably attached to an electronic device includes a connection means for detachably connecting a signal line between the electronic device and the storage cartridge, and a connection means for receiving a memory access permission signal from the electronic device. It is characterized by comprising a control means that enables memory access in the storage cartridge only when a plurality of connection terminals to receive and a memory access permission/denial signal received via the plurality of connection terminals simultaneously satisfy a permission level. memory cartridge.