JPS62275359A - Detecting system for frame synchronization - Google Patents

Abstract

PURPOSE:To increase the width of a detecting window for synchronizing signals by producing the estimated functions in response to a synchronizing signal pattern at an estimated detecting time of the frame synchronizing signal and at the time points before and after said estimated time point and performing detection of the frame synchronization. CONSTITUTION:If a frame synchronizing signal S2 is detected out of data at a time point t2, it is detected from an estimated function P2 that the frame synchronizing time point is equal to t2. Therefore the frame synchronizing signal is detected by one of those estimated functions P2, P1 and P3. Thus the width of a detecting window for synchronizing signals is increased several times as much as the conventional estimated function. However a pattern coincident with a synchronizing pattern may possibly included also in data. Thus it is desirable to decide that the frame synchronization is detected when said synchronization is detected in a fixed frequency by the functions P2 and P3 set before and after the original estimated position.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Summary] The present invention generates a prediction function according to the synchronization signal pattern for data consisting of a plurality of data frames having a frame synchronization signal. Regarding the frame synchronization detection method, the detection window width of the synchronization signal is expanded by performing synchronization detection by generating a prediction function according to the synchronization signal pattern at and around the predicted detection time of the frame synchronization signal. be.

[Industrial application field]

The present invention relates to a frame synchronization detection method when reading data consisting of a plurality of data frames having a frame synchronization signal in a high-density recording device such as an optical disk memory or a magneto-optical memory.

[Conventional technology]

To detect the frame synchronization signal, use a prediction function according to the pattern of the frame synchronization signal to be used, such as "001100111100", which satisfies the rules of the old LLER modulation used in the data part and has a sharp autocorrelation pattern. When used as a synchronization signal pattern in data, Qt (τ) = (112232211)Q2
(τ) = (11111111111111111)
is used as a prediction function.

In a frame synchronization detection method that uses such a prediction function, the read data string is sequentially sent to a matched filter, and this matched filter performs bit shifting in synchronization with the clock and performs synchronization from the input data string. The sum of the value obtained by cutting out data with the same number of bits as the pattern and counting the number of matching bits between the cut out data and the synchronization signal pattern and the value of each digit of the above prediction function that is generated sequentially for each clock is specified. Frame synchronization is achieved by setting the time point when the value exceeds the value as the frame synchronization time.

Note that the prediction function is determined by the time width (
The larger the detection window width (hereinafter referred to as the detection window width), the larger the allowable range of the deviation between the synchronization time and the predicted time, and the detection ability for bit errors in the synchronization signal also differs depending on the pattern of the prediction function.

Therefore, the prediction function Q2(τ) has a relatively wide detection window width of ±8 bits, and Ql(τ) has a maximum of 2
Since it is resistant to bit errors up to bits, the flame prediction function Q2
Detection is performed using (τ), and if detection is possible using Q2(τ), then detection is performed using Q+(τ).

If all the digits of the prediction function have been generated before the sum of the number of matching binods and the prediction function reaches the specified value, in other words, if synchronization cannot be achieved, the frame synchronization of the read signal is within the detection window. This is a case where it deviates from the width.

[Problem that the invention seeks to solve]

The timing at which the prediction function is generated is determined by predicting the position of the first frame synchronization signal by counting clock signals from sector address detection in the preformat section.

However, the preformat part and the preamble containing the frame synchronization signal of the data part are separated by a gap, and due to rotational fluctuations that occur because the disk rotates asynchronously with the signal in this gap part, the predicted The timing may deviate from the position of the actual frame synchronization signal, causing the frame synchronization signal to deviate from the detection window width of the prediction function as described above, and frame synchronization may not be achieved.

In addition, the prediction function is determined by the synchronization signal pattern, and if it is extended independently of the synchronization signal pattern, multiple synchronization positions will be randomly detected within one detection window width, resulting in erroneous synchronization. It cannot be expanded freely because there is a possibility that the

An object of the present invention is to reliably detect frame synchronization by widening the detection window width while using a prediction function according to a synchronization signal pattern.

[Means for solving problems]

The present invention generates a prediction function according to a synchronization signal pattern at a predicted detection position of a frame synchronization signal, that is, a position predicted based on the detection of the sector address, and before and after the position, and uses each prediction function to Detect frame synchronization like .

Regarding the frame synchronization detected by the prediction functions generated before and after the detection predicted time, when this synchronization is detected a plurality of times, this synchronization is determined to be a correct frame synchronization.

[For production]

FIG. 1 is a diagram explaining the operation of the present invention in principle.

S indicates the frame synchronization signal in the data, Sl indicates the case where the frame synchronization signal exists at the predicted detected position, S2 indicates the case where the frame synchronization signal is deviated from the predicted detected position, and P+=P3 indicates the predicted position. is a prediction function generated based on .

Pl is a prediction function generated based on the detected predicted position, P2 and P3 are prediction functions generated before and after the prediction function P1, and P2 − P+
, P3, and a frame synchronization signal is detected.

For example, if the time when the frame synchronization signal S2 is detected from the data is t2, the prediction function P2 detects that the frame synchronization time is t2.

Therefore, multiple prediction functions P2, PI, P3
Since the frame synchronization signal is detected by one of the following, the detection window width is several times that of the conventionally used prediction function.

However, since there is a possibility that there are patterns in the data that coincidentally match the synchronization pattern, the detection using prediction functions P2 and P3 that occur before and after the original predicted position will detect synchronization only after a certain number of detections. It is preferable that the

〔Example〕

In FIG. 2 showing the first embodiment, a prediction function generator 11 sequentially outputs the prediction functions P2 and P+tP3 to the addition/comparison circuit 13 at the prediction time and before and after the prediction time based on the sector address detection signal and the clock. The circuit 12 is a matched filter that counts the number of matching bits between the input data string and the synchronization signal pattern and outputs it to the addition and comparison circuit 13. 11 output prediction function value P2 +
P+, +P3 and the number of matching bits output by the matched filter are sequentially added, compared with a certain reference value, and when this reference value is exceeded, synchronization is detected and the optimal prediction function PI- 15 is an interpolation flag selector which sends an interpolation flag to the OR circuit 140 when the prediction function P1 generated at the detected predicted position fails to detect it.

If the synchronization signal can be detected with the prediction function P+, the prediction function P
Subsequent detection is performed by changing the pattern of l from the above-mentioned Q2(τ) to Ql(τ), which is resistant to bit errors.

That is, in the above case, the addition/comparison circuit 13 sends out the detection signal DI indicating that synchronization has been detected by Pl, and O
While it is output as a frame pulse from the R circuit 140, the flip-flop 101 is set to make its output “H”.
” level, and this “H” level output is output from the OR circuit 160.
The prediction function pattern Q2 (τ) generated by the prediction function generation circuit 11 is switched to Q+ (τ) via the output of the flip-flop 101, and the interpolation flag selector 15 performs synchronization detection using Pl. Controls interpolation so that there are no rows until no more rows are left.

As shown in FIG. 3, if the frame synchronization signal S lags behind the predicted detection position and deviates toward P3, then P2. P
The frame synchronization signal S is not detected depending on l, and the synchronization signal is detected depending on P3.

The counters 120 and 130 are reset at the time of this detection, and the count value of the counter 130 is incremented by 1 in response to the detection signal D3 indicating that synchronization has been detected by P3 from the addition/comparison circuit 13, and the Pl generated at the predicted detection position is Interpolation flag selector 15
An interpolation flag Y1 is generated at the detected predicted position, and this interpolation flag Y1 is sent out from the OR circuit 140 as a frame pulse.

Similarly, when the second and third consecutive detections are performed by the second and third consecutive P3s, the counter 13
The count value of 0 becomes 3, overflows, and a set signal of the flip-flop 103 is sent out.

At this time, PI from the prediction function generation circuit 11.

The transmission of P2 may also be stopped.

If detection is not performed continuously due to this P3, the counter 130 is reset by the interpolation flag Y3 generated at that time.

The H” level set output of the flip-flop 103 is
AND circuit 170 is brought into conduction state, OR circuit 190,1
40, the fourth and subsequent detection signals of the detection signal D3 are sent out as frame pulses.

In addition, since the output of the flip-flop 103 becomes "H" level, the Q signal is passed through the OR circuit 160.

, Q2 (τ) to Q+(τ
).

In this state, if frame synchronization is not detected by the prediction function P3 for some reason, the flip-flop 1
03, the interpolation flag Y3 generated at the position P3 from the prediction function generation circuit 11 is sent out as a frame pulse via the interpolation flag selector 15 and the OR circuit 140.

Note that it is clear that the counter 120, flip-flop 102, and AND circuit 180 perform the same operation even when the frame synchronization is shifted toward P2, which is before the detected predicted position.

FIG. 4 shows the configuration of the second embodiment, which includes a prediction function generation circuit 21, a matched filter 22, and an addition/comparison circuit 23.
has the same function as the corresponding component in the first embodiment shown in FIG. 2, but is shown without switching the prediction function in the prediction function generation circuit 21. The function generation circuit 21 sends interpolation flags Y+-Yt to the positions of the prediction functions P1 to P3, respectively.
At the same time, the addition and comparison circuit 23 sends out the prediction function P+=
Similar to the first embodiment, when synchronization is detected by any one of Pt, detection signals D1 to D3 are generated at the synchronization position.

The preamble display circuit 24 outputs an output indicating the distinction between the preamble part and the data part of the data to be read, and outputs a signal of "L" level for the preamble part and "I(" level) for the data part to the detection signal selector 26.

The detection signal selector 26 selects the addition/comparison circuit 23 based on the set outputs of the flip-flops 201 to 203 and the output signal of the preamble display circuit 24, as will be described later.
The interpolation flag selector 25 selects and outputs the detection signals D+ to D3 outputted by the prediction function generation circuit 21, and the interpolation flag selector 25 selects the interpolation flag outputted by the prediction function generation circuit 21 according to the state of the detection signal selector, as described later. and output it.

As shown in the operation explanatory diagram of FIG. 5, the "L" level output indicating the preamble portion of the preamble display circuit 24 is supplied to the detection signal selector 26, so that the detection signal selector 26 selects the flip-flop 202. Alternatively, even if the flip-flop 203 indicates a cent output, the addition/comparison circuit 23 is controlled not to output the detection signal D2 or D3 during this preamble period, and the interpolation flag selector is sent via the detection signal selector 26. 25 controls to output only the interpolation flag Y1 generated at the predicted detection prediction position during the preamble period.

Further, “H” indicating the data portion of the preamble display circuit 24
"The level output is the output of this preamble display circuit."
When the level changes from "L" level to "H" level, that is, when the preamble section changes to the data section, the detection signal (D+ to
one of D3) is controlled to be output during the subsequent data period, and the interpolation flag selector 25 is set to correspond to the detection signal D+, D2, or D3 when the detection signal D+, D2, or D3 is not generated. Interpolation flag Y1 or Y
2 or Y3 is controlled to be output during this data period.

That is, when the synchronization of the read data is detected by the prediction function P1 generated at the normal detection predicted position predicted based on the selector address read from the preformat section, the addition/comparison circuit 23 detects The flip-flop 201 is set by the signal D1, and the detection signal D1 is outputted as a frame pulse via the detection signal selector 26 and the OR circuit 27, but the flip-flop 201 is not set during the first synchronization detection. Therefore, the interpolation flag YI generated at the normal detected predicted position is sent out as a frame pulse via the interpolation flag selector 25.

If, as shown in FIG. 5, frame synchronization is detected by the prediction function P2 that occurs before the prediction function P+ that occurs at the predicted normal detection prediction position, The detection signal D2 generated at the position is supplied to the detection signal selector 26, but since the flip 202 is not set or the output of the preamble display circuit 24 is an "L" level output, the detection signal selector 26 Instead of outputting the detection signal D2, the interpolation flag Y1 is output as a frame pulse via the interpolation flag selector 25 by the "L" level output of the preamble display circuit 24 as described above.

This flip-flop 202 is set by an overflow that occurs when the counter 220 counts a predetermined number of the detection signals D2 during the preamble period (corresponding to the first embodiment, it counts 3), When the preamble section changes to the data section, the cent output of this flip-flop 202 is sent to the detection signal selector 26.
During the subsequent data period, the detection signal selector 26 outputs the detection signal D2 output from the addition/comparison circuit 23 as a frame pulse via the OR circuit 27. If synchronization cannot be achieved by the prediction function P2 for some reason and this detection signal D2 is no longer generated, the interpolation flag Y2 is sent out as a frame pulse from the interpolation flag selector 25 via the OR circuit 27 as described above.

At this time, the transmission of PI and P3 from the prediction function generation circuit 21 may be stopped during the data portion period.

〔effect〕

According to the present invention, frame synchronization detection using a prediction function passed through a frame synchronization pattern can be performed with a wider detection window width corresponding to the number of prediction functions used than in the past.

In particular, as is clear from the first embodiment, the permissible rotation variation amount for disc frame synchronization detection is three times that of the conventional one, and as is clear from the second embodiment, the detection window width is wide ( As a result, frame synchronization can be detected from the beginning even if a prediction function with a narrow detection range and resistant to bit errors is used.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the present invention in detail, FIG. 2 is a block diagram of the first embodiment, FIG. 3 is a diagram explaining the operation of the first embodiment, and FIG. 4 is a diagram showing the second embodiment. An example block diagram, FIG. 5, is a diagram explaining the operation of the second embodiment.

Claims (4)

[Claims] (1) In a frame synchronization detection method that generates a prediction function according to the frame synchronization signal when reading data consisting of a preamble having a plurality of frame synchronization signals and a plurality of data frames having the frame synchronization signals, A prediction function according to the synchronization signal is generated before the frame synchronization prediction time, next, the prediction function is generated at the frame synchronization prediction time, and next, the prediction function is generated after the frame synchronization prediction time. A frame synchronization detection method characterized by detecting frame synchronization. (2) As the prediction function, a first prediction function that has a wide detection range for the deviation between the frame synchronization time and the frame synchronization predicted time, and a second prediction function that has a high detection ability for bit errors, and Frame synchronization is detected by generating a frame synchronization prediction time and the first prediction function before and after the frame synchronization prediction time, and after frame synchronization is pulled in by the first prediction function, prediction is performed based on the frame synchronization. 2. The frame synchronization detection method according to claim 1, wherein frame synchronization is detected by generating said second prediction function at a frame synchronization prediction time. (3) When detecting frame synchronization using the first prediction function, the first frame synchronization detection at the predicted frame synchronization time, or the continuous detection at each time in the case of detection before or after the predicted frame synchronization time. 3. The frame synchronization detection method according to claim 2, wherein frame synchronization is detected by generating the second prediction function by performing the detection a plurality of times. (4) Using the second prediction function, the frame synchronization predicted time predicted based on the frame synchronization detected multiple times during the preamble for a time before or after the frame synchronization predicted time is set to the normal frame synchronization predicted time after the preamble. 2. The frame synchronization detection method according to claim 1, wherein the frame synchronization prediction time is used as the frame synchronization predicted time.