JPS62274895A - Switching circuit for operation of chrominance signal matrix - Google Patents

Abstract

PURPOSE:To eliminate the generation of a noise in a G signal by forcibly holding the present output state of a switching pulse by an output indicating the absence of a chrominance signal. CONSTITUTION:If the level of the chrominance signal is lower than a prescribed level or brought into a black and white broadcasting state, the output of a black and white detection circuit 44 goes to high level and the output of an inverter G16 goes to low level. In such case, the output of a NAND circuit G13 only goes to high level and the output of a NAND circuit G15 is not changed from the high level. Accordingly, in a flip flop circuit operating by the trailing of an input, a change is not produced. Namely, the output (switching pulse) holds an original state. This indicates that the changeover of a switch 16 is not carried out and means that the direct current offset is not produced in the output. Thereby, at the time of deciding the black and white state, the signal synthesis ratio of a matrix circuit is prevented from switching and the generation of the noise is prevented in the G signal.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Object of the Invention] (Field of Industrial Application) This invention is applicable to a video signal processing circuit that can process signals of various color television systems. This invention relates to a color signal matrix operation switching circuit.

(Prior Art) Current color television systems in the world include the NTSC system mainly in the United States and Japan, the SECAM system mainly in France and Eastern European countries, and the PAL system mainly in Western European countries. In the Middle East countries, video tape recorders of various systems are rapidly becoming popular, and with this, multi-system color television receivers are becoming necessary. This television receiver is provided with a demodulation system for demodulating various color signals, and a matrix circuit for obtaining the G signal is also provided within the demodulation system.

In other words, television signals usually use quadrature modulation,
(R, -Y) signal and (B-Y) signal are sent, (G-
Y) A method is adopted in which the signal is extracted from these two signals using a matrix.

FIG. 2 shows the (GY) signal matrix section.

(RY) signal and (B-Y) signal are respectively (R-Y
), (B-Y) are supplied to clamp circuits 11 and 12, and the outputs of each clamp circuit 11 and 12 are gain controlled by color control circuits 13 and 14, respectively. The gain-controlled (R-Y) signal and (B-Y) signal are supplied to the matrix circuit 16. This matrix circuit 16 can obtain a (G-Y) signal by combining input signals. This (G-Y) signal is transmitted to the next stage G component detection circuit 17.
supplied to The G signal (primary color signal) detected here is pedestally clamped by a pedestal clamp circuit 18 and outputted to an output terminal 19 as a final G signal.

By the way, in a multi-system television receiver, a matrix ratio switching signal is supplied to the matrix circuit 16 described in "2". This matrix ratio switching signal is obtained from the matrix switching circuit 20. The matrix ratio is switched between the NTSC signal and
PAL.

This is because the combination ratio of the (G-Y) signal is originally different from that of the SECAM system.

FIG. 3 shows the above-mentioned matrix circuit 16 section in more detail. Transistors Ql, Q2°Q3 and resistors R1, R2, R3 constitute a bias circuit, and the bias is applied to transistors Q5. Q6. Q13. Q14
．． Supplied to the base of Q20. Transistor Q5. Resistor R5 and transistor Q4 are connected in series and act as a current source for a differential circuit made up of transistors Q7 and Q8.

Transistor Q6. Resistor R6 is transistor Q9゜QI
It acts as a current source for a differential circuit consisting of O.

The emitter of transistor Q4 is connected to (R
-Y) signal is supplied. Transistor Q8. The collector of QIO is connected to the power supply, and the collector of transistor Q7. Q
The collector of 9 is connected to the power supply via a resistor R7. and transistor Q7. The collector output of Q9 is derived via the base and emitter of transistor Qll. The collector of the transistor Qll is connected to a power supply, and the emitter is grounded via a constant current source 11. Transistors Q12 to Q19, resistors R8 to R11, constant current source 12
The circuit configured by the above is also similar to the (RY) signal amplification circuit described above, except that it processes the (B-Y) signal.

The emitter outputs of transistors Qll and Q19 are connected to resistor R1.
4, R15, and R16, and a resistance matrix section including resistors R17, R18, and R19. Resistor R16°R19 is transistor Q
21. Q20. A bias circuit consisting of resistors R13 and R12 and a constant current source i3 supplies the bias to the matrix circuit.

The midpoint between resistors R14 and R15 is supplied to one input section a of switch 161, and the midpoint between resistors R17 and RlB is supplied to the other input section a of switch 161. This switch 161 is controlled by a switching pulse, and input part a is selected when processing an NTSC signal, and PAL, SEC
The AM processing method processing power section is selected.

FIG. 4 specifically shows the matrix switching circuit 20 described in "2". The format of the input signal is determined by the format determination circuit. When a PAL format signal is input, there is a high level output from the PAL detection circuit 31, and when a SECAM format signal is input, there is a high level output. is S
There is a high level output from the ECAM detection circuit 32, and N
When a TSC signal is input, there is a high level output from the NTSC detection circuit 33. Now, when there is a high level output from the PAL detection circuit 31, the output of the inverter G1 changes to a low level, the output of the NAND circuit G5 changes to a high level, and the output of the inverter G7 falls from a high level to a low level. As a result, NAND circuit G9. GIO
The flip-flop circuit consisting of is set and its output becomes low level. A similar operation is obtained when only the output of the SECAM detection circuit 32 is at high level and the others are at low level.

Next, when only the output of the NTSC detection circuit 33 is at high level and the others are at low level, a reset pulse is supplied to the flip-flop circuit, and the switching pulse becomes high level. G3゜G4. G8 is an inverter, G6
is a NAND circuit. The output of a black and white detection circuit 34 for detecting black and white signal states is supplied to the input of the inverter G4.

(Problem to be solved by the invention) In the above circuit, especially PAL or SECAM
If the black and white detection circuit 34 malfunctions while receiving or processing a system signal, there is a problem in that a green or purple striped pattern appears on the screen, impairing the image quality. This phenomenon occurs especially when the color signal level is low in weak electric field reception conditions, or when input television signals (such as VTRs)
This occurs when the color signal level is low.

In other words, in the circuit explained in FIG.
Although the voltages at points D and ED are designed to be equal, variations in the values of resistors R7, R1, 1, and R13, R5, R6
, R9, RIO, R12 value variations and transistor Vbe pairability.

The DC voltage varies due to the pair nature of β. Therefore, the C shown in the diagram
The DC voltages at points D and DD are offset. If the output with such an offset is input to the next-stage clamp circuit, a noise component as shown in FIG. 5 will be generated in the G output.

FIG. 5 shows an example of a transition from a PAL or SECAM color reception state to a monochrome determination state, and then to a color reception state. This noise is caused by the operation of the clamp circuit shown in FIG. 6.

That is, it is assumed that a G signal appears at the emitter of transistor Q31. The emitter of the transistor Q31 is grounded via the constant current source 1]1, and the emitter of the transistor Q31
32 base and collector. Transistor Q32. Q33 is a differential amplifier type comparison circuit,
A reference voltage v1 is supplied to the base of the transistor Q33. f12 is a constant current source that is turned on for a predetermined gate (pedestal clamp period). If the potential shown in the figure is higher than the potential of the reference voltage v1, then the transistor Q3
A current flows through the capacitor C1, the charge in the capacitor C1 is discharged, and the potential shown in the figure becomes equal to the reference voltage.

Further, when the potential shown in the diagram (■) is lower than the reference voltage (■1), a charging current flows to the capacitor C1 via the transistor Q34, increasing the potential and operating so that it becomes equal to the reference voltage v1.

Here, when a direct current with an offset is input from the switch 161 as at time t1 in FIG. 5, the potential shown in the figure becomes high and then becomes equal to the reference voltage. In this case, since the discharge current of the capacitor C1 is discharged through the transistor Q32, it takes time until the reference voltage and the potential shown in the figure become equal. The same thing can be said at time t2. In this way, when the matrix circuit is switched between the color state and the monochrome state, there is an offset in the DC level, which causes noise in the G signal.

-9= Therefore, it is an object of the present invention to provide a color signal matrix operation switching circuit that can prevent the signal synthesis ratio of the matrix circuit from switching when determining the black and white state, and can eliminate noise from occurring in the G signal. shall be.

[Structure of the invention] (Means for solving the problem) In this invention, in order to solve the two-legged problem (RY)
Matrix the color signal and ([3-Y) color signal, and (G
-Y) A matrix circuit section for obtaining color signals, and a matrix circuit section (
In a color signal matrix operation switching circuit having means for switching the R-Y) color signal, the (B-Y) color signal, and the combination ratio using a switching pulse, it is determined whether the color signal of the television signal is at a predetermined level. means for forcibly maintaining the current output state of the switching pulse by the output indicating the absence of the color signal when the output of the detection means changes from the output indicating the presence of the color signal to the output indicating the absence of the color signal; It shall be established.

(Function) As described above, the current output state of the switching pulse for switching the combination ratio of the matrix circuit is determined by the output indicating the absence of the color signal from the detection means that determines whether the color signal of the television signal is at a predetermined level. By providing a means for forcibly holding the output, the output with a DC offset from the matrix circuit is not supplied to the clamp circuit.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, in which the television signal system detection means 40 includes a PAL detection circuit 41, a SECAM
Detection circuit 42. It has an NTSC detection circuit 43. Reference numeral 44 denotes a black and white detection circuit which determines whether the color signal level included in the television signal is higher than a predetermined level and outputs a high level if it is lower than the predetermined level. PAL
Detection circuit 41. SECAM detection circuit 42. The NTSC detection circuit 43 obtains a high-level output when detecting a signal of each corresponding system. PAL detection circuit 41.
The outputs of the SECAM detection circuits 42 are each connected to an inverter G.
It is supplied to the NAND circuit G13 via G12.

The output of this NAND circuit G1.3 is further
14. This NAND circuit G14
The output of the black and white detection circuit 44 is input to the other input of the inverter G16. Also, the NTSC detection circuit 4
The output of No. 3 is supplied to one side of the NAND circuit G15. Similarly, the output of the black and white detection circuit 44 is supplied to the other input of this NAND circuit G15 via an inverter G16.

The outputs of NAND circuits G14 and G15 are outputted to NAND circuit G17.
A set of flip-flop circuits consisting of Glg is supplied to the reset input. The output of this flip-flop circuit is input to the control section of the switch 161. This switch 161 is the same as that described in FIG.

The switch 161 selects the (IIY) signal and the (13-Y) signal with different matrix ratios = 1
2 - I can do it. Signal sources 45 and 46 correspond to the color control circuit sections for the (RY) signal and (+13-Y) signal explained in FIG. 3, respectively. The outputs of the signal sources 45 and 46 are combined via resistors R14 and R15, respectively. A bias E is also supplied to this combining section M1 via a resistor R16.

Then, the signal of the combining section M1 is input to the input section a of the switch 161.
supplied to Further, the respective outputs of the signal sources 45 and 46 are combined via resistors R17 and R18, respectively. A bias E is also supplied to this combining section M2 via a resistor R19. The signal from the combining section M2 is then supplied to the input section of the switch 161.

One embodiment of the invention is configured as a biped.

It is assumed that a PAL signal is currently being processed and only the output of the PAL detection circuit 41 is at a high level. At this time, the output of the inverter Gll is at a low level, and the output of the NAND circuit G13 is at a high level. Further, at this time, assuming that the color signal is at a predetermined level or higher, the output of the black and white detection circuit 44 is at a low level, and the output of the inverter 016 is at a high level. Therefore, the output of the NAND circuit G1.4 is at low level, and the output of the flip-flop circuit is at low level. The switch 161 selects the input section when the switching pulse from the flip-flop circuit is at a low level. In addition, the matrix circuit has a combining section M
The second signal is set to be suitable for the PAL system.

When the television signal is of the SECAM format, the signal of the combining section M2 is selected in the same way as above.

Next, if the television signal is in the NTSC format,
Only the output of the SC detection circuit 43 is at high level, and the outputs of the other detection circuits are at low 1 level. At this time, the output of the NAND circuit G15 becomes low level, and the flip-flop circuit is reset. Therefore, the output of the flip-flop circuit is at the NO1 level, and the switch 161 selects the input section a and selects the output of the combining section M1. Synthesis section M1
The signals are set to be suitable for the combining ratio of the NTSC system.

Next, in the PAL or SECAM reception state,
The operation when the color signal drops below a predetermined level will be described. In the PAL or SECAM reception state,
The output of the NAND circuit G13 is at a high level, and the output of the NAND circuit G15 is at a high level. When the color signal is at a sufficient level, the output of the inverter 016 is at a high level, so the output of the NAND circuit G14 is at a low level. In this state, if the level of the color signal falls below a predetermined level or a monochrome broadcasting state occurs, the output of the monochrome detection circuit 44 becomes high level and the output of inverter G16 becomes low level. At this time, the output of the NAND circuit G13 only becomes high level, and the output of the NAND circuit G15 does not change from the high level. Therefore, no change occurs in the flip-flop circuit that operates at the falling edge of the input. That is, its output (switching pulse) remains in its original state. This means that switch 161
This means that no switching occurs, and no DC offset occurs in the output. Furthermore, when the color broadcasting state returns to the above state or the color signal reaches a predetermined level or higher, the output of the inverter 016 becomes high level and the output of the NAND circuit G13 becomes low level, but the flip-flop circuit in this state It has no effect. Similarly, in the NTSC reception state, even if color broadcasting and black and white broadcasting are switched, the output of the front tube flip-flop circuit is not affected.

[Effects of the Invention] As explained below, the present invention prevents the signal synthesis ratio of the matrix circuit from switching when determining the black and white state,
It is possible to provide a color signal matrix operation switching circuit that can eliminate noise from occurring in the G signal.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a configuration diagram of a color signal demodulation circuit, FIG. 3 is a circuit diagram showing a part of FIG. 2 in more detail, and FIG. FIG. 5 is a signal waveform diagram for explaining the operation of the circuit in FIG. 2, and FIG. 6 is a diagram showing the clamp circuit in FIG. 2. 41... PAL detection circuit, 42... SECAM detection circuit, 43... NTSC detection circuit, 44... Black and white detection circuit, Gll, G12. G16...Inverter, G
13. G14. G15G17. G18...NAND circuit, 45.46...Signal source, R14-R19...Resistor, 161...Switch.

Claims (1)

[Claims] A matrix circuit section that matrixes the (RY) color signal and the (B-Y) color signal to obtain the (G-Y) color signal; In the color signal matrix operation switching circuit having means for switching the combination ratio of the -Y) color signal and the (B-Y) color signal, a first
a detection circuit for detecting a second television system;
a detection circuit, a switching pulse output means for obtaining an inverted output and a non-inverted output from the detection outputs of the first and second detection circuits, and inputting the output to a synthesis ratio switching switch of the matrix circuit; a detection means for determining whether or not a color signal of the signal is at a predetermined level; and an output indicating the absence of the color signal when the output of the detection means changes from an output indicating the presence of the color signal to an output indicating the absence of the color signal. and means for forcibly holding the current output state of the switching pulse output means.