JP2919936B2 - Television signal type discrimination circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a television signal for determining whether an incoming color signal in a television receiver is a color signal or a monochrome signal. And a method discrimination circuit.

(Prior Art) There are PAL, SECAM, and NTSC as broadcast systems for color signals, and among them, the PAL and NTSC systems transmit color difference signals by AM modulation. FIG. 6 shows a conventional two-color signal processing unit. Hereinafter, a color signal is assumed to be based on these two methods.

In FIG. 6, the chroma signal separated from the composite video signal is input to the ACC circuit 1, the color difference signal is output to the second chroma amplifier circuit 3, and the burst signal is output to the color synchronous reproduction circuit 2 and the killer detection circuit 5. You. Killer detection circuit 5
Is connected to the level comparing circuit 6 and the level comparing circuit 6
Is output to the second chroma amplifier circuit 3. The output of the color synchronous reproduction circuit 2 is supplied to a killer detection circuit 5 and a color difference demodulation circuit 4. The demodulated output of the color difference demodulation circuit 4 is output as a color difference baseband signal.

Normally, a receiver is provided with an automatic chroma level control (ACC) circuit for stabilizing the level of a received chroma signal, and compensates for loss of color signal amplitude at a tuner or IF. At present, a method of controlling the variable gain amplifier by detecting the level of the burst signal by peak detection and detecting whether the burst signal has reached the reference level is adopted. In order to hold the control information for the burst signal for one horizontal period, And a capacitor C1. Of the chroma signals whose amplitudes have been stabilized by the ACC circuit 1, only the color difference modulation signal or both the burst signal and the color difference modulation signal are input to the second chroma amplification circuit 3. The 2nd chroma amplifier circuit 3 is provided with a chroma level control function by the user so that the television viewer can adjust the coloring (color density) of the video signal as desired.

Further, only the burst signal of the output signal of the ACC circuit 1 is output to the killer detection circuit 5 and the color synchronous reproduction circuit 2. The color synchronous reproduction circuit 2 reproduces a continuous color subcarrier from the received burst signal. Since a high-Q filter is required to reproduce the color subcarrier, VCXO is normally locked to a burst signal using a crystal X'tal to obtain a continuous wave CW. The continuous wave CW is generated by shifting the oscillation signal of the VCXO,
Used for demodulation and killer detection. In the color difference demodulation circuit 4, a continuous wave
The CW and chroma signals are input, and RY, GY, and BY color difference signals are output.

The killer detection circuit 5 receives the burst signal and the continuous wave CW and performs synchronous detection. The synchronously detected output is connected to capacitor C2.
To accumulate. In the case of a color broadcast on which a burst signal depends, the electric charge of the synchronous detection is charged in the capacitor C2, so that the potential of the capacitor C2 rises. Conversely, in the case of monochrome broadcasting, since there is no burst signal, the synchronously detected voltage becomes zero and the potential of the capacitor C2 becomes "L". The state change between “H” and “L” is output to the next-stage level comparison circuit 6. The level comparison circuit 6 has a certain reference voltage source Vref, and determines whether or not the output voltage of the killer detection circuit 5 has exceeded the reference voltage. If the level is lower than the reference level, the signal is a black-and-white broadcast. Therefore, it is necessary to cut off the signal path from the second chroma amplifier circuit 3 to the color difference demodulation circuit 4 to prevent cross color and reduce color noise. Therefore, the level comparison result is 2n
It is output to the d-chroma amplification circuit 3 to cut off the chroma signal.

Thus, the killer detection circuit 5 and the level comparison circuit 6
, Good images can be received at the time of black and white and color broadcast reception.

The above-described discriminating circuit can receive a signal having a good S / N at a place where the electric field strength of the received television signal is strong (close to the broadcasting station), but received when the electric field strength is medium to weak (far from the broadcasting station). There is a problem that the S / N of the television signal is low, noise is mixed, and a malfunction of the killer determination circuit is likely to occur. Since peak detection is performed by the ACC circuit in the above system, if weak electric field noise is mixed in, ACC is applied to the noise peak, and the original burst signal component is equivalently attenuated. Then, since the synchronous detection output voltage in the killer detection circuit also decreases, there is a disadvantage that the color disappears in spite of the color broadcast.

(Problems to be Solved by the Invention) In a conventional television signal type discriminating circuit, not only a malfunction occurs when the electric field intensity is weak, but also a problem that color disappears despite color broadcasting.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a television signal type discriminating circuit in which colors do not easily disappear even when receiving a color television reception signal in a weak electric field.

[Means for Solving the Problems] The present invention provides an ACC circuit for stabilizing the amplitude of a chroma signal of a composite video signal, and first and second SYNC circuits synchronized with a burst signal output of the ACC circuit. A color synchronous reproduction circuit for reproducing a continuous wave; a first output continuous wave of the color synchronous reproduction circuit;
A killer detection circuit that synchronously detects the output burst signal of the circuit; and a level comparison circuit that compares the detection output of the killer detection circuit with a predetermined reference level and detects that the synchronous detection output exceeds the reference level. A color difference demodulation circuit for demodulating an output chroma signal of the ACC circuit by a second output continuous wave of the color synchronous reproduction circuit, and a chroma signal for preventing the demodulated signal from appearing at the output of the demodulation circuit by the output of the level comparison circuit. Means for interrupting the signal path and means for controlling the detection sensitivity of the killer detection circuit or the reference voltage of the level comparison circuit only when the control information of the ACC circuit and the detection output information of the killer detection circuit satisfy predetermined conditions. It is characterized by comprising.

(Operation) The present invention inputs two pieces of information, that is, the control state of the ACC and the output voltage of the killer detection circuit, to the level comparison circuit, controls the reference voltage and the detection sensitivity of the killer detection circuit based on the two pieces of information, and adaptively determines the killer. By changing the sensitivity of the system, the occurrence of color erasure can be prevented even for a color television reception signal in a weak electric field.

(Embodiment) FIG. 1 shows a color signal processing section of a television receiver according to an embodiment of the present invention. The chroma signal separated from the composite video signal is input to the ACC circuit 1, the color difference signal is output to the second chroma amplifier circuit 3, and the burst signal is output to the color synchronous reproduction circuit 2.
And output to the killer detection circuit 5. The output of the killer detection circuit 5 is connected to the level comparison circuit 6, and the comparison result of the level comparison circuit 6 is output to the second chroma amplification circuit 3. The output of the color synchronous reproduction circuit 2 is supplied to a killer detection circuit 5 and a color difference demodulation circuit 4. The demodulated output of the color difference demodulation circuit 4 is output as a color difference based band signal. The control information of the ACC circuit 1 is input to the level comparison circuit, and the second output of the level comparison circuit 6 is input to the killer detection circuit 5. The level comparison circuit 6 has a power supply Vref which can be externally controlled as a comparison reference voltage source.
Is provided.

First, the chroma signal whose amplitude has been stabilized by the ACC circuit 1 is
Input to the chroma amplifier circuit 3. The chroma signal adjusted by the user is output to the color difference demodulation circuit 4. The burst signal output from the ACC circuit 1 is output to the color synchronous reproduction circuit 2
The signal is output to the killer detection circuit 5, and the color synchronous reproduction circuit 2 reproduces a continuous wave CW signal frequency-locked to a burst using the crystal X'tal. The phase of the reproduced CW signal is shifted to the synchronous detection CW of the killer detection circuit 5 and the color difference demodulation circuit 4.
, Respectively. The killer detection circuit 5 performs synchronous detection with the CW signal in phase with the input burst signal, charges the detection output to the integrating capacitor C2, and outputs the detection output voltage to the level comparison circuit 5. In this level comparison circuit 6, ACC control information is input in addition to the killer detection output voltage. This control information is the control voltage amount if the ACC circuit 1 is of the voltage control type. Therefore, the level comparison circuit 6 detects the level of the reference voltage source Vref and the killer detection output voltage, and outputs the comparison result to the second chroma amplification circuit 3.
Here, it is assumed that the killer detection circuit 5 can increase the killer detection sensitivity by an external control signal, and the reference voltage source Vref can also increase or decrease the voltage by the external control signal.

In the level comparison process, the logical product of the control information of the ACC circuit 1 and the killer detection output voltage of the killer detection circuit 5 is obtained, and the detection sensitivity and the reference voltage value of the killer detection circuit 5 are controlled based on the result. Then, for example, when the ACC control voltage is high and the killer detection output voltage is high, the killer detection sensitivity is raised,
Control such as lowering the reference voltage source Vref becomes possible. The above-described method makes the method determination result of the input signal closer to the color mode, and is suitable for receiving a color signal in a weak electric field. By increasing the sensitivity of the killer system only when the logical product satisfies the condition, it is possible to prevent the sensitivity from increasing under other input conditions, and the weak electric field B / W (black /
The malfunction in the white) mode can be prevented.

This will be further described with reference to the reception waveform diagram of FIG. (A) is a chroma input and ACC output signal when a strong electric field and a B / W signal are received. Because of the strong electric field, there is no noise, and the chroma input signal waveform has a cross color component of the luminance signal and a high frequency component of the synchronization signal slightly superimposed. Since the ACC circuit 1 has no signal whose amplitude should be stabilized, the ACC circuit 1 has a maximum sensitivity (gain Max) and a signal whose input is amplified appears at the output. However, the output signal is just noise,
Since there is no component synchronized with the color subcarrier, the output of the killer detection becomes "L". Next, (b) shows a chroma input and an ACC output signal when a strong electric field and a color signal are received. Because of the strong electric field, the chroma signal waveform has no noise. A burst signal level sufficient to close the ACC loop is obtained, and the output signal has a waveform whose burst amplitude has a certain reference value. Since the burst signal is supplied to the killer detection circuit 5 at a sufficient level, the killer detection output becomes “H”.

FIGS. 2 (c) and 2 (d) show the case when the electric field is weak. FIG. 2 (c) shows each signal when a weak electric field and a B / W signal are received. Because of the weak electric field, it becomes a chroma input waveform with pulse noise. Since the ACC circuit 1 has a large noise amplitude, it is applied to the noise. Since peak detection is performed at the timing when the burst should be located, certain noise is regarded as a burst and the noise amplitude is attenuated as shown in the figure. At this time, a considerably large amplitude signal is obtained at the output.
There is no component synchronized with the chrominance subcarrier because of the B / W signal as in the case of. Therefore, the killer detection output becomes “L”. (D) shows each signal when a weak electric field and a color signal are received. As in (c), there is pulse noise on the chroma signal.
C is applied to the level of burst + noise. Therefore, the output signal has a waveform in which the chroma signal is compressed by noise. The state of the killer detection output voltage at this time is unstable. If the noise is large, the chroma signal is correspondingly weakened by being compressed and becomes "L". If the noise is not so large, it approaches "b" and becomes "H". Any value during this period can be taken depending on the amount of noise.

FIG. 3 shows the four reception states and AC of FIGS. 2 (a) to (d).
Indicates the state of C control. When the input level is sufficiently low, there is an operating point near point B, and as the input level gradually increases, the output becomes flat, and the element operates near point A with adult power. When the input is further increased, the ACC is lost and the output increases with the input. The operations A and B and “H” and “L” of the killer detection output represent the four states in FIG. 2 as shown in the table below.

As described above, when the operating point of the ACC is A and the killer detection output is "H", the color mode is indicated by * in the table. At this time, the detection sensitivity of the killer detection circuit 5 is increased,
If the comparison reference voltage Vref is lowered, the mode can be shifted to the color mode. Therefore, the burst input level at which the color disappears can be greatly reduced, and the color can be made less likely to disappear.

FIG. 4 shows a specific circuit example of killer determination. The transistors Q1 to Q13, the resistors R1 to R7 are the killer detection circuit 5, the transistors Q14 to Q26, and the resistors R8 to R15 are the reference voltage Vref generating circuit, the transistors Q27 to Q36, and the resistors R16 to R18.
Is a level comparison circuit 6, transistors Q37 to Q55, and a resistor R19.
R20 is a sensitivity control circuit, B1 and B2 are burst signals from the ACC circuit, CW1 and CW2 are CW signals from the color synchronous reproduction circuit 2, ACC1 and ACC2 are ACC control voltages, and VB1 and
VB3 is a constant voltage source, and VB2 is a gate voltage source.

In the killer detection circuit 5, the transistor Q1 is turned on by the gate voltage source VB2 only during a period in which a burst exists. Then, the synchronous detection circuits of the transistors Q2 to Q13 are turned on, and a detection current is output. In the Vref generation circuit, the transistor Q17 causes a current to flow through the constant voltage source VB3 via the resistor R14 to generate a potential difference, and VB3 + R14 I17 becomes the reference voltage source Vref. Note that R
14 is the resistance value of the resistor R14, and I17 is the collector current of the transistor Q17. Transistors Q20 to Q24 are buffers that add the load resistance R13 of the detection circuit in synchronization with the gate.
Activate 21 ~ Q24. When the gate is turned on, the base of the transistor Q21 lowers the potential of VB3 + VBE26 (the voltage between the base and the emitter of the transistor Q26). When the detection output current is zero, the terminal P to which the capacitor C2 is connected has this potential. The killer detection circuit 5 passes the output current to the resistor R13 and the capacitor C2 during the gate period, and there is no killer output current during periods other than the gate, so that the killer detection circuit 5 is cut off, and the resistor R13 is also open.
The capacitor C2 holds the detection voltage. The level comparison circuit 6 compares the voltage of the capacitor C2 with the voltage obtained by level-shifting the reference voltage source Vref by the buffer of the transistor Q25. If the voltage at the terminal P is high, a current flows through the transistor Q30, and the transistor Q27 is turned on by the current mirror of the transistors Q33 and Q34, so that the killer output becomes "L".

When the voltage at the terminal P is lower than the reference voltage Vref, the transistor Q31 is turned on, a current flows through the resistor R18 by the current mirror of the transistors Q35 and Q36, and the base potential of the transistor Q32 becomes higher than the reference voltage Vref. This offset voltage disappears when the transistor Q30 turns on.
In other words, this offset voltage has a hysteresis width so that once the killer on or off mode is entered, it is difficult to shift to the opposite mode.

The sensitivity control circuit includes two symmetrical circuits: transistors Q38 to Q46 operated by the gate current source Q40 and transistors Q47 to Q55 operated by the constant current source Q55. The circuit operated by the gate current source Q40 increases the sensitivity of the killer detection circuit 5. If the voltage at terminal P is higher than VL, current flows through transistor Q39 and transistors Q43 and Q4
The current flows through the switches of the transistors Q45 and Q46 via the current mirror 4. AC for transistors Q45 and Q46
The control voltage of C determines which current flows. Assuming that the ACC is operating at the operating point A, the current flows to the transistor Q45, and the current flows to the transistors Q2 and Q3 via the current mirror circuit of the transistors Q41 and Q42. A bias current flows in parallel with the collector current of the transistor Q1, which is the bias current of the killer detection circuit 5, and the detection output current also increases. Therefore, the sensitivity of the killer detection circuit can be increased.

Transistor, the other sensitivity control circuit
The portions of Q47 to Q55 operate the reference voltage Vref. If the voltage at terminal P is higher than VL, transistor Q51 turns on,
Through the current mirror circuit of the transistors Q49 and Q50,
A current flows through the switches of the transistors Q47 and Q48. When the ACC operates at the point A, the transistor Q48 is turned on, and the current flowing through the resistor 14 via the current mirror circuit of the transistors Q53 and Q54 is reduced. In this way, the comparison voltage of the level comparison circuit can be reduced, so that the mode can be shifted to the color mode even if the voltage of the terminal P is low.

FIG. 6 shows the operation levels of the actual circuit described above. sensitivity
The Up zone indicates an area where the sensitivity of the Yorranistas Q38 and Q39 and Q51 and Q52 is increased to increase the sensitivity. Each of the operating pairs has an area where the operation pair operates linearly.

By doing so, the sensitivity of the entire killer discrimination system can be increased by multiplying the operating point (control voltage) of the ACC by the output voltage of the killer detection circuit, so that an adaptive and effective case-by-case compatible A type discrimination circuit can be realized. For black and white broadcasting,
Since the present system does not increase the sensitivity of the killer discrimination circuit, the black-and-white broadcast is not erroneously discriminated as the color mode as when the killer discrimination sensitivity is simply increased.

The above is true for both NTSC and PAL color signal broadcasting systems. In the case of the PAL system, the RY color difference signal is inverted and sent for each horizontal synchronization, and a circuit for determining this is required. However, a line determination circuit may be added to the system of the present invention as it is. Description is omitted.

In addition, there are various examples of the specific circuit of the killer detection circuit in addition to FIG. 4, and increasing the bias current of the killer detection circuit to increase the sensitivity is only one example. Some level comparison circuits have a reference level as a current. In this case, the sensitivity Up may be performed by current control of a reference current source.

[Effects of the Invention] As described above, by using the circuit of the present invention, it is possible to eliminate color erasure when a color television signal is received in a weak electric field, and to determine the same as in the past even when a monochrome signal is received. Can have performance.

[Brief description of the drawings]

FIG. 1 is a system diagram of a television signal type discriminating circuit of the present invention, FIG. 2 is a signal waveform diagram for explaining the operation of FIG. 1, and FIG. 3 is an explanation of the operation of the ACC circuit of FIG. FIG. 4 is a circuit diagram showing a specific embodiment of the killer detection circuit of FIG. 1, FIG. 5 is a level chart used to explain the operation level of FIG. 4, and FIG. The figure is a conventional system diagram. 1 ACC circuit 2 Color synchronous reproduction circuit 4 Color difference demodulation circuit 5 Killer detection circuit 6 Level comparison circuit

Claims (3)

(57) [Claims] An ACC circuit for stabilizing the amplitude of a chroma signal of a composite video signal, a color synchronous reproduction circuit for reproducing first and second continuous waves synchronized with a burst signal output of the ACC circuit, A first output continuous wave of the synchronous reproduction circuit and the ACC
A killer detection circuit that synchronously detects the output burst signal of the circuit; and a level comparison circuit that compares the detection output of the killer detection circuit with a predetermined reference level and detects that the synchronous detection output exceeds the reference level. A color difference demodulation circuit for demodulating an output chroma signal of the ACC circuit by a second output continuous wave of the color synchronous reproduction circuit, and a chroma signal for preventing the demodulated signal from appearing at the output of the demodulation circuit by the output of the level comparison circuit. Means for interrupting the signal path and means for controlling the detection sensitivity of the killer detection circuit or the reference voltage of the level comparison circuit only when the control information of the ACC circuit and the detection output information of the killer detection circuit satisfy predetermined conditions. 1. A television signal type discriminating circuit comprising: 2. A signal for identifying that an ACC circuit is closed for an incoming television signal and a signal for identifying that a component obtained by synchronously detecting a burst is present in an output of a killer detection circuit. 2. The television signal format discrimination circuit according to claim 1, wherein the detection sensitivity of the killer detection circuit or the reference voltage of the level comparison circuit is controlled only when the following condition is satisfied. 3. A killer having a function of flowing an output current of a killer detection circuit to a holding capacitor and a load resistance one of which is connected to a first reference voltage source, and cutting off the load resistance from the killer detection circuit for one horizontal period after detection. A detection circuit, a differential pair for detecting a potential difference between the voltage of the storage capacitor and a second reference voltage source,
A level comparison circuit comprising a second and a third differential pair for detecting a potential difference between the first reference voltage and the storage capacitor voltage, wherein a means for setting an output of the first differential pair to a killer output; Outputs of the second and third differential pairs are supplied and are respectively switched by first and second switch means which can be switched by ACC control information, and the detection sensitivity of the killer detection circuit is controlled by the output of the first switch means. Means for performing
2. A television signal type discriminating circuit according to claim 1, further comprising means for controlling the voltage of the second reference voltage source by the output of said switch means.