JPH05336470A - Video signal limiting circuit - Google Patents

Video signal limiting circuit

Info

Publication number
JPH05336470A
JPH05336470A JP13831992A JP13831992A JPH05336470A JP H05336470 A JPH05336470 A JP H05336470A JP 13831992 A JP13831992 A JP 13831992A JP 13831992 A JP13831992 A JP 13831992A JP H05336470 A JPH05336470 A JP H05336470A
Authority
JP
Japan
Prior art keywords
circuit
video signal
input
signal
output terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13831992A
Other languages
Japanese (ja)
Other versions
JP3203762B2 (en
Inventor
Masaya Fujita
雅也 藤田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP13831992A priority Critical patent/JP3203762B2/en
Publication of JPH05336470A publication Critical patent/JPH05336470A/en
Application granted granted Critical
Publication of JP3203762B2 publication Critical patent/JP3203762B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Television Receiver Circuits (AREA)

Abstract

PURPOSE:To prevent a beam current from exceeding a standardized upper limit value when excessive video signals are inputted and to improve the freedom at the time of setting brightness or the like relating to the video signal limiting circuit suitable for being applied to a television receiver. CONSTITUTION:A clamping circuit 4 is inserted between the luminance signal output terminal 3 of a video signal switching circuit 1 and the inverse amplification circuit 5 of a delay circuit 6 for loss compensation and signals with amplitude more than specified are saturated and limited at an inverse circuit 7. Only the signals with the amplitude less than specified are inputted to a video signal processing circuit 10.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、テレビジョン受像機に
おける映像信号制限回路に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal limiting circuit in a television receiver.

【0002】[0002]

【従来の技術】従来、この分野の技術としてはABL
(自動輝度制限)回路によるものがあり、図2に示すよ
うにビ−ム電流の増加に伴う電圧降下を利用して映像信
号処理回路の輝度制御電圧及びコントラスト制御電圧を
押さえるようにした回路を使用しているものが主流であ
った。
2. Description of the Related Art Conventionally, ABL is a technology in this field.
There is an automatic brightness limiting circuit, and as shown in FIG. 2, a circuit for suppressing the brightness control voltage and the contrast control voltage of the video signal processing circuit by utilizing the voltage drop accompanying the increase of the beam current is provided. The one used was the mainstream.

【0003】[0003]

【発明が解決しようとする課題】しかしながら上記構成
の回路では、コントラスト制御範囲の限界によるビ−ム
電流の規格はずれや、輝度制御の過補正による画面の明
るさ不足、あるいはビ−ム電流検出の時定数によるAB
Lの発振等の問題があり効率良く設計を行いにくいとい
う問題があった。
However, in the circuit having the above structure, the beam current is out of the standard due to the limit of the contrast control range, the screen brightness is insufficient due to the overcorrection of the brightness control, or the beam current is detected. AB by time constant
There is a problem that L is oscillated and it is difficult to design efficiently.

【0004】[0004]

【課題を解決するための手段】本発明は、上記問題を解
決するために入力映像信号切り替え回路と映像信号処理
回路との間に映像信号の振幅を制限する回路を挿入し、
規格内信号入力時の画面の明るさの設定及びビ−ム電流
の制限を効率良く設定出来るようにするものである。
In order to solve the above problems, the present invention inserts a circuit for limiting the amplitude of a video signal between an input video signal switching circuit and a video signal processing circuit,
It is possible to efficiently set the screen brightness and the beam current limit when a signal within the standard is input.

【0005】[0005]

【作用】本発明によれば、上記のように入力映像信号切
り替え回路より出力される輝度信号をクランプしペデス
タルレベルを揃えてから増幅回路に入力するため、一定
の振幅レベル以上の信号が入力されると、増幅回路内で
一定振幅以上の部分が飽和し振幅レベルに制限がかか
る、これにより映像信号処理回路には一定の振幅以下の
映像信号のみが入力されることになり、ABL回路の設
定が容易になり同時に、ビ−ム電流も規格値内に納まる
ため耐久性の向上がはかれる。
According to the present invention, since the luminance signal output from the input video signal switching circuit is clamped and the pedestal level is adjusted as described above before being input to the amplifier circuit, a signal having a certain amplitude level or more is input. Then, a portion with a certain amplitude or more is saturated in the amplifier circuit and the amplitude level is limited. This causes only a video signal with a certain amplitude or less to be input to the video signal processing circuit. At the same time, the beam current falls within the standard value, and the durability is improved.

【0006】[0006]

【実施例】以下、本発明の実施例について図面を参照し
ながら説明する。
Embodiments of the present invention will be described below with reference to the drawings.

【0007】図1は本発明の第1の実施例を示す映像振
幅制限回路の概略構成図である。図1において、1は映
像信号切り替え回路、2はY/C分離回路、3は輝度信
号出力端子、4はクランプ回路、5は反転増幅回路、6
は遅延回路、7は反転回路である。
FIG. 1 is a schematic configuration diagram of a video amplitude limiting circuit showing a first embodiment of the present invention. In FIG. 1, 1 is a video signal switching circuit, 2 is a Y / C separation circuit, 3 is a luminance signal output terminal, 4 is a clamp circuit, 5 is an inverting amplifier circuit, 6
Is a delay circuit, and 7 is an inverting circuit.

【0008】図1において、映像信号切り替え回路1に
て選択された映像信号は、Y/C分離入力の場合はその
輝度信号がそのまま輝度信号出力端子3より出力され、
コンポジット入力の場合はY/C分離回路2を経て分離
された輝度信号が輝度信号出力端子3より出力される。
次に出力された輝度信号はクランプ回路4によりそのペ
デスタルレベルが一定の電圧に固定され反転増幅回路5
に入力される。但しこの反転増幅回路5は遅延回路6と
のインピ−ダンス整合の為R2とR3の値を同値にしそ
れ等の並列抵抗値とR1を等しく設定している為反転し
ているだけの動作となる。そして、反転回路7ではTR
1のエミッタ側にて信号振幅の制限行いコレクタ側で信
号の極性を元に戻し出力としている。D1はTR1の温
度特性補償用として用いている。
In FIG. 1, the video signal selected by the video signal switching circuit 1 is the brightness signal output from the brightness signal output terminal 3 as it is in the case of Y / C separation input.
In the case of composite input, the luminance signal separated through the Y / C separation circuit 2 is output from the luminance signal output terminal 3.
The luminance signal output next is fixed to a voltage whose pedestal level is constant by the clamp circuit 4, and the inverting amplifier circuit 5
Entered in. However, since the inverting amplifier circuit 5 sets the values of R2 and R3 to the same value for impedance matching with the delay circuit 6 and sets the parallel resistance values thereof and R1 to the same value, the inverting amplifier circuit 5 operates only by inverting. . Then, in the inverting circuit 7, TR
The signal amplitude is limited on the emitter side of 1 and the polarity of the signal is restored to the original on the collector side for output. D1 is used for temperature characteristic compensation of TR1.

【0009】[0009]

【発明の効果】以上、詳細に示したように本発明によれ
ば、テレビジョン受像機において過大な映像信号が入力
されても一定の振幅レベル以下の部分だけが画面に映し
出される為規定値以上のビ−ム電流が流れることもなく
またABL回路の設定の自由度が増すためより明るい画
面づくりを容易に行う事ができる。
As described above in detail, according to the present invention, even if an excessive video signal is input to a television receiver, only a portion having a certain amplitude level or less is displayed on the screen, so that the value is equal to or more than a specified value. Beam current does not flow and the degree of freedom in setting the ABL circuit is increased, so that a brighter screen can be easily created.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第一の実施例を示す映像信号制限回路
の概略構成図
FIG. 1 is a schematic configuration diagram of a video signal limiting circuit showing a first embodiment of the present invention.

【図2】従来の回路の概略構成図FIG. 2 is a schematic configuration diagram of a conventional circuit.

【符号の説明】[Explanation of symbols]

1 映像信号切り替え回路 2 Y/C分離回路 3 輝度信号出力端子 4 クランプ回路 5 反転増幅回路 6 遅延回路 7 反転回路 8 映像信号入力端子群 9 同期信号 10 映像信号処理回路 11 輝度制御端子 12 コントラスト制御端子 13 ABL回路 1 Video signal switching circuit 2 Y / C separation circuit 3 Luminance signal output terminal 4 Clamp circuit 5 Inversion amplification circuit 6 Delay circuit 7 Inversion circuit 8 Video signal input terminal group 9 Synchronization signal 10 Video signal processing circuit 11 Luminance control terminal 12 Contrast control Terminal 13 ABL circuit

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 輝度信号の出力端子を有する入力映像信
号切り替え回路と、Y/C分離信号入力時とコンポジッ
ト信号入力時の同期信号との時間合わせのための遅延回
路と、前記遅延回路の前段及び後段に挿入され遅延回路
での損失補正を行うための増幅回路と、前記前段増幅回
路の入力と前記映像信号切り替え回路の輝度信号出力端
子との間に挿入されたクランプ回路とを備えたテレビジ
ョン受像機において、過大な映像信号が入力された場合
にCRTのビ−ム電流が規格値以上流れないようにし、
耐久性及び設計裕度を向上させることを目的とした映像
信号制限回路。
1. An input video signal switching circuit having a luminance signal output terminal, a delay circuit for time synchronization between a Y / C separation signal input and a sync signal when a composite signal is input, and a preceding stage of the delay circuit. And a television provided with an amplifier circuit inserted in the latter stage for performing loss correction in the delay circuit, and a clamp circuit inserted between the input of the former stage amplifier circuit and the luminance signal output terminal of the video signal switching circuit. In John receiver, when the excessive video signal is input, the beam current of CRT does not flow beyond the standard value,
A video signal limiting circuit intended to improve durability and design latitude.
JP13831992A 1992-05-29 1992-05-29 Video signal limiting circuit Expired - Fee Related JP3203762B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13831992A JP3203762B2 (en) 1992-05-29 1992-05-29 Video signal limiting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13831992A JP3203762B2 (en) 1992-05-29 1992-05-29 Video signal limiting circuit

Publications (2)

Publication Number Publication Date
JPH05336470A true JPH05336470A (en) 1993-12-17
JP3203762B2 JP3203762B2 (en) 2001-08-27

Family

ID=15219122

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13831992A Expired - Fee Related JP3203762B2 (en) 1992-05-29 1992-05-29 Video signal limiting circuit

Country Status (1)

Country Link
JP (1) JP3203762B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100468706B1 (en) * 1998-03-17 2005-04-06 삼성전자주식회사 AL non-preamplifier with luminance compensation circuit
KR100493007B1 (en) * 1998-06-17 2005-08-01 삼성전자주식회사 Preamplifier and its operation method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100468706B1 (en) * 1998-03-17 2005-04-06 삼성전자주식회사 AL non-preamplifier with luminance compensation circuit
KR100493007B1 (en) * 1998-06-17 2005-08-01 삼성전자주식회사 Preamplifier and its operation method

Also Published As

Publication number Publication date
JP3203762B2 (en) 2001-08-27

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