JPS62274790A - Optical and electronic integrated circuit and manufacture thereof - Google Patents

Optical and electronic integrated circuit and manufacture thereof

Info

Publication number
JPS62274790A
JPS62274790A JP11747986A JP11747986A JPS62274790A JP S62274790 A JPS62274790 A JP S62274790A JP 11747986 A JP11747986 A JP 11747986A JP 11747986 A JP11747986 A JP 11747986A JP S62274790 A JPS62274790 A JP S62274790A
Authority
JP
Japan
Prior art keywords
semiconductor layer
layer
composition
conductivity type
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11747986A
Other languages
Japanese (ja)
Inventor
Yuji Hasumi
蓮見 裕二
Jiro Tenmiyo
天明 二郎
Hajime Asahi
一 朝日
Atsuo Yukimae
篤郎 幸前
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP11747986A priority Critical patent/JPS62274790A/en
Publication of JPS62274790A publication Critical patent/JPS62274790A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bipolar Transistors (AREA)
  • Semiconductor Lasers (AREA)

Abstract

PURPOSE:To increase the light confining effect, and to reduce the threshold current of a photo electron integrating circuit by a method wherein quantum well structure is adopted as the active layer of an LU to enlarge oscillation level density, gain is enhanced to contrive to reduce an oscillation threshold current, and both the sides of the active layer are made to have gradient band gap structure. CONSTITUTION:A second semiconductor layer 4 having gradient band gap structure is consisting of an n-type AlGaAs layer, the rate of composition of Al is (x) at the boundary between a semiconductor layer 3, the rate of composition of Al is zero at the boundary between a semiconductor layer 5, and the rate of composition of Al varies continuously corresponding to thickness of the layer at the midway between them. A third semiconductor layer 5 of narrow gap is consisting of a quantum well layer (impurity concentration is 5X10<17>/cm<3>) of n-type GaAs or undoped GaAs, thickness thereof is the degree of 50-300Angstrom , and to be used as the active layer of a laser diode (LD). A fourth semiconductor layer 6 having gradient band gap structure is consisting of p-type AlGaAs, the rate of composition of Al is zero at the boundary between the semiconductor layer 5, the rate of composition of Al is (x) at the boundary between a fifth semiconductor layer 7, and the rate of composition of Al varies continuously corresponding to thickness of the layer at the midway between them. The fifth semiconductor layer 7 of wide gap is consisting of p-type AlGaAs, and the layer thereof is the part to be used as the clad layer of the LD.

Description

【発明の詳細な説明】 3、発明の詳細な説明 (産業上の利用分野) 本発明は、高速変調可能なf、通信用送信器として使用
する定めの半導体光源装置に関するものである。
Detailed Description of the Invention 3. Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a semiconductor light source device capable of high-speed modulation and used as a communication transmitter.

(従来技術及び発明が解決しょうとする問題点ン半専俸
V−ザとそれt駆動・変調する電子素子ケ同−基板上に
一体化した光・電子集積回路(optOElectri
c Integrated C1rcuit  以下、
0EICと記す)は、光送信器の爾迷化・高信頼化會は
かる上で効果的である。特に、ヘテロ・バイポーラ会ト
ランジスタ(HeterostructureBipo
lor Transister  以下HBTと配子)
は高い電流駆動能力と高速動作性を待つ几め、0EIC
の電子素子として適している。
(The problem to be solved by the prior art and the invention is that the optoelectronic integrated circuit (optOelectri
c Integrated C1rcuit Below,
0EIC) is effective in making optical transmitters more confusing and more reliable. In particular, heterostructure bipolar transistors (Heterostructure Bipo
lor Transister (hereinafter referred to as HBT and ligand)
0EIC has high current drive capability and high speed operation.
It is suitable as an electronic device.

この工うZHBTとレーザダイオード(La5erDi
 ode以下LDと記す)を組合せ窺ogICの例とし
て、ジエ・カアツ(J、 Katz )等の報告(Ap
pl、 Phys、 Lett、 37(2)、198
0)がある。第3図は上記の報告に示さtL7’C4#
を成を示すもので、この素子はn”−GaAs基板20
上に、基板側エリ第11W n −AlGaAs 21
 、第284 p −GaAs 22、第3NIn −
AlGaAs 23エピタキシャル映ヲ成長し、npn
構造工9なるHBTを製作すると共に、Beイオンを第
3層おからp−GaAs 22まで圧入することで、g
37123のn −AtcaAsの一部tp型24に変
え、npp構遺構造成るLDとじても動作させられる工
う工夫さtしている。しかしながら、このLうl構造に
は仄の工うな欠点かめる。
This ZHBT and laser diode (La5erDi)
ode (hereinafter referred to as LD) is an example of a combination of log IC, as reported by J. Katz et al. (Ap
pl, Phys, Lett, 37(2), 198
0). Figure 3 is shown in the above report tL7'C4#
This device is based on an n''-GaAs substrate 20.
On the top, the substrate side area No. 11 W n -AlGaAs 21
, 284th p-GaAs 22, 3rd NIn-
AlGaAs 23 epitaxial film grown and npn
By manufacturing an HBT with structural engineering 9 and press-fitting Be ions up to the third layer of okara p-GaAs 22,
A part of the n-AtcaAs of 37123 was replaced with the tp type 24, and a device was devised so that it could be operated even with an LD having an npp structure. However, this structure has some disadvantages.

(イ)HBTのベース層全同時にLDの活性層としても
使うため、自由キャリアによる光吸収を防ぐ必安土、こ
の層のキャリア濃度を高く(≧5XIOI?α−39す
ることができない。一方、HBTの動作速度については
、その目安となるカットCo:コレクタ容室うで与えら
れることから分るように、ベース抵抗の減少に伴って高
速となる。
(a) Since the base layer of HBT is also used as the active layer of LD at the same time, it is necessary to prevent light absorption by free carriers, and the carrier concentration of this layer is high (≧5XIOI? α-39 cannot be achieved.On the other hand, HBT As for the operating speed, as can be seen from the standard cut Co: given by collector chamber arm, the operating speed becomes faster as the base resistance decreases.

したがって、ベース抵抗の低減が十分に行えないカアツ
らの構造では、高速動作可能な素子を作ることが難しい
Therefore, with the structure of Kaatsu et al., in which the base resistance cannot be sufficiently reduced, it is difficult to create a device capable of high-speed operation.

(ロ)n+基板を使い、基板下面をコレクタ電極として
いるため、コレクタ面積が大きくなジコレクタ容tCc
が大きい。し九がって、先程のfcの表穴から判るよう
に、HBTの高速化には適していない。
(b) Since an n+ substrate is used and the bottom surface of the substrate is used as the collector electrode, the collector area is large.
is large. Therefore, as can be seen from the fc table hole mentioned earlier, it is not suitable for increasing the speed of HBT.

(9コレクタ電極が下面にある文め、素子間分離や配線
が難しい構造である。
(9) The collector electrode is on the bottom surface, making it difficult to separate elements and conduct wiring.

以上説明し之りうに、カアツらの素子は、高速化・集積
化の点で問題かめるといえる。
As explained above, it can be said that Kaatsu et al.'s device poses problems in terms of speeding up and integration.

(問題点全解決するtめの手段) 本発明の目的は、上述し友問題点、すなわちビ)HBT
、LD各々の高性能化に適した構造ではない点 (ロ)素子間分離、配線等の点で集積化が難しい点 を解決し、高速かつ集積化に適し九0EICを提供する
ことにある。
(Tth Means for Solving All Problems) The object of the present invention is to solve the above-mentioned problems, namely, B) HBT.
, the structure is not suitable for improving the performance of each LD (b) The object is to solve the problem that integration is difficult in terms of isolation between elements, wiring, etc., and to provide a 90EIC that is high-speed and suitable for integration.

上記の目的を達成する之め、本発明は半絶縁性基板上に
、第1導電型のワイドギャップの第1の半導体層、#4
斜バンドギャップを有する第1導電型の第2の半導体層
、第1導it型或いは不純物を添加しないナロウギヤツ
プの第3の半導体層、傾斜バンドギャップを有する′W
J24を型の第4の半導体層、第2導電型のワイドギャ
ップの第5の半4体層が順次積層され定多層エピタキシ
セル膜内の第1の領域に、第3の半導体層を活性層、第
1及び第5の半導体層全クラッド層とするGRIN−S
CHレーザが構成され、多層エピタキシャル膜内の第2
の領域に、第1〃為ら第3の半導体+m tコレクタ、
第4.第5の半導体層内に形成された第14亀型の不純
物領域をエミッタ、第4の半導体層内のエミッタとコレ
クタに挾まi″L7t、領域全ベースとするヘテロ接合
バイポーラトランジスタが構成されることを特徴とする
光・電子集積回路を発明の要旨とするものである。
To achieve the above object, the present invention provides a wide gap first semiconductor layer of a first conductivity type, #4, on a semi-insulating substrate.
a second semiconductor layer of a first conductivity type having an oblique band gap; a third semiconductor layer of a first conductivity type or a narrow gap with no impurity added; 'W having an oblique band gap;
A fourth semiconductor layer of J24 type and a fifth wide-gap semi-quadruple layer of a second conductivity type are sequentially stacked in a first region in a constant multilayer epitaxy cell film, and a third semiconductor layer is formed as an active layer. , the first and fifth semiconductor layers are all cladding layers GRIN-S
A CH laser is constructed and the second laser in the multilayer epitaxial film is
In the region, the first to third semiconductor + m t collector,
4th. A heterojunction bipolar transistor is constructed in which the 14th turtle-shaped impurity region formed in the fifth semiconductor layer is the emitter, and the entire region is the base, i''L7t sandwiched between the emitter and collector in the fourth semiconductor layer. The gist of the invention is an optical/electronic integrated circuit characterized by the following.

さらに本発明に半絶縁性基板上に、第1導電型のワイド
ギャップの第1の半導体層、傾斜バンドギャップを有す
る第1導電型の第2の半導体層、第14屯型或いに不純
物を添加しないナロウギヤツプの第3の半導体層、傾斜
バンドギャップ七育する第導電型の第4の半導体層、第
導電型のワイドギャップの第5の半導体層を順次積層し
て多層エピタキシャル膜を形成し、絶縁層にLす、第1
の領域及び第2の領域に分離し、前記の多層エピタキシ
ャル膜内の第1の領域に、第3の半導体層を活性層、第
1及び第5の半導体層をクラッド層とするGRIN−S
CHレーザ會構成し、多層エピタキシャル膜内の第2の
領域において、第4.第5の半導体層内にイオン注入法
を用いて第1導電型の不純物領域を選択的に形成し、第
1から8g3の半導体層をコレクタ、第4.第5の半導
体層内に形成され7?、第14′tJL型の不純物領域
をエミッタ、第4の半導体層内のエミッタとコレクタに
挾まれ九領域をベースとするヘテロ接合バイポーラトラ
ンジスタを構成することを特徴とする光・電子集積回路
の*遣方+9−を発明の要旨とするものである0 本発明の特徴は次の点にある。
Further, in the present invention, a wide-gap first semiconductor layer of a first conductivity type, a second semiconductor layer of a first conductivity type having a sloped bandgap, a 14th conductivity type semiconductor layer, or an impurity layer are formed on a semi-insulating substrate. forming a multilayer epitaxial film by sequentially stacking a narrow-gap third semiconductor layer without additives, a fourth conductivity type semiconductor layer with a graded bandgap, and a wide-gap fifth conductivity type semiconductor layer; L on the insulating layer, first
GRIN-S is separated into a region and a second region, and in the first region in the multilayer epitaxial film, the third semiconductor layer is an active layer, and the first and fifth semiconductor layers are cladding layers.
A CH laser system is configured, and in a second region within the multilayer epitaxial film, a fourth. A first conductivity type impurity region is selectively formed in the fifth semiconductor layer using an ion implantation method, and the first to 8g3 semiconductor layers are used as a collector, and the fourth and fourth semiconductor layers are used as a collector. Formed within the fifth semiconductor layer 7? , an optical/electronic integrated circuit comprising a 14'tJL type impurity region as an emitter, a 9 region sandwiched between an emitter and a collector in a fourth semiconductor layer, and a heterojunction bipolar transistor as a base. The gist of the invention is the way of reading +9-.0 The features of the present invention are as follows.

(イ)LDの活性層として、電子井戸構造(不純物濃度
5 x lQ”/crn’ ) f採用し発掘準位密度
を大にし、ゲインを高めることで発振閾値電流の低下を
はかると共に、活性層両swm斜バンドギャップ構造と
することで光閉じ込め効果を増し、一層の閾値vL流低
減をはかることができる。
(a) As the active layer of the LD, an electron well structure (impurity concentration 5 x lQ"/crn') is adopted to increase the density of excavated levels and increase the gain, thereby reducing the oscillation threshold current. By forming both swm diagonal bandgap structures, the light confinement effect can be increased and the threshold value vL flow can be further reduced.

(ロ) 上記LDの活性層’kHBTのベースI−と共
有する従来の構造では、活性Nt麓子井戸構造とするた
め、薄層化(〜0.01μm)すると、ベース抵抗が増
大し、HBTの動作速度が遅くなる欠点を有してい友。
(b) In the conventional structure in which the active layer of the above LD is shared with the base I- of the HBT, it is an active Nt footwell structure, so when the layer is thinned (~0.01 μm), the base resistance increases, and the HBT Friend has the disadvantage of slow operation speed.

この点、本発明では2つの傾斜バンドギャップ層の一方
のみ七HBTのベース層とすることで、ベース層の薄層
化(〜0.2μm)を回避することができる。
In this regard, in the present invention, by using only one of the two graded bandgap layers as the base layer of the 7HBT, it is possible to avoid making the base layer thinner (up to 0.2 μm).

ビ1 妊らに、一方の傾斜バンドギャップ層をHBTの
ベース層(適切な不純物炭度約5XlO’ンcm’)と
することで、ベース層内に電界を生じさせ、キャリアの
加速が行なわれる構造としている。
B1 In addition, by using one of the graded bandgap layers as the base layer of the HBT (appropriate impurity carbon content of approximately 5XlO'cm'), an electric field is generated in the base layer and carriers are accelerated. It has a structure.

この加速により、キャリアは従来の均一ベースにおける
拡散速度;りも速い速度(ドリフト速V)全もっことに
なり、結果とじて電流増幅率金増大丁ゐことができる。
Due to this acceleration, the carriers have a higher diffusion speed (drift speed V) than the conventional uniform base, and as a result, the current amplification factor can be increased.

(へ)LDの基本となるpn構造の膜をエピタキシャル
膜で形成し、イオン注入もしくは気相拡散にぶり、上部
傾斜バンドギャップ層内に1で達するn型不純物憤域を
形成してエミッタとし、npn構造のHBTk製作する
。この:うに簡単なプロセスでLDとHBTとを同一基
板上に搭載できる。
(f) A film with a pn structure, which is the basis of the LD, is formed as an epitaxial film, and an n-type impurity region reaching 1 is formed in the upper inclined bandgap layer by ion implantation or vapor phase diffusion to form an emitter. Fabricate HBTk with npn structure. LD and HBT can be mounted on the same substrate with this simple process.

(ホ)半絶縁性基板を使用するので、素子間分離。(e) Since a semi-insulating substrate is used, elements can be isolated.

配線が容易に行え、同時に、コレクタ容量が低減できる
ので、素子の高速動作が可能である。
Wiring can be done easily and at the same time, collector capacitance can be reduced, so high-speed operation of the device is possible.

(へ)LDの活性層(適切な不純物濃度≦5 X 10
’7zりとHBTのベース層(適切な不純物濃度約5×
10IンcPn勺とを夫々適切な不純物濃度とすること
により、LDの閾値電流を低く、かつHBT。
(f) LD active layer (appropriate impurity concentration ≦5 x 10
'7z HBT base layer (appropriate impurity concentration approximately 5x
By setting appropriate impurity concentrations for 10I and cPn, respectively, the threshold current of the LD can be lowered and the HBT can be reduced.

カットオフ周波数を高くすることができる。The cutoff frequency can be increased.

以上説明し′fc素子構造は、従来のものと比べ。As explained above, the FC element structure is compared with the conventional one.

全体の層構成、特に活性層の構造が全く異なっている。The overall layer structure, especially the structure of the active layer, is completely different.

次に不発明の実施?lj k添付図面について説明する
Next is the implementation of non-invention? lj kThe attached drawings will be explained.

なお実施例は一つの例示であって、不発明の精神を逸脱
しない範囲で独々の変更あるいに改jLf行いうろこと
は言うまでもない。
It should be noted that the embodiments are merely illustrative, and it goes without saying that individual changes and modifications may be made without departing from the spirit of non-invention.

第1図は不発明の実施例を示すもので、素子の縦構造を
示している。図において1は半絶縁性GaAs基板、2
rLLDとHBTの=zレクタ篭極をとるためのn+−
GaAs層、3はワイドギャップの第1の半導体層でn
 −At、Ga1 、As (0(x<])工りn5、
LDのクラッド及びHBTのコレクタ層、4は1#4斜
バンド構造をもつ第2の半導体層でn −AlGaAs
層エリなり、半導体層3との境界ではM組成の割合が2
、半導体層5との境界ではM組成がゼロで、その間は、
層の厚でに伴いM組成が連続的に変化している。
FIG. 1 shows an embodiment of the invention, showing the vertical structure of the device. In the figure, 1 is a semi-insulating GaAs substrate, 2
rLLD and HBT = n+- to take the z rector cage pole
GaAs layer 3 is a wide gap first semiconductor layer with n
-At, Ga1, As (0(x<]) processing n5,
LD cladding and HBT collector layer, 4 is a second semiconductor layer with a 1#4 oblique band structure, and is made of n-AlGaAs.
At the layer edge, the M composition ratio is 2 at the boundary with the semiconductor layer 3.
, the M composition is zero at the boundary with the semiconductor layer 5, and in between,
The M composition changes continuously with the layer thickness.

5はナロウギヤツプの第3の半導体層で、n−GaAs
もしくはアンドープGaAs (1)量子井戸層(不純
物濃度5XlO’ンm’)で、その厚ざは5o〜3(1
0)A程度で、LDの活性層となる。6は傾斜バンド構
造?もつ第4の半導体層で、p−A江aAs工9なり、
半導体層5との境界ではM組成がゼロ、半導体層7との
境界でμM組成は、Mの組成が2で、その間は7mの厚
さに伴い、M組成が連続的に変化している。7にワイド
ギヤングの第5の半導体層でp−AlGaAsエクなり
、LDのクラッド11#となる部分であり、8はp”−
GaAaニジなり、HBTのベース′4極とLDのp菟
極全とる。
5 is a third semiconductor layer with a narrow gap, and is made of n-GaAs.
Or undoped GaAs (1) Quantum well layer (impurity concentration 5XlO'nm'), the thickness of which is 50~3(1
0) At about A, it becomes the active layer of the LD. Is 6 a sloped band structure? The fourth semiconductor layer has a p-AAs process9,
The M composition is zero at the boundary with the semiconductor layer 5, the μM composition is 2 at the boundary with the semiconductor layer 7, and the M composition changes continuously over the 7 m thickness. 7 is the wide-giang fifth semiconductor layer, which is made of p-AlGaAs and becomes the cladding 11# of the LD, and 8 is the p''-
When GaAa is used, the HBT's base 4 poles and the LD's p pole are all taken.

9はイオン圧入もしくに気相拡散法にニジ形成し7tn
型不純物領域でその深さは、半導体層6の傾斜バンドギ
ャップ層の一部にまで達するようにする。HBTのエミ
ッタとなる。
9 is 7tn formed by ion injection or vapor phase diffusion method.
The depth of the type impurity region is made to reach a part of the graded bandgap layer of the semiconductor layer 6. It becomes the emitter of HBT.

B、E、Cに夫々HBTのベース、エミッタ。HBT base and emitter at B, E, and C, respectively.

コレクタ電極、P、Nは夫々LDの電極を示す。Collector electrodes P and N indicate electrodes of the LD, respectively.

次に製造方法について説明する。Next, the manufacturing method will be explained.

半絶縁性基板1のGaAs上に、半導体層2のn−Ga
As1形成し、ついでワイドギャップの第1の半導体層
3のn −AlGaAsを形成し、次に傾斜バンドギャ
ップを有する第2の半導体/m 4のrl −AlGa
Asを形成する。この場合成の組成の割合が半導体ノー
3との境界ではMの組成割合がX、半4俸層5との境界
ではM組成がゼロで、その間は層の厚さに伴い、Mが連
続的に変化するように形成する。この傾斜バンド層の形
成方法については後に述べる。次に第3の半導体層5の
n −GaAsあるいはアンドープのGaAs’i形成
する。この場合Si等の不純物濃度は5 X 10”/
 cm3以下である。その厚さは50〜3(10)A程
度にする。
A semiconductor layer 2 of n-Ga is formed on a semi-insulating substrate 1 of GaAs.
As1 is formed, then a wide-gap first semiconductor layer 3 of n-AlGaAs is formed, and then a second semiconductor layer with a sloped bandgap is formed of rl-AlGaAs of /m4.
Forms As. In this case, the composition ratio of M is X at the boundary with semiconductor no. form in such a way that it changes. A method for forming this inclined band layer will be described later. Next, a third semiconductor layer 5 of n-GaAs or undoped GaAs'i is formed. In this case, the concentration of impurities such as Si is 5 x 10”/
cm3 or less. Its thickness is about 50 to 3 (10) A.

次に#A斜バンドギャップを有する第4の半導体層6の
p−AlGaAs ’fr−形成する。Mの組成は半導
体1= sとの境界ではゼロ、半4 % 7m 7との
境界1:ぼXで、その間は鳩の厚さに伴い、M組成が連
伏的に変化している。次にワイドギャップの第5の半導
体層7であるp −AンaAs f形成して、多層エビ
タキ/セル映全形成す/bO しかしてこの多j−エピタキシャル膜内にB、Hなどの
イオンを注入して絶縁# 10 i形成し、第1〃、び
第2の領域に分離する。しかして第1の領域内に、半導
体Ij5全后注M、半導体層3及び7t・クラッド層と
するGRIN−SCHンーザを構成し、電極P、Nを夫
々半導体層8.2に形成する0次に多j−エピタキシセ
ル埃円の第2の領域内において、半導体1f46.7の
一部にイオン注入法を用いて、n型の不純物鎖酸9を形
成し、褐1ないし第3の半4俸鳩である3〜5tコレク
タ、第4゜第5の半導体層6.7円に形成され九n型不
純物禎域9′!i1′エミッタ、第4の半導体層6I7
3のエミッタとコレクタに挾まれた領域をベースとする
ヘテロ接合バイポーラトランジスタを構成する0B、E
、CH夫々ベース、エミッタ、コレクタ電極である。
Next, a fourth semiconductor layer 6 of p-AlGaAs'fr- having a #A diagonal bandgap is formed. The composition of M is zero at the boundary with the semiconductor 1=s, and is zero at the boundary with the semiconductor 1:7m7, and the M composition continuously changes with the thickness of the pigeon between them. Next, a wide-gap fifth semiconductor layer 7 of p-A and aAs f is formed, and ions such as B and H are added to this multi-layer epitaxial film/bO. Insulation #10i is formed by implantation and separated into first and second regions. Thus, in the first region, a GRIN-SCH sensor is constructed in which the semiconductor layers 3 and 7 are cladding layers, and the zero-order electrodes P and N are respectively formed in the semiconductor layer 8.2. In the second region of the multi-J-epitaxy cell dust circle, an n-type impurity chain acid 9 is formed in a part of the semiconductor 1f 46.7 using an ion implantation method, and brown 1 to third half 4 are formed. 3~5T collector, 4th degree, fifth semiconductor layer 6.7 degrees formed in 9th n-type impurity region 9'! i1' emitter, fourth semiconductor layer 6I7
0B and E constituting a heterojunction bipolar transistor based on the region sandwiched between the emitter and collector of 3.
, CH are base, emitter, and collector electrodes, respectively.

なお、上記のような傾斜バンド構造は、結晶成長中にそ
の原料となる物質の比率全変化させてゆくことで実現で
きる。例えばAlGaAsの傾斜バンド構造全有機金属
気相エピタキシャル法(Metalorganic V
apor Phase EpttaXy )で製作する
場合には、トリメチルガリウム(TMG)を含む水素ガ
スとアルシン(Ash、)ガスの流量を一定にしながら
、トリメチルアルミニウム(TMA)’に含む水素ガス
の流蓋ヲ連続的に変化させる方法をとるものである。
Incidentally, the above-mentioned inclined band structure can be realized by completely changing the ratio of the raw materials during crystal growth. For example, AlGaAs gradient band structure all-organic vapor phase epitaxial method (Metalorganic V
When manufacturing with apor Phase Eptta This method uses a method to change the

第2図に、上述した層構造をもつHBTの動作状態にあ
る時のバンド図である。ワイドギャップエミッタ9工り
注入され之電子は、図に示す二うにベース内部電界で加
速される丸め、通常の均一ベース層での拡散より速く走
行する。
FIG. 2 is a band diagram of the HBT having the above-described layered structure in an operating state. The electrons injected into the wide gap emitter 9 are rounded and accelerated by the internal electric field of the base, as shown in the figure, and travel faster than diffusion in a normal uniform base layer.

ボルツマン定数、T:絶対温度、q:電子の亀荷蓋)で
見積もられ、ベース層でのギャップの差を△Eg = 
0.2 eVとすると、電子の走行時間τは、均一ベー
スの場合の1/4程度となるoHBTの電流増幅率βは
ベースノーでの電子の速度に比例するので、結果的にβ
が数倍増加する。この工うにβが大きくとれる構造にす
ると、ベースのMJ#に化に伴う(不純物#度FJ 5
 X 10 ”7cm”が適切)βの低下を補償できる
ことになり、電流増幅率を洛丁ことなく HBTの(I
GHz以上の)高速化(II:にかめことが可能となる
Boltzmann's constant, T: absolute temperature, q: electron gap), and the difference in the gap in the base layer is expressed as △Eg =
If it is 0.2 eV, the electron transit time τ is about 1/4 of that in the uniform base case.The current amplification factor β of oHBT is proportional to the electron speed at the base no, so as a result β
increases several times. If we create a structure in which β can be large in this way, the base MJ # will change (impurity # degree FJ 5
X 10 (appropriately 7 cm) can compensate for the decrease in β, and the HBT's (I
It becomes possible to increase the speed (II: faster than GHz).

1だ、量子井戸及び片側の傾斜バンドギャップノ曽はコ
レクタ1llilの空乏層となるため、HBT動作上問
題とはならない。一方、エミッタ側のn−不純物領域の
境界は半導体層7のAlGaAsノーと半導体層6の傾
斜バンドギャップ層の境界もしくは牛4坏ノー6の内部
にとる。これは、半24坏層7内にpn接合ができると
ワイドエミッタ、ナロウベースというHBT本米の効果
が損われるからである。すなわち、エミッタ電流の注入
効率が低下する。
1. Since the quantum well and the inclined band gap on one side become a depletion layer of the collector 1llil, there is no problem in the operation of the HBT. On the other hand, the boundary of the n- impurity region on the emitter side is set at the boundary between the AlGaAs layer of the semiconductor layer 7 and the graded bandgap layer of the semiconductor layer 6, or inside the layer 6. This is because if a pn junction is formed in the semi-conductive layer 7, the HBT's main effects of wide emitter and narrow base will be impaired. That is, the emitter current injection efficiency decreases.

次にLDに対するこの構造の効果を説明する。Next, the effect of this structure on LD will be explained.

LDの発振閾値1は、光閉じ込め係数Fと活性層の利得
αにエリ?=1(α+1 tnl 、で表わ1’   
  LR される。活性層を量子井戸とすると発光準位の準位密度
が増加するため、αが増大する0また、活性層両側を傾
斜バンドギャップとすることで通常の急峻なバンドギャ
ップ変化の場合エリ光閉じ込め係数が増大し、以上2つ
の効果にLジ、発掘閾値の低減が可能となる0さらに、
この列ではりツジガイド構造の採用にエリさらに閾値を
下げる構造としており、予測として10ffIA以下の
電流でレーザ動作が可能と考えられる。
Does the LD oscillation threshold 1 depend on the optical confinement coefficient F and the active layer gain α? = 1 (α+1 tnl , expressed as 1'
LR will be done. When the active layer is made of a quantum well, the level density of the light emitting level increases, so α increases.0 Also, by making both sides of the active layer a sloped bandgap, the optical confinement coefficient decreases in the case of a normal steep bandgap change. increases, and in addition to the above two effects, it becomes possible to reduce the excavation threshold.
In this series, a beam guide structure is used to further lower the threshold value, and it is predicted that laser operation will be possible with a current of 10 ffIA or less.

尚、素子間分離は絶縁層で確保する。Note that isolation between elements is ensured by an insulating layer.

なお第3の半導体層のGaAsの代りにAlGaAsを
用いることもできる。
Note that AlGaAs can also be used instead of GaAs for the third semiconductor layer.

また第1.第2.第4.第5の半導体層がInP 、第
3の半導体層がInGaAsあるいはInGaAsPで
も工い。さらに半絶縁性基板としてQaAsの代りにI
nP’t”用いることもできる。
Also number 1. Second. 4th. The fifth semiconductor layer may be made of InP, and the third semiconductor layer may be made of InGaAs or InGaAsP. Furthermore, as a semi-insulating substrate, I
nP't'' can also be used.

(梵明υ効未) 水上の工うに不発明によれば、 K)HBT、LD各々の高性能化を可能とし之素子構造
金もつ0EICを提供することができる〇これに工って
、このLうな0EICは加入者系光通信の送1g器とし
て利用できる利点がある。
(Banmei υ effect) According to the uninventiveness of the waterworks, K) It is possible to provide an 0EIC with an element structure that makes it possible to improve the performance of both HBT and LD. The UNA0EIC has the advantage that it can be used as a transmitter for subscriber-based optical communications.

(ロ)LDの活性層として、量子井戸構造(不純物I#
度5 X 10 l7cm’ )を採用し発振準位ぞ度
?大にし1ゲインを高めることで発振閾値電流の低下を
μたると共に、活性J−両側を傾斜バンドギャップ構造
とすることで元閉じ込め効果t′4し、一層の閾値戒流
低#、會はかることができる。
(b) Quantum well structure (impurity I#
The oscillation level is 5 x 10 l7cm'). By increasing the gain and increasing the gain, the decrease in the oscillation threshold current can be reduced by μ, and by creating a sloped bandgap structure on both sides of the active J, the original confinement effect t'4 can be achieved, further reducing the threshold current. Can be done.

C→ 上記LDの活性層’t−HBTのベース層と共有
する従来の構造では、活性層會撤子井戸構造とするため
、薄1−化(〜0.01μm)すると、ベース抵抗が増
大し、HBTの動作速度が遅くなる欠点を有してい几。
C→ In the conventional structure in which the active layer of the above LD is shared with the base layer of t-HBT, the active layer has a retracting well structure, so making it thinner (~0.01 μm) increases the base resistance. However, the HBT has the disadvantage of slow operation speed.

この点、不発明では2つの傾斜バンドギャップ層の一方
のみ’t−HB Tのベースt*とすることで、ベース
層の薄層化(〜0.2μrn)を回避することができる
In this regard, in the present invention, by making only one of the two inclined bandgap layers the base t* of 't-HBT, it is possible to avoid making the base layer thinner (~0.2 μrn).

に)さらに、−万の傾斜バンドギャップ層tHBTのベ
ース層(適切な不純物鏝度約5X10”/のりとするこ
とで、ベース層内に電界を生じさせ、キャリアの加速が
行なわれる構造としている。
Furthermore, the base layer of the graded bandgap layer tHBT (appropriate impurity concentration of about 5×10”/glue) generates an electric field in the base layer and accelerates carriers.

この加速にLす、キャリアに従来の均一ベースにおける
拡散速度エリも速い速度(ドリフト速匿ノケもつことに
なり、結果として電流増幅率を増大することができる。
Due to this acceleration, carriers have a higher diffusion rate than the conventional uniform base (drift speed reduction), and as a result, the current amplification factor can be increased.

(ホ)LDの基本となるpn構造の@全エピタキシャル
膜で形成し、イオン注入もしくは気相拡散にエリ、上部
傾斜バンドギャップ層内にまで達するn型不純物領域を
形成してエミッタとし。
(e) It is formed from an all-epitaxial film with a pn structure, which is the basis of an LD, and is used as an emitter by ion implantation or vapor phase diffusion to form an n-type impurity region that reaches into the upper inclined bandgap layer.

npn構造のHBTk製作する。この工うに簡単なプロ
セスでLDとHBTと°を同一基板上に搭載できる。
Fabricate HBTk with npn structure. This simple process allows the LD, HBT, and ° to be mounted on the same substrate.

(へ)中絶縁性基板を便用するので、素子間分離。(F) Since a medium insulating substrate is used, elements can be separated.

配線が容易に行え、同時に、コレクタ容量が低減できる
ので、素子の高速動作が可能である。
Wiring can be done easily and at the same time, collector capacitance can be reduced, so high-speed operation of the device is possible.

(ト)I、Dの活性層(適切な不純物濃度≦5 X 1
0 ’、/cm” )とHBTのベース層(適切な不祠
物#反約5x’10 ”/cm’ )とを夫々適切な不
純物濃度とすることに=ジ、LDの閾値電流を低く、か
つHBTのカットオフ周波数金高くすることができる〇
等の効果を有する。
(g) Active layers of I and D (appropriate impurity concentration ≦5 x 1
By setting appropriate impurity concentrations in the HBT base layer (approx. 0',/cm') and the HBT base layer (approx. It also has the effect of increasing the cutoff frequency of the HBT.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は不発明装置の縦構造を示す図、第2図は不発明
装置のバンド構造を示す図、第3図は従来例を示す。 1・・・・・・半絶縁性GaAs基板 2−−−−−− n”−GaAs層 3・・・・・・第1の半導体層、 n−At、Ga1−
1As層4・・・・・・第2の半導体/1 、傾斜バン
ドギャップn−AlGaAs5・・・・・・第3の半導
体1m、nもしくにアンドープGaAs層6・・・・・
・第4の半導体層、傾斜バンドギャップp−ABGaA
s7・・・・・・第5の半導体層、n−At工Ga1−
、As層8 =−−−・p+−GaAs )fi9・・
・・・・n−不純物領域 10・・・・・・素子間分朧の絶縁層 特許出願人  日本電信電話株式会社 第2図
FIG. 1 is a diagram showing the vertical structure of the uninvented device, FIG. 2 is a diagram showing the band structure of the uninvented device, and FIG. 3 is a diagram showing a conventional example. 1...Semi-insulating GaAs substrate 2------- n''-GaAs layer 3... First semiconductor layer, n-At, Ga1-
1As layer 4...Second semiconductor/1, graded bandgap n-AlGaAs5...Third semiconductor 1m, n or undoped GaAs layer 6...
・Fourth semiconductor layer, graded bandgap p-ABGaA
s7...Fifth semiconductor layer, n-At engineering Ga1-
, As layer 8 =---・p+-GaAs)fi9...
...N-impurity region 10...Insulating layer for inter-element separation Patent applicant Nippon Telegraph and Telephone Corporation Figure 2

Claims (12)

【特許請求の範囲】[Claims] (1)半絶縁性基板上に、第1導電型のワイドギャップ
の第1の半導体層、傾斜バンドギャップを有する第1導
電型の第2の半導体層、第1導電型或いは不純物を添加
しないナロウギヤツプの第3の半導体層、傾斜バンドギ
ャップを有する第2導電型の第4の半導体層、第2導電
型のワイドギャップの第5の半導体層が順次積層された
多層エピタキシャル膜内の第1の領域に、第3の半導体
層を活性層、第1及び第5の半導体層をクラッド層とす
るGRIN−SCHレーザが構成され、多層エピタキシ
ャル膜内の第2の領域に、第1から第3の半導体層をコ
レクタ、第4、第5の半導体層内に形成された第1導電
型の不純物領域をエミッタ、第4の半導体層内のエミッ
タとコレクタに挾まれた領域をベースとするヘテロ接合
バイポーラトランジスタが構成されることを特徴とする
光・電子集積回路。
(1) On a semi-insulating substrate, a first conductivity type wide-gap first semiconductor layer, a first conductivity type second semiconductor layer having a sloped bandgap, and a first conductivity type or narrow gap semiconductor layer to which no impurities are added. A first region in a multilayer epitaxial film in which a third semiconductor layer of , a fourth semiconductor layer of a second conductivity type having a tilted bandgap, and a fifth semiconductor layer of a wide gap of a second conductivity type are sequentially stacked. A GRIN-SCH laser is constructed in which the third semiconductor layer is an active layer and the first and fifth semiconductor layers are cladding layers, and the first to third semiconductor layers are formed in a second region within the multilayer epitaxial film. A heterojunction bipolar transistor in which the layer is the collector, the impurity regions of the first conductivity type formed in the fourth and fifth semiconductor layers are the emitter, and the region sandwiched between the emitter and collector in the fourth semiconductor layer is the base. An optical/electronic integrated circuit characterized by comprising:
(2)第1導電型がn型、第2導電型がp型であること
を特徴とする特許請求の範囲第1項記載の光・電子集積
回路。
(2) The opto-electronic integrated circuit according to claim 1, wherein the first conductivity type is n type and the second conductivity type is p type.
(3)第1、第2、第4、第5の半導体層がAlGaA
s、第3の半導体層がGaAs或いはAlGaAsであ
ることを特徴とする特許請求の範囲第1項記載の光・電
子集積回路。
(3) The first, second, fourth, and fifth semiconductor layers are AlGaA
s. The opto-electronic integrated circuit according to claim 1, wherein the third semiconductor layer is GaAs or AlGaAs.
(4)第2の半導体層が、第3の半導体層との接続部分
でのAl組成が0、第1の半導体層との接続部分でのA
l組成が第1の半導体層のAl組成に等しくなるように
、Al組成が順次変化するAlGaAsであり、第4の
半導体層が、第3の半導体層との接続部分でのAl組成
が0、第5の半導体層との接続部分でのAl組成が第5
の半導体層のAl組成に等しくなるように、Al組成が
順次変化するAlGaAsであることを特徴とする特許
請求の範囲第3項記載の光・電子集積回路。
(4) The second semiconductor layer has an Al composition of 0 at the connection part with the third semiconductor layer, and an Al composition of A at the connection part with the first semiconductor layer.
The fourth semiconductor layer is AlGaAs in which the Al composition changes sequentially so that the Al composition is equal to the Al composition of the first semiconductor layer, and the fourth semiconductor layer has an Al composition of 0, The Al composition at the connection part with the fifth semiconductor layer is the fifth
4. The opto-electronic integrated circuit according to claim 3, wherein the optical/electronic integrated circuit is made of AlGaAs whose Al composition changes sequentially so as to be equal to the Al composition of the semiconductor layer.
(5)第1、第2、第4、第5の半導体層がInP、第
3の半導体層がInGaAs或いはInGaAsPであ
ることを特徴とする特許請求の範囲第1項記載の光・電
子集積回路。
(5) The opto-electronic integrated circuit according to claim 1, wherein the first, second, fourth, and fifth semiconductor layers are InP, and the third semiconductor layer is InGaAs or InGaAsP. .
(6)半絶縁性基板がGaAs或いはInPであること
を特徴とする特許請求の範囲第1項記載の光・電子集積
回路。
(6) The opto-electronic integrated circuit according to claim 1, wherein the semi-insulating substrate is GaAs or InP.
(7)半絶縁性基板上に、第1導電型のワイドギャップ
の第1の半導体層、傾斜バンドギャップを有する第1導
電型の第2の半導体層、第1導電型或いは不純物を添加
しないナロウギヤツプの第3の半導体層、傾斜バンドギ
ャップを有する第2導電型の第4の半導体層、第2導電
型のワイドギャップの第5の半導体層を順次積層して多
層エピタキシャル膜を形成し、絶縁層により、第1の領
域及び第2の領域に分離し、前記の多層エピタキシャル
膜内の第1の領域に、第3の半導体層を活性層、第1及
び第5の半導体層をクラッド層とするGRIN−SCH
レーザを構成し、多層エピタキシャル膜内の第2の領域
において、第4、第5の半導体層内にイオン注入法を用
いて第1導電型の不純物領域を選択的に形成し、第1か
ら第3の半導体層をコレクタ、第4、第5の半導体層内
に形成された第1導電型の不純物領域をエミッタ、第4
の半導体層内のエミッタとコレクタに挾まれた領域をベ
ースとするヘテロ接合バイポーラトランジスタを構成す
ることを特徴とする光・電子集積回路の製造方法。
(7) On a semi-insulating substrate, a first conductive type wide-gap first semiconductor layer, a first conductive type second semiconductor layer having a sloped bandgap, a first conductive type or a narrow gap layer to which no impurity is added. A multilayer epitaxial film is formed by sequentially stacking a third semiconductor layer of a second conductivity type with a tilted bandgap, a fourth semiconductor layer of a second conductivity type with a wide gap, and an insulating layer. The multilayer epitaxial film is separated into a first region and a second region, and the third semiconductor layer is used as an active layer and the first and fifth semiconductor layers are used as cladding layers in the first region in the multilayer epitaxial film. GRIN-SCH
A laser is configured, and impurity regions of the first conductivity type are selectively formed in the fourth and fifth semiconductor layers in the second region in the multilayer epitaxial film by using an ion implantation method, and The third semiconductor layer is used as a collector, the first conductivity type impurity regions formed in the fourth and fifth semiconductor layers are used as an emitter, and the fourth semiconductor layer is used as an emitter.
1. A method for manufacturing an opto-electronic integrated circuit, comprising forming a heterojunction bipolar transistor based on a region sandwiched between an emitter and a collector in a semiconductor layer.
(8)第1導電型がn型、第2導電型がp型であること
を特徴とする特許請求の範囲第7項記載の光・電子集積
回路の製造方法。
(8) The method for manufacturing an optoelectronic integrated circuit according to claim 7, wherein the first conductivity type is n type and the second conductivity type is p type.
(9)第1、第2、第4、第5の半導体層がAlGaA
s、第3の半導体層がGaAs或いはAlGaAsであ
ることを特徴とする特許請求の範囲第7項記載の光・電
子集積回路の製造方法。
(9) The first, second, fourth, and fifth semiconductor layers are AlGaA
8. The method of manufacturing an opto-electronic integrated circuit according to claim 7, wherein the third semiconductor layer is GaAs or AlGaAs.
(10)第2の半導体層が、第3の半導体層との接続部
分でのAl組成が0、第1の半導体層との接続部分での
Al組成が第1の半導体層のAl組成に等しくなるよう
に、Al組成が順次変化するAlGaAsであり、第4
の半導体層が、第3の半導体層との接続部分でのAl組
成が0、第5の半導体層との接続部分でのAl組成が第
5の半導体層のAl組成に等しくなるように、Al組成
が順次変化するAlGaAsであることを特徴とする特
許請求の範囲第9項記載の光・電子集積回路の製造方法
(10) The second semiconductor layer has an Al composition of 0 at the connection part with the third semiconductor layer, and an Al composition of the second semiconductor layer at the connection part with the first semiconductor layer is equal to the Al composition of the first semiconductor layer. It is AlGaAs whose Al composition changes sequentially, and the fourth
The semiconductor layer is made of Al so that the Al composition at the connection part with the third semiconductor layer is 0 and the Al composition at the connection part with the fifth semiconductor layer is equal to the Al composition of the fifth semiconductor layer. 10. The method of manufacturing an opto-electronic integrated circuit according to claim 9, wherein the material is AlGaAs whose composition changes sequentially.
(11)第1、第2、第4、第5の半導体層がInP、
第3の半導体層がInGaAs或いはInGaAsPで
あることを特徴とする特許請求の範囲第7項記載の光・
電子集積回路の製造方法。
(11) The first, second, fourth, and fifth semiconductor layers are InP,
The optical system according to claim 7, wherein the third semiconductor layer is InGaAs or InGaAsP.
Method of manufacturing electronic integrated circuits.
(12)半絶縁性基板がGaAs或いはInPであるこ
とを特徴とする特許請求の範囲第7項記載の光・電子集
積回路の製造方法。
(12) The method for manufacturing an opto-electronic integrated circuit according to claim 7, wherein the semi-insulating substrate is GaAs or InP.
JP11747986A 1986-05-23 1986-05-23 Optical and electronic integrated circuit and manufacture thereof Pending JPS62274790A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11747986A JPS62274790A (en) 1986-05-23 1986-05-23 Optical and electronic integrated circuit and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11747986A JPS62274790A (en) 1986-05-23 1986-05-23 Optical and electronic integrated circuit and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS62274790A true JPS62274790A (en) 1987-11-28

Family

ID=14712717

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11747986A Pending JPS62274790A (en) 1986-05-23 1986-05-23 Optical and electronic integrated circuit and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS62274790A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6441265A (en) * 1987-08-06 1989-02-13 Mitsubishi Electric Corp Optical integrated element
US5101246A (en) * 1988-12-08 1992-03-31 Ricoh Company, Ltd. Photo-functional device
JP2012514870A (en) * 2009-01-08 2012-06-28 ザ ボード オブ トラスティース オブ ザ ユニバーシティ オブ イリノイ Light emitting and laser semiconductor device and method
WO2014127502A1 (en) * 2013-02-19 2014-08-28 Source Photonics (Chengdu) Co., Ltd. Variable bandgap modulator for modulated laser system
WO2021259356A1 (en) * 2020-06-24 2021-12-30 京东方科技集团股份有限公司 Chip structure and manufacturing method therefor, and display apparatus

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6441265A (en) * 1987-08-06 1989-02-13 Mitsubishi Electric Corp Optical integrated element
US5101246A (en) * 1988-12-08 1992-03-31 Ricoh Company, Ltd. Photo-functional device
JP2012514870A (en) * 2009-01-08 2012-06-28 ザ ボード オブ トラスティース オブ ザ ユニバーシティ オブ イリノイ Light emitting and laser semiconductor device and method
WO2014127502A1 (en) * 2013-02-19 2014-08-28 Source Photonics (Chengdu) Co., Ltd. Variable bandgap modulator for modulated laser system
CN104254951A (en) * 2013-02-19 2014-12-31 索尔思光电(成都)有限公司 Variable bandgap modulator for modulated laser system
WO2021259356A1 (en) * 2020-06-24 2021-12-30 京东方科技集团股份有限公司 Chip structure and manufacturing method therefor, and display apparatus

Similar Documents

Publication Publication Date Title
US4801993A (en) Monolithic semiconductor structure of a heterojunction bipolar transistor and a laser
US6756615B2 (en) Heterojunction bipolar transistor and its manufacturing method
US5822349A (en) Semiconductor device and method of manufacturing the same
US4751195A (en) Method of manufacturing a heterojunction bipolar transistor
JP3368452B2 (en) Compound semiconductor device and method of manufacturing the same
KR100386928B1 (en) Manufacturing a heterobipolar transistor and a laser diode on the same substrate
JP5463760B2 (en) Optical waveguide integrated semiconductor optical device and manufacturing method thereof
JPS63140570A (en) Semiconductor device
KR930007190B1 (en) Compound semiconductor device
US6229150B1 (en) Semiconductor structures using a group III-nitride quaternary material system with reduced phase separation and method of fabrication
JPH05175594A (en) Semiconductor laser device
JPS62274790A (en) Optical and electronic integrated circuit and manufacture thereof
Mochizuki et al. GaInP/GaAs collector-up tunneling-collector heterojunction bipolar transistors (C-up TC-HBTs): Optimization of fabrication process and epitaxial layer structure for high-efficiency high-power amplifiers
JPH0513882A (en) Semiconductor optical element using wide band gap material for p-n current blocking layer
JP2780275B2 (en) Embedded semiconductor laser
JPS61251090A (en) Semiconductor laser and manufacture thereof
JP2001085795A (en) Semiconductor device and semiconductor light-emitting element
JPH0654806B2 (en) Optical / electronic integrated circuit and manufacturing method thereof
JPH04251934A (en) Semiconductor device
JP2527197B2 (en) Optical integrated device
JPH11261106A (en) Semiconductor device
JPH02285682A (en) Semiconductor hetero junction and semiconductor device using it
JPH11121461A (en) Hetero junction bipolar transistor
JPH05175225A (en) Manufacture of hetero junction bipolar transistor
JP3228431B2 (en) Method of manufacturing collector-up structure heterojunction bipolar transistor