JPS62274669A - Gallium arsenide field-effect type semiconductor device - Google Patents

Abstract

PURPOSE:To attenuate the leak current of a substrate, and to contrive suppression of generation of a side-gate effect by a method wherein a field-effect transistor element is completely surrounded by a high resistance insulation damage layer. CONSTITUTION:An insulation damage layer 2 is provided on the position deeper than an active layer 3, and another dielectric damage layer 12 is provided in such a manner that the lateral direction of a transistor element is isolated. Accordingly, the active region of a fieldeffect transistor element is completely isolated on a substrate from other regions. These insulation damage layers 2 and 12 are formed by performing an implantation of proton H<+> ions, for example, the spreading of a depletion layer to an active region by a substrate depletion layer is inhibited, and the leak current of the substrate is attenuated. As a result, the generation of a side-gating effect can be impeded.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Industrial Application] The present invention uses gallium arsenide (GaAs) as a substrate.
The present invention relates to a field effect transistor 1, and in particular to the structure of a female type 1 field effect transistor having a Schottky-type gate capacitor.

[Conventional technology]

Gallium arsenide female field effect transistor (hereinafter referred to as Ga A
s -Mg2- FET) is approximately 107 to 10'
A low concentration active layer is formed on a semi-insulating substrate of about Ωα by epitaxial growth or ion implantation, this is used as a channel region, and the channel width is controlled by the depletion layer of the Schiltsky gate to obtain desired electrical characteristics. What you get is common.

[Problem that the invention seeks to solve]

At this time, the Shitkeygate depletion layer ≠ Kyotejipo -71 (
At the same time, a substrate depletion layer (hereinafter referred to as gate depletion layer) is generally formed as a second depletion layer at the interface between the semi-insulating substrate and the active layer. Therefore, it is easy to imagine that the electrical characteristics of a transistor are greatly influenced by the properties of its substrate depletion layer.When considering the properties of this substrate depletion layer, a particularly important factor is its deep level. ), which cannot be avoided with current manufacturing technology.The existence of this level causes a change in the spread of the depletion layer toward the active layer when the substrate potential is negative, resulting in the formation of a deep level. The higher the density of the points, the stronger the influence (
The depletion layer is also large. Therefore.

The channel width decreases accordingly, and the current flowing between the source and drain decreases. Moreover, this substrate leakage current flows when the substrate itself is relatively resistive.

The resulting voltage drop causes the substrate depletion layer to further expand, and if the nearby source potential is relatively negative, the source.

The drain-to-drain current decreases further. Above is the side.

Gating (8ide Gatirrg) effect L,
Other mistakes of the known S (MES) (MIS)
This phenomenon appears in other forms as well, and is an obstacle in the production of GaAs integrated circuit devices having GaAs-PET as a basic element.

In view of the above circumstances, an object of the present invention is to provide a gallium arsenide field effect semiconductor device that suppresses the generation of base current due to the base depletion layer and reduces the side gating effect. .

[Means for resolving issues]

The gallium arsenide field effect semiconductor device of the present invention is a gallium arsenide field effect semiconductor device.

a gallium arsenide semi-insulating substrate, a field effect transistor formed on the gallium arsenide semi-insulating substrate, and surrounding all of the bottom and side surfaces of the active region of the field effect transistor within the gallium arsenide semi-insulating substrate; In other words, according to the present invention, the interface between the active layer and the substrate where the substrate depletion layer is formed is located at a deep position. An insulating damage layer is formed.

〔Example〕

The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a conventional cross-sectional view showing one embodiment of the present invention. This example shows a case where a GaAs-MES 4hFETKN is formed, and includes a gallium arsenide semi-insulating substrate 1, an active layer 3. Source area 4. Drain region 5° Gate electrodes 6, 9
．． Source Kangyoku 8. It includes a field effect transistor consisting of a drain electrode 10 and horizontal and vertical insulation damage layers 2 and 12. Here, 7 is a surface-retaining film, and 11 is gold (
Au) electrode.

As is clear from FIG. 1, the insulation damage layer 2 is the active layer 3.
The insulation damage layer 12 is provided at a deeper position than the
are provided so as to isolate the transistor elements in the lateral direction. Therefore, the active region of the field effect transistor element is completely isolated within the substrate. These insulation damage layers 2 and 12 are formed, for example, by implanting proton (H+) ions, and prevent the substrate depletion layer from spreading into the active region, reducing substrate leakage current, which has been a problem in the past. The occurrence of the side gating effect can be sufficiently suppressed. The semiconductor device of the present invention can be easily manufactured by the following method.

FIGS. 2(a) to 2(d) are sequential diagrams of one step in manufacturing the semiconductor device of the present invention. First, as shown in FIG. 3(a), proton ions (H+) are implanted into a gallium arsenide (GaAs) substrate 1 to form a horizontal insulation damage layer 2, and then an active layer 3 is formed by, for example, ion implantation. formed by. Then, using a normal manufacturing process, the product shown in FIG.
), the source region 4, train region 5. A field effect transistor consisting of gate electrodes 6 to 9 is formed. Here, 7 is the surface retention*a. Furthermore, if a gold (Au) material is coated using a sputtering method or the like, an opening 13 is formed by a normal photoresist process, and proton (H") t- ions are implanted again, the vertical insulation damage layer 12 is formed. It is formed connected to the horizontal insulation damage layer 2.

FIG. 3(C) shows this state. Here, gold (Au
) By leaving the wiring portion of the material 11 and removing the rest, the field effect semiconductor device of the present invention is completed as shown in FIG. 3(d). Note that some parts of the above description that are less relevant to the invention have been omitted. The above is GaAs 11MES eF
Although ET has been described, the invention can be applied to all device structures in which a substrate depletion layer is formed, including MIS type field effect transistors. In addition, although only proton implantation has been described as a method for causing damage, it is clear that other methods such as RIE (reactive ion etching), ion-milling, and etching methods may also be used. It is.

〔Effect of the invention〕

As explained in detail above, according to the present invention, by surrounding the entire field effect transistor element with a high-resistance insulating damage layer, the substrate leakage current can be reduced and the side gate effect can be significantly suppressed. What are the effects of achieving straw-scale integration of transistors? M.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional structural diagram showing one embodiment of the present invention, and Figure 2 (
a) to (d) are process flow diagrams for manufacturing the present invention. 1...GaAs substrate, 2...-horizontal insulating damage layer, 3...active layer, 4...source region, 5...-drain Area, 6...
- (lower layer) gate electrode, 7... surface ml protective film, 8
...Source electrode, 9... (upper layer) gate electrode, 10...--Drain electrode, 11...
-・fL(Au)' electrode, 12... Vertical insulation damage layer. Agent: Patent Attorney Uchihara -) Japan. /---σaAs half J spicy kal, L, f---
Ohadaffpt=t*Tanushimesho, 3-3 Zankoo layer
4- Swords Tojo Ebisu, Tar-train 4-Kinari, Otsu-m- and “Do-me-ji) Genitsan IEto, 7.
-Table 6 1 burn 2, 8-0-Source electric left 7---
(J: layered Kasumi Oo, 1i---p'b in IIE Gi 45, n-#(Itt)'e year old/2...
-Kenpo J! Damage layer to 'l'eυ.

Claims (1)

[Claims] a gallium arsenide semi-insulating substrate, a field effect transistor formed on the gallium arsenide semi-insulating substrate, and surrounding all of the bottom and side surfaces of the active region of the field effect transistor within the gallium arsenide semi-insulating substrate; a gallium arsenide field effect semiconductor device comprising: an insulating damage layer formed in the manner described above and insulating and isolating the active region in an island shape within a substrate.