JPS62274455A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To considerably improve the throughput by connecting plural microprocessor units, each of which consists of the same kind of microprocessor, an instruction converting circuit, and a conversion control circuit which controls the conversion mode of the instruction converting circuit, to a bus. CONSTITUTION:If trouble occurs in an MPU 7 while the MPU 7 executes the processing of a subroutine A, a trouble signal is sent to a CTL 2 through a trouble signal line 11, and this trouble signal is reported to an MPU 6. When detecting the occurrence of trouble in the MPU 7 by an interrupt, the MPU 6 changes the conversion mode of a CCV 4 to MOD 2 through a bus 8 to perform the interrupt processing, and instruction CALL A in address 200 is fetched at this time if necessary. Instruction CALL A in address 200 read out by the CCV 4 is not converted and is sent to the MPU 6 and is executed. As the result, the processing of the subroutine A starting with address 500 is executed by the MPU 6 to execute the processing of the MPU 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiprocessor system, and particularly to a multiprocessor system in which a plurality of microprocessor units are connected to one bus.

[Conventional technology]

Conventionally, this type of multiprocessor system uses a plurality of different processors to handle a wide range of microcomputer applications. For example, as shown in pages 125 to 130 of ``Intel Japan Material No. 210760Jr 1APX286 Hardware Reference Manual,'' a multiprocessor system is constructed using a host microprocessor and an extended numerical microprocessor for numerical data operations. In this system, a host microprocessor executes individual instruction streams, and an enhanced numerical microprocessor extends the host microprocessor's instruction set and architecture to increase its numerical processing capabilities.

[Problem that the invention seeks to solve]

The conventional multiprocessor system described above requires at least two types of microprocessors. For this reason, during mass production, the burden of inventory management and production management increases, making it impossible to expect mass production effects.

Furthermore, when one microprocessor fails, another microprocessor cannot take its place, which poses a serious problem in terms of reliability.

Furthermore, since the processing function is limited depending on the type of microprocessor used, there is a drawback that there is a limit to the improvement of the processing capacity.

[Means for solving problems]

In a multiprocessor system according to the present invention, in which a plurality of microprocessor units are connected to a bus, each microprocessor unit performs conversion control in which a conversion mode of an instruction conversion circuit is specified by writing from other microprocessors and a specified signal from the outside. a command conversion circuit that converts instructions on the bus according to a conversion mode specified by the conversion control circuit; and a microprocessor that executes instructions from the instruction conversion circuit.

〔Example〕 Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the multiprocessor system of the present invention, in which a main memory device (hereinafter referred to as MEM) 1,
The same type of microprocessor (hereinafter referred to as MPU>6.7)
A command conversion circuit (hereinafter referred to as CCV) 4.5 and a conversion control circuit (hereinafter referred to as CTL) 2. each connected to the MPU 6.7.
3, and these circuits are connected to each other via a bus 8.

CCV4 and CCV5 convert the instructions in MEM1 into other instructions according to the conversion mode specified by CTL2 and CTL3, or transfer them to MPU6.7 without conversion. CTL2 specifies the conversion mode of the CCV 4 by a failure signal sent by the MPU 7 via the failure signal line 11 and by the MPU 7 writing data via the bus 8.

The other CTL3 connects MPU6 via the fault signal line 12.
The conversion mode of the CCV 5 is designated by a failure signal sent by the MPU 6 and data written by the MPU 6 via the bus 8.

In FIG. 1, it is assumed that MPU 6° is the main processor and MPU 7 is the sub-processor.

Next, FIG. 2 is a diagram showing an example of a memory map of the main storage device in FIG. 1.

The initialization program of this multiprocessor system is placed after address θ, and the function instruction (hereinafter FUN) is placed at address 100.
C1), Subroutine call instruction to call subroutine A at address 200 (hereinafter referred to as CALL), 5
The processing program for subroutine A is stored from address 00 onwards. Furthermore, a save area is provided after address 800 to save the status when the MPU 6 of the main processor executes the CALL ^ instruction, and a failure restart processing status save area necessary for restart processing in the event of a processor failure is provided after address 900. ing. MPU
6 normally controls the entire system by accessing memory areas other than the processing program of subroutine A starting at address 500. On the other hand, the subprocessor MPU 7 is in charge of only executing the initialization program from address θ and the processing program of subroutine A from address 500.

FIG. 3 is a diagram showing the instruction conversion status in each mode of the instruction conversion circuit shown in FIG. indicates a processor stop instruction. FUN
Cl is an instruction that performs the same processing as the no-operation instruction NOP (simply fetching the instruction at the next address without performing any processing). Furthermore, after storing the status of the processor in the save area starting from address 800, FUNC2 sets the conversion mode of the conversion control circuits belonging to other processor units to MOD 1 via bus 8, and further sends a start signal to other processors through the start signal line. It means a command to do. CALL ^ is an instruction that saves the return address in the stack area of the memory map (not shown), jumps to subroutine A, and performs the processing of subroutine A.

RET A is an instruction to jump to the return address saved in the stack area and execute the instruction at that address. General instructions are load, store, at, subtract, CALL (except CALL A), RET (
(excluding RET), AND instructions, etc.

Now, in Figures 1 and 2, CTL2 and 3 are initialized at the same time as MPU6.7 by an external reset signal, and the initial conversion mode of CCV4 and 5 is changed to MO in Figure 3.
Specify as DO. CCV4゜5 is this initial conversion mode M
ODO sends the initialization program command from address θ of MEM 1 to the MPU 6.7 without converting it. CCV4.

This initialization program via MPU 5 is executed by MPU 6゜7, and the microprocessor itself and its peripheral circuits (
(not shown) is initialized.

When the processing of MPtJ7 of the sub-microprocessor progresses and the instruction FUNC1 at address 100 is read out, the CCV
5 converts the instruction F'UNC1 into a 5TOP instruction as shown in MODO in FIG. 3, and sends it to the MPU 7.
PU7 executes instruction 5TOP and stops.

On the other hand, the main processor MPU6 is also processing 1
When the instruction FUNC1 at address 00 is read, CCV4
As shown by MODO in FIG. 3, this instruction FUNCI is sent to the MPU 6 of the main processor without being converted. As a result, the MPU 6 fetches the instruction at the next address without performing any processing. Furthermore, the processing of M P' and U 6 progresses to 200
The command CALLA at the address is read. Command CALLA
4 is converted into instruction FUNC2 as shown by MODO in FIG.

MPU6 executes instruction FUNC2. MPU6 records the processor status at that time as 80 of MEM1.
Store it in the save area starting from address 0, then change CTL3 to MODI via bus 8, and at the same time change the MP of the sub-processor that was in the stopped state via start signal line 10.
A start signal is sent at t17. MPU that received the activation signal
7 restarts the process, reads the status of the save area from address 800 onward, sets it in its own processor, and executes the instruction CALL ^ at address 200.

Thereafter, the main processor MPU 6 executes the processing from address 201 onwards, and the sub-processor MPU 7 executes the processing from subroutine A from address 500 onwards in parallel. At this time, the conversion mode of CCV4 is MODo, and the conversion mode of CCV5 is MODl.

When the processing of subroutine A from address 500 onward is progressed by MPU 7 and the command RET at address 600 is transferred to CCV 5, command R is executed as shown in MOD l in FIG.
ET A is converted into an instruction 5TOP and sent to the MPU 7. As a result, the MPU 7 stops.

In this way, the sub-processor can execute a portion of the instruction stream in parallel with the processing of the main processor. The subroutine A executed by the subprocessor may be one that can be processed in parallel with the processing of the main processor, or a method may be used in which the main processor does not execute processing while the subprocessor is processing. It is clear that the latter can also be achieved by entering the main processor into a waiting state while the sub-processor is processing, and then executing the next process after the sub-processor completes processing.

By the way, while MPtJ6 and MPU7 are both operating, that is, while MPU7 is executing subroutine A, MP
When a failure occurs in U7, CT is transmitted through the failure signal line 11.
A failure signal is sent to L2.

Furthermore, this failure signal is notified to the MPU6 by an interrupt (the interrupt signal line from CTL2 to MPtJ6 is not shown). When the MPU6 learns of the failure of the MPU7 by the interrupt, it changes the conversion mode of the CCV4 to MOD2 via the bus 8. and perform interrupt processing. At this time, if necessary, fetch the instruction CALL^ at address 200. The instruction CALL A at address 200 read out to the CCV 4 is sent to the MPU 6 and executed without being converted, as shown in FIG. As a result, the MPU 6 selects subroutine A from address 500 onwards.
This process is executed and can replace the process of the MPU 7.

Next, while MPU6 is operating and MPU7 is stopped, the MPLI
If CTL 7 fails, a failure signal is sent to CTL 2 through failure signal line 11 in the same way as described above.

Further, this failure signal is notified to the MPU 6 by an interrupt. When MPU6 learns of the failure of MPU7 through an interrupt,
The conversion mode of CTL2 is changed to MOD2 via bus 8. Thereafter, as shown in MOD2 of FIG. 3, the MEMI command continues to be sent to the MPU 6 without being converted by the CCV4. When CCV4 is MOD2, instruction C at address 200
When ALL ^ is read, it is transferred to CCV4 and sent to MPU6 without being converted, and the processing program of subroutine A starting from address 500 is executed by MPU6, so it can completely replace the function of MPU7. .

When MPLI6 is in operation and MPU7 is in a stopped state, M
When a failure occurs in the PU 6, a failure signal is sent to the CTL 3 through the failure signal line 12. The CTL3 changes the conversion mode of the CCV5 to MOD2 shown in FIG. 3 and starts the MPU 7 through the start signal line 10. MPU7 is 900
Reads the failure restart processing status save area after the address, sets it in its own processor, and starts failure restart processing. Since the conversion mode of CCV5 is MOD2, all accessed MEM1 instructions are sent to MPU7 and processed without being converted by CCV5. That is, the MPU7 can replace the MPU6.

Above, we described an example of a multiprocessor system constructed by connecting two microprocessor units, each consisting of a microprocessor, an instruction conversion circuit, and a conversion control circuit, to the same bus. It is also easily possible to construct a processor system. In a multiprocessor system in which a plurality of such microprocessor units are connected, a large number of processes can be executed in parallel, so that processing capacity can be significantly improved.

〔Effect of the invention〕

As explained above, the present invention provides processing capacity by connecting to a bus a plurality of microprocessor units each composed of the same type of microprocessor, an instruction conversion circuit, and a conversion control circuit that controls the conversion mode. You can build a multiprocessor system, which greatly improves production management than when you configure a multiprocessor system using several types of microprocessors.

Inventory control is easy and mass production has the effect of increasing the mass production effect. Furthermore, even if one microprocessor fails, the processing of the failed microprocessor can be replaced by another microprocessor, which has the effect of configuring a highly reliable multiprocessor system.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the multiprocessor system of the present invention, FIG. 2 is a diagram showing an example of the memory map of the main storage device in FIG. 1, and FIG. 3 is a diagram showing an example of the instruction conversion circuit of FIG. FIG. 7 is a diagram showing the conversion status of instructions in each mode. 1... Main memory device (MEM), 2.3... Conversion control circuit (CTL), 4.5... Command conversion circuit (CCV)
, 6.7... Microprocessor (MPU>, 8...
・Bus, 9.10...Start signal line, 11.12...
Failure signal, 21st side

Claims (1)

[Claims] In a multiprocessor system in which a plurality of microprocessor units are connected to a bus, each microprocessor unit has a conversion control circuit that specifies a conversion mode of an instruction conversion circuit based on writes from other microprocessors and external designation signals. , an instruction conversion circuit that converts instructions on the bus according to a designation from the conversion control circuit, and a microprocessor that executes the instructions from the instruction conversion circuit.