JPS62270100A - Sample/hold circuit - Google Patents

Abstract

PURPOSE:To obtain a sample/hold circuit with a wide dynamic range and a high speed of action by providing a voltage holding circuit which does not saturate a switching element to execute the changing-over control of a sampling action and a holding action. CONSTITUTION:A voltage holding circuit 9 is composed of a resistance 10 connected serially between a power source VCC and a grand terminal, a Zener diode ZD and an NPN type transistor TrQ5. During the holding period when a control signal inversion phi is an H level and phi is an L level, the input signal V1 of a low voltage level is supplied, the TrQ5 comes to be turned on, then, the current Ia conducted at a constant electric current source circuit 4 through a resistance 2 and a switching TrQ2 comes to be the total current from the resistance 2 and the TrQ5, and is conducted through the TrQ2 to the constant current source circuit 4. Thus, even when an input signal V1 comes to be further a low voltage level, the TrQ2 is hardly saturated by the current supplied from the TrQ5.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a sample and hold circuit with improved dynamic range.

(Conventional Example) A conventional sample-and-hold circuit is shown in FIG. First, to explain the configuration, 91021 mouth 8゜Q, BAN
It is a PN type transistor, and the base terminal of transistor Q4 is signal input terminal 1, and its collector terminal is @@V
cc, and its emifuku terminal is connected to the base terminal of the transistor Q via a resistor 2, respectively. The collector terminal of transistor Q3 is connected to the power supply Vcc, and its emitter terminal is connected to the collector terminal of transistor Q+ and the
The transistors Q are connected to the input terminals of the nofa amplifier 3, respectively.

A hold capacitor C is connected between the emitter terminal and the ground terminal.

The transistors Q+ and Q* are both connected to the constant current source circuit 4 at their emitter terminals, and the collector terminals are connected in parallel between the base and emitter terminals of the transistor U, and are connected to the base terminal. The on/off operation is controlled by φ under the control signal from the signal input terminal 5.6, thereby forming a switching circuit that switches the current flowing into the constant current source circuit 4.

The constant current source circuit 7 is provided to set the bias current of the transistor Q4, and the voltage across the buffer amplifier 3 and the hold capacitor C (hereinafter referred to as hold voltage) L+
o is impedance-converted and output to the output terminal 8.

Next, the operation of the sample-and-hold circuit having such a configuration will be explained.

Control signals φ, φ supplied to control signal input terminals 5 and 6
is used to set the sample period and hold period, and as shown in Figure 3, they are the same! 134 is a rectangular wave signal that does not have the same level, and as shown in the following table, the control signal? When the level is "J" and the tlj control signal φ is "H" level, the sampler Ts and the control signal i are "
The hold period T, l is set to the time when the control signal φ is at the "H" level and the control signal φ is at the "L" level.

That is, during the sampling period Ts, transistor Q2 is turned off by No. 8 T, and transistor Q is turned on by No. 3 φG, which is at H level, so transistor Q3 is also turned on. , therefore, when a human input signal v1 is applied to the signal input terminal 1, the input signal v1 is applied to both ends of the hold capacitor C, and the input signal v1 is applied to the respective bases of the transistors Q3+ [Ia].
By subtracting the emitter voltage 'Jbe3+Vbea, a voltage Vl -Vbei-Vbea is generated.

On the other hand, the hold period? , conversely, the transistor Q2 is on and the transistor Q1 is off, so the current flowing into the constant current diagram -4 flows through the resistor 2 and the transistor Q.
t, and due to the voltage drop generated across the resistor 2 at this time, the potential at the connection point Pc in the figure drops, turning off the transistor 01.

In this way, by turning off the transistors Q1 and Q simultaneously, the voltage generated in the hold capacitor C during the sampling period Ts remains at a constant hold voltage V without being charged or discharged. . An output voltage equal to this hold voltage vtto is output to the output terminal 8.

Here, during the hold period T, the input signal is V.

It is necessary that the hold voltage v8° does not change even if the voltage changes, and in order to satisfy this condition, the resistance value Rs of the resistor 2 and the setting of the constant current source circuit 4'it flow! Set a to a predetermined value, and during this period T, transistors n,
This ensures that there is no forward bias.

That is, if the voltage between the base and emitter for turning on the transistor (h is Vbe1, and the potential of the connection point Pc is 'jpc, the voltage VPCVPll between the connection points Pc and Pn is always (VPC - VFM) - (νpc - VMI+)
The condition is that <Vbe3- .= +t+. In particular, as is clear from the above equation +1), when the -hold voltage WHO is at a low voltage level, the input signal V is Vcc.
If the amplitude of the electric current a is close to that of the voltage a, then if the ta continuation point Pc
If the potential Vpc also rises accordingly, the transistor Q will turn on, but in order to prevent this from happening, the resistor 2 and the constant Each value Rs of the current source circuit 4, [a is the following formula (2)
The relationship is set as follows.

Vsig= lltw*x VIMII+...
・(2) (Rs X Ia) > Vbe, + Vsig(
(Problems to be Solved by the Invention) However, as is well known, in such conventional sample-and-hold circuits, when the transistor is operated in the saturation region, the operation becomes slow and problems such as oscillation occur. Since this is likely to occur, it is necessary to operate in a non-saturated region. However, in the circuit of FIG. 2, the hold period T. In the middle, the base terminal of transistor 2 is set to “H” by control 2Tj signal φ.
When the potential at the connection point Pc, that is, the collector potential of the transistor Q, falls below the voltage level of the signal f while a voltage of this level is applied, the transistor Q2 becomes saturated.
, a problem arises in that the off operation due to the "L" level of the control signal 1 is no longer performed at high speed when the next sampling period T3 begins. Such problems can be solved during the hold period TM.
This occurs when the amplitude of the input signal ν1 drops to a low voltage level. In order not to saturate the transistor Qt, the lowest voltage v1□8 of the input signal v1 must be set to “H” of the control signal 1.
"Level voltage is VH-1" If the forward bias voltage (voltage between base and emitter) of transistor Q is represented by Vbe*, it must be equal to or higher than the voltage shown on the right side of the following equation (3).

VIMIN≧Vll + R3X Ia + Vbe4
=-...f31 In this way, conventionally, the lower limit of the input signal V+ that can be inputted is limited by the above formula (3),
It was not possible to process large amplitude input signals at high speed.

(Means for Solving the Problems) The present invention has been made in view of the above problems, and an object of the present invention is to provide a sample-and-hold circuit with a wide dynamic range.

To achieve this purpose, a resistor to which an input signal is supplied to one input terminal, a power amplification element such as a transistor whose input terminal is connected to the output terminal of the resistor and performs power amplification, and a power amplification element such as a transistor that performs power amplification are used. a capacitor' connected to the output terminal; a first switching element such as a switching transistor, to which the output terminal of the power amplification element is connected an input terminal, for example, the collector terminal of the transistor, and an output terminal, for example, the emitter terminal of the transistor; , a second switching element such as a transistor whose input terminal, for example, a collector terminal is connected to the output terminal of the resistor, and whose output terminal, for example, an emitter terminal, is commonly connected to the output terminal of the first switching element; 1st. In the sample-and-hold circuit comprising a switching circuit that causes the opening and closing operations of the second switching element to be performed mutually exclusive, when the second switching element is closed, the voltage at the input terminal reaches the saturation voltage of the second switching element. The technical point is that a voltage holding circuit is provided which detects that the voltage is substantially equal and maintains a predetermined voltage between the input and output terminals of the second switching element, and prevents the second switching element from operating in the saturation region. do.

(Embodiment) FIG. 1 is a circuit diagram showing an embodiment of a sample-and-hold circuit according to the present invention, and the same or equivalent parts as in FIG. 2 are given the same reference numerals.

First, the configuration will be explained based on the differences from the circuit shown in FIG. 2.

A voltage holding circuit 9 is provided between a connection point Pc connecting the output terminal of the resistor 2 and the base terminal of the transistor Q and a power supply Vcc. The voltage holding circuit 9 includes a resistor 10 and a Zener diode ZD connected in series between a power supply Vcc and a ground terminal, and a resistor 10 and a Zener diode ZD connected in series between the power supply Vcc and a ground terminal.
The base terminal is connected to the connection point P6 of
It includes an NPN transistor Q whose collector terminal is connected to Vcc and whose emitter terminal is connected to the connection point Pc.

The Zener diode ZO generates a constant voltage V at the connection point P by the 'F1 current supplied through the resistor 10,
This voltage V is the Heath-emitter voltage Vb required to turn on the transistor Q, as shown in the following equation (4).
The voltage is set to be approximately equal to the sum of e5 and the voltage vH at the "H" level of the control signal 7 applied to the switching transistor Qt.

'd@ ~VH+Vbe5=・-141 For example, in this embodiment, the control signal 1. The voltage Vi at the “I(” level of ψ is 0.6v, and the above base-emitter voltage Vbe
5 to about 0. The voltage V of the TV is set to approximately 1.3V.

Next, the operation of the sample and hold circuit having such a configuration will be explained.

During the sampling period when the control signal 7 is at the "L" level and the control signal φ is at the "H" level, the transistors Q3.
[1O is turned on and the transistor Q is turned off, so a voltage approximately equal to the voltage of the input signal v1 supplied to the input terminal l is generated at one end P8 of the hold capacitor C.

Next, during the hold period in which the control signal 1 is at the "H° level" and the control signal φ is at the "L" level, the transistor low,
is off, the transistor h is turned on, and the voltage drop across the resistor 2 caused by the current 1a flowing into the constant current source circuit 4 via the resistor 2 lowers the potential at the connection point Pc, and the transistor Q is also turned off.

Therefore, the charge accumulated in the hold capacitor C is held constant without being discharged or charged, and the voltage at the connection point P becomes a constant hold voltage VIID during the hold period T.

Furthermore, the resistance value Rs of the resistor 2 and the setting current of the constant current source circuit 4! a is set such that the condition of equation (2) is satisfied and the transistor Q is not turned on during the hold period T9.

During this hold period T, the input signal ν at a low voltage level
, is supplied, and accordingly, when the voltage Vpc at the connection point Pc is approximately equal to the base terminal voltage of the switching transistor Q (the "H" level of the control signal 1, that is, V), the base-emitter of the transistor Q becomes sequential. Becomes a bias,
Transistor OS turns on.

As a result, when the voltage Vpc at the connection point Pc is equal to or higher than the voltage V, the current 1a that flows into the constant current source circuit 4 only through the resistor 2 and the switching transistor Qt is reduced to the sum of the current from the resistor 2 and the transistor Qt. The current flows through the switching transistor 0□ to the constant current source circuit 4.

Therefore, even if the input signal v1 is further reduced to a lower voltage level, the voltage at the connection point Pc will not fall below the voltage V due to the current supplied by the transistor US, and the switching transistor Q2 will not be saturated.

Next, it will be explained that the dynamic range is expanded by providing the voltage holding circuit 9.

First, as mentioned above, during the hold period T,
Connection point Pc has voltage V. Therefore, in order for the transistor Q to be always kept off during this hold period TM, the hold voltage V must be increased.

is required to be equal to or higher than the voltage V. Therefore, according to this condition, the minimum voltage of the hold voltage VIID stored in the hold capacitor C is V, and in other words for the human input signal v1, the minimum voltage VININ of the input signal V is expressed by the following equation (5). .

VININ ≧Vbea + Vbe2 + VH・=
-(51 Furthermore, in the above equation (5), since the base current flowing through the transistor 03 during the sampling period ↑S is extremely small, the resistance 2 during this sampling period Ts
This voltage drop is omitted because it can be ignored.

Here, when comparing the lowest voltage level of the input signal by the conventional sample-and-hold circuit with the above formula (5), the conventional lowest voltage is Vat + as shown in the above formula +31.
Rs X Ia + Vben, and in this example L + Vbe, + Vben. However, since the voltage Rs +
Since Vbe3-(71), this embodiment can make it lower than the lowest voltage of the conventional input signal V, and as a result, the dynamic range can be expanded.

As explained above, according to this embodiment, the saturation operation of the switching transistor Q is eliminated and the dynamic range is expanded, so that even large amplitude input signals can be sampled and held at high speed.

In this embodiment, a resistor 10 and a Zener diode Z are used as the reference power supply provided in the voltage holding circuit 9 shown in FIG.
Although D is used, the Zener diode ZD is not limited to this.
Instead, a plurality of diodes connected in the forward direction may be used, or a battery power source or the like may be used.

Further, although this embodiment is concerned with providing a sample-and-hold circuit using NPN type transistors, it is also possible to use PNP type transistors or other types of transistors, such as MOS type transistors.

(Effects of the Invention) As explained above, according to the sample-and-hold circuit of the present invention, the switching element that controls switching between the sampling operation and the hold operation is held at a predetermined bias voltage before being saturated, and is forced into saturation. A voltage holding circuit is provided to prevent the switching element from becoming saturated, and the switch notching element is always operated in the non-saturation region, so the switching operation becomes faster, and since the saturation of the switching element is removed, the input signal The maximum amplitude can be increased. Therefore, it is possible to provide a sample and hold circuit that has a large dynamic range and can operate at high speed.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of a sample-and-hold circuit according to the present invention, FIG. 2 is a circuit diagram showing an example of a conventional sample-and-hold circuit, and FIG. 3 is a control diagram used in the circuit of FIG. 2. It is a waveform diagram of a signal. 1; Signal input terminal 2.10i Resistor 3; Buffer amplifier 4.7; Constant current source circuit 5.6; Control signal input terminal 8; Output terminal 9; Voltage holding circuit o, , Q, i Switching transistor Q3. Q...
0%; Transistors Pc, P, tPm; Connection point C; Hold capacitor ZD, Zener diode 12 Figure 3

Claims (1)

[Claims] A resistor to which an input signal is supplied to one input terminal, a power amplification element whose input terminal is connected to the output terminal of the resistor and performs power amplification, and a power amplification element connected to the output terminal of the power amplification element. a first switching element whose input terminal is connected to the output terminal of the power amplification element and whose output terminal is connected to the constant current source circuit; and a first switching element whose input terminal is connected to the output terminal of the resistor and whose output terminal is connected to the constant current source circuit; A sample device comprising: a second switching element whose output terminal is commonly connected to the output terminal of the first switching element; and a switching circuit that causes the first and second switching elements to perform opening/closing operations mutually exclusive. In the hold circuit, when the second switching element is closed, it is detected that the voltage at the input terminal is approximately equal to the saturation voltage of the second switching element, and the voltage between the input and output terminals of the second switching element is maintained at a predetermined voltage. A sample/hold circuit characterized in that it is equipped with a voltage holding circuit.