JPS62269532A - Data generating circuit - Google Patents

Abstract

PURPOSE:To detect a phase shift from the optimum timing of a recovered clock signal by detecting the timing where a clock pattern crosses a prescribed reference level and integrating output data. CONSTITUTION:A clock pattern for phase correction having a prescribed period is prepared as a part of input signals fed to an input terminal 20. A zero cross timing detection signal (d) outputted from a synchronization detecting circuit 27 is fed to a phase error detection circuit 28, where it is converted into a voltage signal by a D/A converter circuit 29 and the signal is fed to a voltage- controlled variable phase shifter 25. Thus, the feedback loop is formed during the clock pattern period so as to form the discrimination result of the circuit 28 to be 0 and phase control is applied so that an inverted clock signal 9b is fed to an A/D conversion circuit 22 the timing optimum to the data detection.

Description

[Detailed Description of the Invention] εObject of the Invention (Industrial Application Field) The present invention provides a data generation circuit that detects data by regenerating a sampling clock signal from a transmission signal in a digital data transmission system. Regarding.

(Prior Art) As is well known, in a digital data transmission system, a transmitted signal is received, a sampling clock signal is regenerated from this input signal, and data is detected based on the clock signal. Data generation systems based on the above are widely mentioned.

FIGS. M5 to FIG. 7 each show such conventional data generation circuits. First, the circuit shown in FIG.
The clock component is extracted through the two-wave rectifier circuit 13 and the sampling clock signal is reproduced through the narrow-band bandpass filter 14. This clock signal is then supplied to a data detection circuit 16 via a phase adjustment circuit 15, which will be described later, to be used for data generation, and digital data is output to an output terminal 17.

In this case, since the phase relationship between the input signal and the clock signal is not specified at all when detecting data, the phase adjustment circuit 15 manually adjusts the clock signal so that data detection can be performed at an appropriate timing. However, the problem is that the phase adjustment work is complicated. Furthermore, the narrowband bandpass filter 14 has a problem in that its center frequency tends to fluctuate, and as a result, the phase of the clock signal also tends to fluctuate, making it difficult to detect data at optimal timing. .

Next, what is shown in FIG. 6 is the bandpass filter 1.
4, a phase comparator 18a, a DC amplifier 18b, a low-pass filter 18C, and a voltage controlled oscillator (hereinafter referred to as VC○
A clock signal is regenerated using a phase-locked loop circuit 18 consisting of 18d (18d).

However, in this case as well, the manual phase adjustment work is troublesome, and the PLL circuit 1
DC (direct current) drift of the DC amplifier 18b in 8, V
A frequency drift of the CO 18d occurs, which causes the phase of the clock signal to fluctuate, which again poses a problem in that it becomes difficult to detect data at optimal timing.

Furthermore, the one shown in FIG. By feeding back to the phase comparator 18a via the differentiating circuit 18e, the phase of the clock signal is automatically adjusted so that data can be detected at optimal timing.

However, even such a data generation circuit has a problem in that the phase of the clock signal fluctuates due to deviations in the delay circuit 19 and phase offsets and fluctuations in the PLL circuit 18.

(Problems to be Solved by the Invention) As described above, in the conventional data generation circuit, it is difficult to perform phase adjustment work, and the DC current of the PLL circuit 18 due to fluctuations in the center frequency of the bandpass filter 14 and temperature changes. Occurrence of DC drift of amplifier 18b and frequency drift of VCO 18d, as well as deviation of delay circuit 19 and PLL
Due to phase offsets and fluctuations in the circuit 18, stationary phase errors are likely to occur in the clock signal, which poses the problem of not being able to perform data detection at the optimal timing, and increasing the bit error rate. It is something that exists.

Therefore, the present invention was made in consideration of the above circumstances, and it automatically adjusts the phase of the sampling clock signal reproduced from the input signal to the best state for data detection, and detects data at the optimal timing. The purpose of the present invention is to provide an extremely good data generation circuit that can perform the following steps.

[Structure 1 of the Invention (Means for Solving Problems) That is, the data generation circuit according to the present invention has the following features from the output of the data detection means that performs data detection based on a clock signal reproduced from an input signal. The clock pattern period for phase correction prepared in the input signal is detected and an inverted signal of the tarok signal is supplied to the data detection means, and the timing at which the clock pattern crosses a predetermined reference level is detected from the output of the data detection means. The output data of the data detection means is detected and integrated, and the phase of the inverted signal of the clock signal supplied to the data detection means is controlled according to the output.

(Function) According to the above configuration, the timing at which the clock pattern crosses a predetermined reference level from the output of the data detection means is detected, and the output data of the data detection means at the time of detection is integrated. , a phase shift of the reproduced clock signal from the appropriate timing is detected. Then, a feedback loop is configured to adjust the phase of the inverted signal of the clock signal supplied to the data detection means in accordance with the integral output so that the phase of the inverted signal of the clock signal supplied to the data detection means is adjusted to the optimum timing. The phase can be automatically adjusted to the best condition for data detection, and data detection can be performed at the optimal timing.

(Embodiment) Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In FIG. 1, 20 is an input terminal to which a transmission signal is supplied. The signal is waveform-shaped by a low-pass filter 21 so that the eye aperture ratio is maximized, and then passed through an A/V for data detection.
D (analog/digital) conversion circuit 22.

Further, the output signal from the low-pass filter 21 is supplied to a clock regeneration circuit 23, and a clock signal for sampling is regenerated. This clock regeneration circuit 23 uses a well-known circuit as shown in FIGS. 5 and 6, for example. It generates an inverted clock signal S which is an inversion of the clock signal @a.

Therefore, the phase of the clock signal output from the clock reproducing circuit 23 has no defined phase relationship with the input signal, and is likely to fluctuate.

Then, the clock signal regenerated by the clock regeneration circuit 23 is transmitted to a selector 24 and a voltage-controlled variable phase shifter 2, which will be described later.
5, the signal is supplied to the A/D conversion circuit 21 for data generation, and digital data is outputted to the output terminal 26.

Here, a phase correction clock pattern (for example, a pattern of 1.0, 1.O, . . . ) having a constant period is prepared as part of the input signal supplied to the input terminal 20. ing. Then, among the outputs of the Δ/D conversion circuit 21, the above-mentioned 0 vine pattern component is detected by the synchronization detection circuit 2.
7.

This synchronization detection circuit 27 generates a clock pattern gate pulse C while detecting a clock pattern component, and also detects zero cross timing of the clock pattern to generate a zero cross timing detection signal d.

Further, the selector 24 is connected to the synchronization detection circuit 27.
During the period when the clock pattern gate pulse C is generated, it operates to guide the inverted clock signal S output from the clock regeneration circuit 23 to the voltage controlled variable phase shifter 25, and during the period when the clock pattern gate pulse C is not generated. , operates to guide the non-inverted clock signal a output from the clock regeneration circuit 23 to the voltage controlled variable phase shifter 25.

Therefore, during the period when the clock pattern gate pulse C is generated from the synchronization detection circuit 27, the inverted lock signal output from the clock regeneration circuit 23 is transmitted to the A/D conversion circuit via the voltage controlled variable phase shifter 25. 22 for data detection.

Further, the zero-crossing timing detection signal d output from the synchronization detection circuit 27 is supplied to a phase error detection circuit 28. This phase error detection circuit 28 is a synchronization detection circuit 2.
7 to determine whether the output signal of the A/D conversion circuit 22 is positive, 0, or negative at the time when the zero-crossing timing detection signal @d is generated, and calculate each determination result and its magnitude. D/A digital data corresponding to
It outputs to two (digital/analog) conversion circuits.

Here, if the determination result of the phase error detection circuit 28 is positive, it means that the rise of the inverted clock signal S is advanced with respect to the zero cross timing of the clock pattern, as shown in FIG. 2(a). (1 in time), which means that the phase of the inverted clock signal S is selected relative to the phase of the output signal of the A/D conversion circuit 22. In addition,
T1 in FIG. 2(a) indicates a phase correction turn.

Furthermore, the fact that the determination result of the phase error detection circuit 28 is 0 means that the zero-crossing timing of the clock pattern and the rising edge of the inverted clock signal S match, as shown in FIG. 2(b). In other words, the phase of the inverted clock signal S matches the phase of the output signal of the A/D conversion circuit 22, indicating that it is the most favorable timing.

Furthermore, the fact that the determination result of the phase error detection circuit 28 is negative means that the rise of the 1-inverted clock signal S is delayed with respect to the zero-crossing timing of the clock pattern, as shown in FIG. 2(C). t2), that is, the phase of the inverted clock signal S lags behind the phase of the output signal of the A/D conversion circuit 22. In addition,
T2 in FIG. 2(C) indicates the correction range for one phase.

The digital data output from the phase error detection circuit 28 is converted into a voltage signal by the D/A conversion circuit 29 and supplied to the voltage-controlled variable phase shifter 25. This voltage control variable phase shifter 25 controls the phase of the clock signal selected by the selector 24 according to the voltage signal level output from the D/A conversion circuit 29, and outputs the clock signal to the A/D conversion circuit 22. This is what is output.

Therefore, during the clock pattern period, a feedback loop is formed so that the determination result of the phase error detection circuit 28 becomes O, and one inverted clock signal is supplied to the A/D conversion circuit 22 at the optimal timing for data detection. The phase is controlled as follows.

Furthermore, when the clock pattern period ends, the synchronization detection circuit 27 no longer generates the clock pattern gate pulse C, so the selector 24 transfers the non-inverted clock signal a output from the clock regeneration circuit 23 to the voltage-controlled variable phase shifter 25. Data detection is performed using this non-inverted clock signal a. In this case, the voltage control variable phase shifter 25 is held in the control state immediately before the end of the clock pattern period.
Phase at the perfect timing for data detection! The non-inverted clock signal a, which has been inverted by 11tll, is supplied to the A/D conversion circuit 22.

In other words, in periods other than the above clock pattern period,
As shown in FIG. 3, since data detection is performed based on a non-inverted clock signal whose phase is controlled at an optimal timing, data detection can be performed when the eye opening of the eye pattern is at its maximum. Note that T3 in FIG. 3 indicates a symbol period.

Therefore, according to the configuration of the above embodiment, a clock pattern is prepared as part of the input signal, and the polarity and magnitude of the data detection output at the zero-crossing point of this clock pattern are determined. Since the phase of the inverted clock signal supplied to the A/D conversion circuit is controlled so that the result is 0, data detection is possible even if a steady phase error occurs in the clock signal output from the clock regeneration circuit 23. The phase of the clock signal can be controlled at the optimal timing, and good data generation with a low bit error rate can be performed.

FIG. 4 shows a modification of the above embodiment, in which the regeneration circuit 23 and the voltage υ controlled variable phase shifter 25 are connected to the same P
The LL circuit 30 is also used to simplify the configuration.

That is, a differentiating circuit 30a and a double-wave rectifier circuit 30b.

The phase comparator 30C1, the DC amplifier 30d, the low-pass filter 30e, and the VCO 30f have the same configuration as the clock recovery section shown in FIG. Yes, vC030r
The control input voltage is superimposed on the control input voltage.

This is equivalent to detuning the free-running oscillation frequency of V C030f, and a steady phase error occurs in the PLL circuit 30. As a result, the phase of the clock signal obtained from the PLL circuit 30 changes depending on the output voltage of the D/A conversion circuit 29, and as in the case of the above embodiment, the clock signal has the optimum phase for data detection. This will allow you to get a signal.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be implemented with various modifications without departing from the gist thereof.

[Effects of the Invention] Therefore, as detailed above, according to the present invention, the phase of the sampling clock signal reproduced from the input signal is automatically adjusted to the best state for data detection,
It is possible to provide an extremely good data generation circuit that can perform data detection at optimal timing.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a data generation circuit according to the present invention, FIGS. 2 and 3 are waveform diagrams for explaining the operation of the same embodiment, and FIG. 4 is a block diagram showing an embodiment of the data generation circuit according to the present invention. A block configuration diagram showing a modification of the example, and FIGS. 5 to 7 are block configuration diagrams showing conventional data generation circuits, respectively. 11... Input terminal, 12... Differential circuit, 13...
double-wave rectifier circuit, 14... bandpass filter, 15.
... Phase adjustment circuit, 16... Data detection circuit, 17.
...Output terminal, 18...PLL circuit, 19...Delay circuit, 20...Input terminal, 21...Low pass filter, 22...A/D conversion circuit, 23...Clock regeneration Circuit, 24...Selector, 25...Normal pressure tilt
) it variable phase shifter, 26... output terminal, 27... synchronization detection circuit, 28... phase error detection circuit, 29...
D/A conversion circuit, 30...PLL circuit. Applicant's agent Patent attorney Takehiko Suzue (a) (b) (C) Figure 2

Claims (1)

[Claims] A data generation circuit comprising: a clock reproducing means for reproducing a clock signal for data detection from an input signal; and a data detecting means for detecting data from the input signal based on the clock signal obtained by the clock reproducing means. , a first detection means for detecting a clock pattern period for phase correction prepared in the input signal from the output of the data detection means; and a first detection means for detecting a period of a clock pattern for phase correction prepared in the input signal from the output of the data detection means; an inverted clock supply means for supplying an inverted signal to the data detection means; a second detection means for detecting the timing at which the clock pattern crosses a predetermined reference level from the output of the data detection means; phase error detection means for integrating output data from the data detection means in a detection state of the means; and a clock signal supplied to the data detection means by the inverted clock supply means in accordance with the output of the phase error detection means. 1. A data generation circuit comprising: phase control means for controlling the phase of an inverted signal.