JPS6226948A - Method and equipment for transmitting and receiving retransmission data - Google Patents

Method and equipment for transmitting and receiving retransmission data

Info

Publication number
JPS6226948A
JPS6226948A JP60165671A JP16567185A JPS6226948A JP S6226948 A JPS6226948 A JP S6226948A JP 60165671 A JP60165671 A JP 60165671A JP 16567185 A JP16567185 A JP 16567185A JP S6226948 A JPS6226948 A JP S6226948A
Authority
JP
Japan
Prior art keywords
data
retransmission
receiving
memory
transmitting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60165671A
Other languages
Japanese (ja)
Other versions
JPH0410261B2 (en
Inventor
Kiichi Matsuda
松田 喜一
Takashi Ito
隆 伊藤
Yoshiji Nishizawa
西沢 美次
Yuji Takenaka
裕二 竹中
Toshitaka Tsuda
俊隆 津田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60165671A priority Critical patent/JPS6226948A/en
Publication of JPS6226948A publication Critical patent/JPS6226948A/en
Publication of JPH0410261B2 publication Critical patent/JPH0410261B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE:To reduce the time from error detection to the arrival of a retransmission data to the reception side by sending a retransmission data after buffer memories of the transmission side and the reception side are cleared when an error is detected in the reception data. CONSTITUTION:When an error detection circuit ED detects an error in the reception data, a read inhibition signal (INH) is given to a reception side control circuit RC, the circuit RC turns off the 4th switch SW4 to inhibit data read from reception side buffer memories BM4-BM6 to a data reception section DR. When the circuit RC receives the read inhibition signal (INH) from the error detection circuit ED, the content of the reception side buffer memories BM4-BM6 is cleared. When a transmission side control circuit SC receives an initializing instruction signal (INC 2), after all transmission side buffer memories BM1-BM3 are cleared immediately, the 1st switch SW1 is controlled so as to write the retransmission data from the initializing circuit INI to, e.g., the transmission side buffer memory BM1. A transmission side control circuit SC controls the 2nd switch SW2 to write the retransmission data in the memory BM1, then the data is sent immediately and sent to a transmission line L.

Description

【発明の詳細な説明】 〔概 要〕 う−一夕送受信システ1、においで、受信側で受信デー
タのエラーを検出すると、受信側バッファメモリの読出
しを禁止すると共に受信側バッファメモリの内容をクリ
アし、且つ、送信側バッファメモリをクリアして再送デ
ータを書込み、受信側で11データを受信側バッファメ
モ1月、二格納後、涜出し禁11を解除することにより
再生データ中受信側への到達時間の短縮を図った再送デ
ータ送受倍力ンノ、。
[Detailed Description of the Invention] [Summary] In the U-Overnight Transmission/Reception System 1, when an error in received data is detected on the receiving side, reading of the receiving side buffer memory is prohibited and the contents of the receiving side buffer memory are Clear the transmitting side buffer memory and write the retransmitted data, and after storing the 11 data in the receiving side buffer memo, cancel the prohibition of 11 and send the reproduced data to the receiving side. The retransmission data transmission and reception system is designed to reduce the arrival time of data.

〔産業上の利用分野〕[Industrial application field]

本発明はデータ送受信シスう−J、における再送デ−タ
送受信方法及び装置t、二係ν)、特a、=画像フーー
タの伝送エラーに対応して送出する再送データの受信側
−1の到達時間の短縮を図−っだハノソlメモリ制御ノ
J一式に関する。
The present invention provides a retransmission data transmission/reception method and apparatus in a data transmission/reception system (t, two coefficients ν), special a. This article relates to a complete memory control system designed to save time.

〔従来の技術) 一般に、画像データ等の高速データの送受信は、所定1
ド位、例えC、トノl/−1、栄位に行われる。このた
めに、所定甲イ17のデータを格納するバッファメモリ
が送信側と受信側にノ(に設+)られている。データは
i[tl常、送信側から+;I: D 11 CM等の
差分データを符号化し2て受信側に送られる。受(18
側はごの差分データをト記所定111位で受は取り、既
に受信済みのデータと合成1.て差分データをもとのデ
ータに再〕1−Jる。
[Prior art] Generally, high-speed data such as image data is transmitted and received at a predetermined rate.
It is done in the do position, e.g. C, tono l/-1, and the honor rank. For this purpose, buffer memories for storing predetermined data 17 are provided on the transmitting side and the receiving side. Data is usually sent from the transmitting side to the receiving side by encoding differential data such as +;I: D 11 CM. Uke (18
The side receives the difference data at the specified 111th position and combines it with the already received data.1. 1-J to convert the difference data back to the original data.

この上・うに、受信側に受は取で一層するデータ(11
差分データll′ので、受信データに1ビットでも伝送
路りで生した誤りがあるとその後の再拝データにはエラ
ーに差分が加算されて再生データ中のエラーが次第に伝
播し7てしまう。
In addition, the receiving side receives more data (11
Since the data is differential data 11', if there is even a single bit error in the transmission path in the received data, the difference will be added to the error in subsequent repeat data, and the error in the reproduced data will gradually propagate.

これをnjj <ために、受信データ中にエラーを検出
−4ると、受fM部から送信部にデータ再送指示をりえ
、送信部は、これを受しJて前の画面によらないilし
、−いデータを送信側バッファメモリを介して再送する
ようにしている。
If an error is detected in the received data, the receiving fM section sends a data retransmission instruction to the transmitting section, and the transmitting section receives this and does not use the previous screen. , - data is retransmitted via the sending buffer memory.

往来のデータ送受信方式においては、データ再送指示に
応t7て正しいデータを送信側バッファメモリに書込む
1易合、通常の送信データと同様にして謁込んでいた。
In the conventional data transmission/reception system, when correct data is written into the transmitting side buffer memory at t7 in response to a data retransmission instruction, the data is received in the same way as normal transmission data.

すなわち、送信側バッファメモリに送信データを書込み
中、あるいは送信側バッファメモリから送信データを読
出し中は、再送データの書込め日持機し−(おり、1−
記送信データの書込みあるいIl読出しが終了後にはし
めて再送データを送信側バッファメモリに書込んでいた
。そして受信側ではデータ再送指示の送出から再送デー
タ中に含まれる再送指示データを検出する迄の間に受信
されたデータの読出しを禁止し、再送指示データ検出後
に再びデータを受信し解読して再生していた。
In other words, while writing transmission data to the transmission side buffer memory or reading transmission data from the transmission side buffer memory, the retransmission data write date is set.
After the writing or reading of the transmitted data is completed, the retransmitted data is written to the transmitting side buffer memory. Then, on the receiving side, reading of the data received from the sending of the data retransmission instruction until the retransmission instruction data included in the retransmission data is detected is prohibited, and after the retransmission instruction data is detected, the data is received again, decoded, and reproduced. Was.

〔発明が解決すべき問題点〕[Problems to be solved by the invention]

前述の如く、従来は、送信側ハ・ノファメ七11・\の
再送データの書込みは、受信側からの1Til送指示が
あってから、書込み中又は読出し中の通常の送信データ
の書込め又は読出しの終了の後にはしめて行われるので
、再送指示を発してから再送データが受信側に到達する
迄に要する時間が長ずざるという問題点がある。特に、
各々が1フレ一ム分のデータを格納する送信側バッファ
メモリを?M数個並置して送信データの読出しにおける
待ち時間をなくしたマルチバッファメモリ構成において
は、再送データが受信側に到達する迄に複数フレー1、
の送信データが送出されること心こなり、■−記問題点
は一層深刻になる。
As mentioned above, conventionally, the writing of retransmission data on the sending side was performed after receiving a 1Til transmission instruction from the receiving side, and then writing or reading the normal sending data that was being written or read. Since the retransmission is carried out after the completion of the retransmission, there is a problem that the time required from issuing the retransmission instruction until the retransmission data reaches the receiving side is not long. especially,
A transmitting buffer memory each storing one frame's worth of data? In a multi-buffer memory configuration in which M number of buffer memories are arranged in parallel to eliminate waiting time in reading transmission data, multiple frames 1,
If the transmission data is sent out, the problem described in (1)-- becomes even more serious.

〔問題点を解決するための手段〕[Means for solving problems]

」二記の問題点を解決するために、本発明により、デー
タ送受信システムにおいて、受信側で受信データにエラ
ーを検出すると、受信側バッファメモリの読出しを禁止
すると共に送信側および受信側のバッファメモリをクリ
アして再生データを書込め、 受信側で111送データを受信側バッファメモリに格納
後、読出し禁11を解除することにより再送データを受
信側バッファメモリから読出ずようεこした、−とを特
徴とする再送データ送受信方法が提供される。
In order to solve the above two problems, the present invention provides a data transmission/reception system in which, when an error is detected in received data on the receiving side, reading of the receiving side buffer memory is prohibited, and the buffer memory on the sending side and the receiving side is 111 on the receiving side, and after storing the transmitted data in the receiving side buffer memory, the retransmitted data is prevented from being read from the receiving side buffer memory by canceling the read prohibition 11. A retransmission data transmission/reception method is provided.

〔作 用] 受信データ中のエラー検出に応して送信側および受イA
側のへソファメモリをクリアすることによめ、直らに再
送データを書込むことができるので、データの再送が短
時間に行われる。
[Function] In response to the detection of an error in the received data, the transmitting side and the receiving side
By clearing the side sofa memory, retransmission data can be written immediately, so data can be retransmitted in a short time.

〔実施例] 以下、添付の図面に基づいて本発明の詳細な説明する。〔Example] Hereinafter, the present invention will be described in detail based on the accompanying drawings.

同図に示される本発明の一実施例に、Lるデータ送受信
システJ・は、送信側Sと受信側Rからなっている。送
信側Sはデータ発生部r)Gと、第1のスイッチ計1と
、3つの送信側ハソフプメモリBM]、BM2および8
M3と、第2のス・イ・2チSW2と、送信側制御回路
S Cとを備えている。受信側Rは、第((のスイッチ
SW3と−3つの受信側バッファメモ1月+MiBM5
および8M6と、第4のスイッチ踵4と、データ受信側
DRと、受信側制御[01路RCとを備えている。送信
側Sの第2のスイッチSW2と受信側Rの第3のスイッ
チ鉢3とは伝送路I7にて接続されている。データ受信
部DRはエラー検出回路EDを備えており、データ発生
部11Gは初期化回路INIを備えている。
In one embodiment of the present invention shown in the figure, a data transmitting/receiving system J consists of a transmitting side S and a receiving side R. The sending side S includes a data generating unit r)G, a first switch in total, and three sending side memories BM], BM2 and 8.
M3, a second SW2, and a transmitting side control circuit SC. Receiver R has switch SW3 and -3 receiver buffers Memo 1+MiBM5
and 8M6, a fourth switch heel 4, a data receiving side DR, and a receiving side control [01 path RC. The second switch SW2 on the sending side S and the third switch pot 3 on the receiving side R are connected through a transmission path I7. The data receiving section DR includes an error detection circuit ED, and the data generating section 11G includes an initialization circuit INI.

エラー検出回路EDが受信データ中にエラーを検出して
いないときは、データ発生部DGはデータ受信部r′J
Rにおいて前回再生された]画面のデータとの差分のデ
ータを第1のスイッチSKIを介して送信側バッファメ
モリBMI、BM2、および8M3のいずれか1つに書
込む。送信側制御回路SCは送(3側ハソファメモ1月
IMI、RM2、およびFIM3における書込みまたは
読出しのタイミングを制御すると共に、第1および第2
のスイ・ノチSWIおよび跡2を制御して、送信側バッ
ファメモリ11M1.R)12、およびIIM3のいず
れか1つに送信う一−夕を書込み中ば、残りの送信バッ
ファメモリの1つから、既に書込まれている送信データ
を伝送路L、に読出ずようにしている。
When the error detection circuit ED does not detect an error in the received data, the data generation section DG detects the error in the data reception section r'J.
The difference data from the screen data previously reproduced in R is written to any one of the transmitting side buffer memories BMI, BM2, and 8M3 via the first switch SKI. The transmission side control circuit SC controls the timing of writing or reading in the sending (third side IMI, RM2, and FIM3), and also controls the timing of writing or reading in the first and second
Controls the SWI and trace 2 of the transmitting side buffer memory 11M1. R) While writing the transmission data to any one of IIM3 and IIM3, the transmission data that has already been written is not read from one of the remaining transmission buffer memories to the transmission line L. ing.

受信側では受信側制御回路RCの制御の下に、伝送路I
5を伝送されて来たデータを第3のスイッチSW3を介
して受信側バッファメモリBM4 、8M5 。
On the receiving side, under the control of the receiving side control circuit RC, the transmission line I
5 is transmitted through the third switch SW3 to the receiving side buffer memories BM4 and 8M5.

8M6のいずれかに書込むと共に8M4.8M5 、B
i12からスイッチSW4を介して順次データ受信部D
Rに読出ず。データ受信部DRは受信データをデコ−+
シて画面データを再生する。
Write to either 8M6 and 8M4.8M5, B
Data receiving unit D sequentially from i12 via switch SW4
Not read to R. The data receiving unit DR decodes the received data.
to play the screen data.

エラー検出回路EDが受信データ中にエラーを検出した
ときの動作を次に説明する。
The operation when the error detection circuit ED detects an error in received data will be described next.

エラー検出回路EDは、受信データにエラーを検出する
と、受信側制御回路RCに読出し禁lL:信号(INI
+)をIjえ、それにより該受信側制御回路RCは第4
のスイッチSW4をオフにして受信側バッファメモリB
M4.BM5、および8M6からデータ受信部I)Rへ
のデータの読出しを禁IIニする。エラー検出回路Iコ
Dはまた、エラー検出に応してデー夕発生部DC内の初
期化回路INIにデータ再送要求信号(DI?EQ)を
送る。受信側制御回路RCはまた、エラー検出回路1ミ
Dから読出し禁止信号(!Nl+)を受は取ると、受信
側バッファメモI月(M4.lE5、および8M6の内
容をクリアする。
When the error detection circuit ED detects an error in the received data, it sends a read prohibition lL: signal (INI) to the reception side control circuit RC.
+), thereby causing the receiving side control circuit RC to
Turn off the switch SW4 of the receiving side buffer memory B.
M4. Prohibits reading of data from BM5 and 8M6 to data receiving section I)R. The error detection circuit I/D also sends a data retransmission request signal (DI?EQ) to the initialization circuit INI in the data generator DC in response to error detection. When the receiving side control circuit RC also receives a read inhibit signal (!Nl+) from the error detection circuit 1MID, it clears the contents of the receiving side buffer memo I (M4, 1E5, and 8M6).

初期化回路IN+ は、エラー検出回路F、I〕から上
記データ再送要求信号(111?EO)を受は取ると、
再送データを作成すると共に、送信側制御回路SOに初
期化指示信号(INIC2)を与える。再送データは既
に送出したデータとの差分データではない1フレ一ム分
の正しいデータであり、1つ、再送データであることを
示ず再送指示ビットを含んでいる。
When the initialization circuit IN+ receives the data retransmission request signal (111?EO) from the error detection circuits F and I,
While creating retransmission data, an initialization instruction signal (INIC2) is given to the transmitting side control circuit SO. The retransmission data is correct data for one frame, not difference data from data that has already been transmitted, and includes one retransmission instruction bit that does not indicate that it is retransmission data.

送信側制御回路SCは、上記初回化指示信号(INIC
2)を受は取ると、送信側バッファメモリBMI、BM
2、および8M3のずべてを直らにクリアした後に、例
えば送信側バッファメモリBMIに初期化回路INIか
らの再送データを書込むべく第1のスイッチSWIを制
御する。送信側制御回路SCはまた、第2のスイッチ計
2を制御して、上記再送データをBMIに書込み後直ち
にそこから読出しくIO) て伝送路■、に送出する。
The transmission side control circuit SC receives the initialization instruction signal (INIC).
2) When receiving the data, the sending side buffer memory BMI, BM
After immediately clearing all of 2 and 8M3, the first switch SWI is controlled to write retransmission data from the initialization circuit INI to, for example, the sending buffer memory BMI. The transmission side control circuit SC also controls the second switch 2 to immediately read out the retransmission data from the BMI after writing it to the BMI, and send it to the transmission line (1).

受信側Rでは、再送指示検出器Ii!8Dが再送データ
中の再送指示ビットを検出すると受信側制御回路RCに
再送指示検出信号(I〕)を与え、それにより受信側制
御回路RCは第3のスイッチSW3を制御して伝送路■
4からの再送データを直ちに、例えば受信側バッファメ
モリBM4に書込む。受信側制御回路RCは、FIM4
に再送データを書込み終了後、信号(INIC1)によ
りデータ受信部r)Rへ再送データ準備完了を通知し、
第4のスイッチSW4を制御して読出し禁1にを解除し
、8M4から再送データをデータ受信部r)Rに読出ず
On the receiving side R, a retransmission instruction detector Ii! When 8D detects the retransmission instruction bit in the retransmission data, it gives a retransmission instruction detection signal (I) to the receiving side control circuit RC, and thereby the receiving side control circuit RC controls the third switch SW3 to open the transmission line
The retransmitted data from BM4 is immediately written to, for example, the receiving side buffer memory BM4. The receiving side control circuit RC is FIM4
After writing the retransmission data to the retransmission data, it notifies the data receiving unit r)R of the completion of retransmission data preparation by a signal (INIC1),
The fourth switch SW4 is controlled to release the read prohibition 1, and the retransmitted data from 8M4 is not read to the data receiving section r)R.

以」二の実施例によれば受信部で受信データにエラーを
検出すると直りに、送信側バッファメモリ、受信側バッ
ファメモリ共にクリアするようにしたので、読出し中あ
るいは書込み中のバッファメモリの動作の終了を待つ必
要なしに直ちに再送データの書込みおよび読出しができ
る。
According to the second embodiment, as soon as the receiving unit detects an error in the received data, both the transmitting side buffer memory and the receiving side buffer memory are cleared, so that the operation of the buffer memory during reading or writing is easily controlled. Retransmission data can be written and read immediately without the need to wait for completion.

なお、本発明は上記の実施例に限定されるものではなく
、例えばバッファメモリの数は送信側、受信側共に任、
aの数でよい。
Note that the present invention is not limited to the above-described embodiments; for example, the number of buffer memories can be determined by both the transmitting side and the receiving side.
The number of a is sufficient.

〔発明の効果〕〔Effect of the invention〕

以−にの説明から明らかなように、本発明によれば、デ
ータ送受信システムにおいて、受信データ中にエラーを
検出したとき、送信側および受イ8例のバッファメモリ
をクリアした後に再送データを送出するようにしたので
、エラー検出から再送データが受信側に到達する迄の時
間が短縮され、特に画像データ伝送において誤りを含む
画面が表示される時間を短縮できるという効果が得られ
る。
As is clear from the above description, according to the present invention, in a data transmission/reception system, when an error is detected in received data, retransmission data is sent after clearing the buffer memories of the transmitting side and the receiving side. As a result, the time from error detection to the time when retransmitted data reaches the receiving side is shortened, and in particular, the time during which a screen containing an error is displayed during image data transmission can be shortened.

【図面の簡単な説明】[Brief explanation of drawings]

添I−Jの図面は本発明の一実施例による再送データ送
受信方式を説明するだめのブロック図である。 S・・・送信側、     I≧・・・受信側、DG・
・・データ発り17部、  IN+・・・初期化回路、
RMI−8M3・・・送信側バッファメモリ、SC・・
・送信側制御回路、r)R・・・データ受信部、ED・
・・エラー検出回路、 BM4〜l’1M6・・・受信側バッファメモリ、RC
・・・受信側バッファメモリ、 D・・・再送指示検出回路。
The drawings in Appendices I-J are block diagrams for explaining a retransmission data transmission/reception system according to an embodiment of the present invention. S...Sending side, I≧...Receiving side, DG・
...Data starting part 17, IN+...Initialization circuit,
RMI-8M3...Sending side buffer memory, SC...
・Transmission side control circuit, r)R...data reception section, ED・
...Error detection circuit, BM4 to l'1M6...Reception side buffer memory, RC
...Reception side buffer memory, D...Retransmission instruction detection circuit.

Claims (1)

【特許請求の範囲】 1 データ送受信システムにおいて、受信側で受信デー
タにエラーを検出すると、受信側バッファメモリの読出
しを禁止すると共に送信側および受信側のバッファメモ
リをクリアして該送信側バッファメモリに再送データを
書込み、該受信側で該再送データを受信側バッファメモ
リに格納後、読出し禁止を解除することにより再送デー
タを該受信側バッファメモリから読出すようにしたこと
を特徴とする再送データ送受信方法。 2 送信側に、データ発生手段と、該データ発生手段か
らの送信データを格納する送信側メモリと、該送信側メ
モリに対するデータの書込み/読出しを制御する送信側
制御手段を具備し、受信側に、該送信側メモリからのデ
ータを格納する受信側メモリと、該受信側メモリからの
データを受信するデータ受信手段と、該受信側メモリに
対するデータの書込み/読出しを制御する受信側制御手
段とを具備するデータ送受信システムにおいて、該デー
タ受信手段はエラー検出手段を具備し、該エラー検出手
段は、受信データのエラーを検出すると該受信側制御手
段の制御の下に該受信側メモリから該データ受信手段へ
のデータ読出しを禁止させると共に該受信側メモリをク
リアし、且つ、該データ発生手段にデータ再送要求信号
を送るものであり、 該データ発生手段は、初期化手段を具備し、該初期化手
段は、該データ再送要求信号に応答して再送指示検出デ
ータを含む再送データを作成すると共に、該データ再送
要求信号に応答して該送信側制御手段の制御の下に該送
信側メモリをクリアした後に該再送データを該送信側メ
モリに書込むものであり、 該受信側は、該送信側メモリから送られて来た該再送デ
ータから該再送指示検出データを検出する再送指示検出
手段を具備し、 該再送指示検出手段は、該再送指示検出データの検出に
応じて、該受信側制御手段の制御の下に、該受信側メモ
リに該再送データを書込ませた後に該受信側メモリから
のデータの読出し禁止を解除させるものであることを特
徴とする再送データ送受信装置。
[Claims] 1. In a data transmission/reception system, when an error is detected in the received data on the receiving side, reading of the receiving side buffer memory is prohibited, and the buffer memories on the sending side and the receiving side are cleared and the data is stored in the sending side buffer memory. The retransmission data is characterized in that the retransmission data is read from the reception side buffer memory by writing the retransmission data into the reception side buffer memory at the reception side, and after storing the retransmission data in the reception side buffer memory, canceling the read prohibition. How to send and receive. 2. The transmitting side is equipped with a data generating means, a transmitting side memory for storing transmission data from the data generating means, and a transmitting side control means for controlling writing/reading of data to and from the transmitting side memory, and the receiving side , a receiving side memory for storing data from the sending side memory, a data receiving means for receiving data from the receiving side memory, and a receiving side control means for controlling writing/reading of data to/from the receiving side memory. In the data transmitting/receiving system, the data receiving means includes an error detecting means, and when the error detecting means detects an error in the received data, the receiving side memory receives the data under the control of the receiving side control means. The data generation means is provided with an initialization means, and the data generation means is provided with an initialization means, and the data generation means is provided with an initialization means, and the data generation means is provided with an initialization means, and a data retransmission request signal is sent to the data generation means. The means creates retransmission data including retransmission instruction detection data in response to the data retransmission request signal, and clears the transmitting side memory under the control of the transmitting side control means in response to the data retransmission request signal. After that, the retransmission data is written into the transmitting side memory, and the receiving side is equipped with retransmission instruction detection means for detecting the retransmission instruction detection data from the retransmission data sent from the transmitting side memory. The retransmission instruction detection means writes the retransmission data into the reception side memory and then writes the retransmission data from the reception side memory under the control of the reception side control means in response to the detection of the retransmission instruction detection data. What is claimed is: 1. A retransmission data transmitting/receiving device, characterized in that the retransmission data transmitting/receiving device is capable of canceling a read prohibition of data.
JP60165671A 1985-07-29 1985-07-29 Method and equipment for transmitting and receiving retransmission data Granted JPS6226948A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60165671A JPS6226948A (en) 1985-07-29 1985-07-29 Method and equipment for transmitting and receiving retransmission data

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60165671A JPS6226948A (en) 1985-07-29 1985-07-29 Method and equipment for transmitting and receiving retransmission data

Publications (2)

Publication Number Publication Date
JPS6226948A true JPS6226948A (en) 1987-02-04
JPH0410261B2 JPH0410261B2 (en) 1992-02-24

Family

ID=15816810

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60165671A Granted JPS6226948A (en) 1985-07-29 1985-07-29 Method and equipment for transmitting and receiving retransmission data

Country Status (1)

Country Link
JP (1) JPS6226948A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5333137A (en) * 1990-08-06 1994-07-26 Fujitsu Limited Coding system having data controlling mechanism activated when error is detected
US8321736B2 (en) 2008-03-25 2012-11-27 Fujitsu Limited Transmission system, transmission method and communication device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52147910A (en) * 1976-06-03 1977-12-08 Toshiba Corp Error control system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52147910A (en) * 1976-06-03 1977-12-08 Toshiba Corp Error control system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5333137A (en) * 1990-08-06 1994-07-26 Fujitsu Limited Coding system having data controlling mechanism activated when error is detected
US8321736B2 (en) 2008-03-25 2012-11-27 Fujitsu Limited Transmission system, transmission method and communication device

Also Published As

Publication number Publication date
JPH0410261B2 (en) 1992-02-24

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