JPS62266915A - Power voltage detection circuit - Google Patents

Abstract

PURPOSE:To detect a power voltage by utilizing a forward voltage of a PN junction element as a reference potential so as to utilize the MOS process as it is and using a detection voltage with less variation without an externally mounted component. CONSTITUTION:In selecting resistors 31, 32, a point where a potential V23 of a node 23 and a potential V33 of a node 33 crosses is set. For example, the potentials are crossed with a voltage VDD at nearly 3.6V and a differential amplifier circuit 40 receives the potential V23 of the node 23 and the potential V33 of the node 33. The two potentials are compared and when the potential V23 of the node 23 is lower, an L level and in case of a higher voltage, an H level is outputted respectively. Thus, the potential V53 of the output node 53 of a CMOS inverter 50 changes from an H level to an L level with the voltage VDD of nearly 3.6V. Then the detection voltage of the power voltage VDD is nearly 3.6V, and of the voltage VDD is lowered more than said value, the potential V53 of the node 53 changes from the L to the H level and the power supply voltage drop is detected.

Description

[Detailed Description of the Invention] [Object of the Invention] (Field of Industrial Application) This invention has 1! The present invention relates to an N-imposed voltage detection circuit that detects a drop in source voltage, and particularly relates to a power supply voltage detection circuit that can be rounded by an MOS process and is less susceptible to manufacturing variations.

(Prior art) A power supply voltage detection circuit that detects a drop in the power source is as follows:
Conventionally, the configuration is as shown in FIG. 4, for example.

In FIG. 4, two resistors 81 and 82 and an N channel MO8t-
The source and drain of the transistor 83 are connected. Each of the resistors 81 and 82 has a high resistance of about 1 MΩ, and is usually composed of a P-type diffused resistor or the like. Further, the gate of the transistor 83 is connected to a node 84 on its drain side.

Roughly speaking, a resistor 85 and a source and drain of a channel MO5 transistor 86 are connected between Voo and Vss. The resistor 85 is externally attached when the entire circuit is integrated into one chip, and corrects variations in the threshold voltage vth of the transistor 86. Further, the gate of the transistor 86 is connected to a node 87 where the resistors 81 and 82 are connected in series.

Furthermore, there is a P-channel MOS between Voo and VB2.
A CMOS inverter 90 consisting of a transistor 88 and an N-channel ~1ost'' transistor 89 is connected, and the gates of both transistors 88 and 89 are connected to the resistor 85.
and a connection node 91 of transistor 8G. A detection signal is output from a node 92 which is a common connection point between the drains of transistors 88 and 89.

The characteristic diagram in FIG. 5 shows potential changes at each node of the circuit in FIG. 4. Here, the transistor 83 is a gate.

Since the drains are connected, the pentode operates, and the resistors 81 and 82 have high resistance, so the electric iT! Lit pressure Vo
.

When the potential V84 of the node 84 is raised from OV, the potential V84 of the node 84 is ΔV (approximately 0.
From the point where the potential becomes higher by -0.3 V to 2 V, the potential becomes almost constant. Here, since the values of resistors 81 and 82 are made equal, the potential V87 of node 87 is always equal to VDO.
and the potential is approximately 1/2 of the potential V84 of the node 84,
This potential V87 rises at a gentler slope than VDO as VD[+ rises. Since this node 87 is connected to the gate of the transistor 86, the voltage at the node 91
Rank 91 rises little by little at first, but after reaching a maximum value, it then declines. After reaching the maximum value, when the potential V91 at the node 91 falls below the circuit threshold voltage of the inverter 90, the inverter 90 performs an inverting operation and the potential V92 at the node 92 changes from the low level to the H level. That is, Voo at this time is the detection voltage of this circuit, which in the illustrated case is approximately 4°5.

By the way, in the conventional circuit described above, the detection voltage is determined by the resistance ratio of the resistor 81.82 and the threshold m of the transistor 86.
Voltage and resistance of resistor 85. Here, resistance 81.
Although the ratio of 82 can be made almost constant when the entire circuit is integrated, the threshold voltage of the transistor 86 varies depending on the manufacturing loft. Therefore, the resistor 85 is provided for the purpose of correcting this variation, and this resistor 85 is used to control the circuit. l! It is attached externally when it is integrated into an integrated circuit. As a result, in the past, it was not possible to integrate everything into a single chip, and the manufacturing cost was increased by the provision of the resistor 85.

Roughly speaking, the value of the resistor 85 needs to be selected depending on the threshold voltage of the transistor 86. That is, during a chip die sort test, it is necessary to adjust the single-value voltage of the loft and determine the resistance for each loft.

That is, when shipping the chips, it is necessary to manage each lot, which also has the drawback of increasing the price.

(Problems to be Solved by the Invention) As described above, the conventional circuit has the disadvantage that a resistor must be externally attached when it is integrated into an integrated circuit, resulting in a high price.

This invention was made in consideration of the above circumstances, and its purpose is to provide a power supply voltage detection system that can incorporate everything into an integrated circuit, thereby reducing manufacturing costs. The purpose is to provide circuits.

[Structure of the Invention] (Means for solving the fmm point) The power supply voltage detection circuit 1 of the present invention includes a well region of a first conductivity type formed on a semiconductor substrate and a second conductivity type formed on the inclined wall of the well. a potential shifting means for generating a first potential shifted by this reference potential from the voltage 1Tiii with the forward voltage of the PN junction element made of a type semiconductor region as a reference potential; 2
The electric potential dividing means generates a potential, and the electric potential comparing means compares the first potential and the second potential.

(Function) In the N applied voltage detection circuit of the present invention, a PN junction element consisting of a well region of a first conductivity type formed on a semiconductor substrate and a semiconductor region of a second conductivity type formed on this well region is arranged in the following order: By using the directional voltage as a reference potential,
By using the MOS process as is and without using any external parts, the power supply voltage can be detected with less variation in the detection voltage.

(Example) Hereinafter, one example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing 11 configurations of the N applied voltage detection circuit according to the present invention.

In the figure, 10 is a bias circuit. In this bias circuit 10, the source of a P channel MoS transistor 11 is connected to an N applied voltage Voo. The gate of this transistor 11 is connected to the ground voltage Vas, and the drain is connected to the drain of the N-channel to 10S transistor 12. The source of transistor 12 is connected to ground voltage Vas, and the gate is connected to its drain. In this bias circuit 10,
A predetermined bias voltage is formed according to the current determined by the element dimensions (particularly the channel width) of the transistor 11.
It will be done.

20 is a potential shift circuit. This potential shift circuit 20
Now, add a bipolar NPN transistor 21 to Voo.
The collector and base of are connected.

The emitter of this transistor 21 is an N-channel MOS.
The drain of transistor 22 is connected.

The source of this transistor 22 is connected to Vss, and the bias voltage generated by the bias circuit 10 is supplied to the gate. Here, NPN type transistor 2
1 has the collector and base connected, so in effect,
It acts as a PN junction diode with the base as the P pole and the emitter as the N pole. Further, the transistor 22 and the transistor 12 in the bias circuit 10 constitute a so-called current mirror circuit, and the element dimensions of the transistor 12 and the transistor 22 are set at a one-to-one ratio. Therefore, ff1R, which is approximately equal to 'iFR flowing through the transistor 12, flows through the transistor 22, and this current determines the operating point of the PN junction diode.

Then, an output potential is obtained at a node 23 which is a connection point between the emitter of the NPN transistor 21 and the drain of the transistor 22.

30 is a potential dividing circuit. In this potential dividing circuit 30, two resistors 31 and 32 are connected in series between Voo and Vss. Both resistors 31 and 3.2 are each formed of, for example, a lightly doped P-type diffusion region, and divide the voltage between VOO and Vss according to their resistance ratio and output it from node 33.

40 is a differential amplifier circuit that compares the output potential of the potential shift circuit 20 and the output potential of the potential divider circuit 30. This differential amplifier circuit 40 includes a differential amplifier section 46 in which P-channel MOS transistors 41 and 42 are load elements, N-channel MOS transistors 43 and 44 are drive elements, and N-channel MOS transistor 45 is a current source element; Channel MOS transistor 47 and N-channel MO
It is composed of an inverting amplifying section 49 that amplifies the output of the difference e amplifying section 46, which is composed of an S transistor 1) 48. Then, the potential V33 of the node 33 is supplied to the gate of the transistor 43 of the differential amplification section 46, the potential V23 of the node 23 is supplied to the gate of the transistor 44, and the output potential of the differential amplification section 46 is supplied to the gate of the transistor 43 of the differential amplification section 46. is supplied to the gate of transistor 47. In addition, the transistor 45
A bias voltage generated by the bias circuit 10 is supplied to the gates of and 48. Here transistor 45
．． 48 transistors 12 in each bias circuit 10
constitutes a current mirror circuit, and the element dimensions of each transistor 45°48 and transistor 12 are 1.
A current approximately equal to the current flowing through the transistor 12 flows through each of the transistors 45 and 48, and this current flows through the differential amplifier section 46 and the inverting amplifier section 49.
The operating current will be .

50 is a CMOS for amplifying the output of the differential amplifier circuit 40;
It is an inverter. This CMOS inverter is composed of a P channel MOS transistor 51 and an N channel MOS transistor 52 connected between Voo and Vss.

Each MO3 transistor constituting the above embodiment circuit is constructed using a normal CMOS process, and the bipolar NPN transistor 21 in the potential shift circuit 20 is constructed as shown in the cross-sectional view of FIG. It is structured.

That is, in FIG. 2, 61 is an N-type semiconductor substrate, and on this substrate 61 there is provided a P-well region 2 that is formed at the same time as the P-well IM is formed for forming a channel 840S transistor. There is. A P4 type region 63 is provided in the boundary between the P well region 62 and the substrate 61. Further, on the P well region 62, N
An N+ type region 65 is provided on the + type region 64 and the substrate 61, respectively. Here, the NPN type transistor 21 has an N type substrate 61 as its collector, and a P well region 62 as its collector.
The N4 type region 65 and the P+ type head region 63 are electrically connected, and the power supply voltage V is applied thereto. 0 is supplied. Further, an N+ type region 64 is connected to the node 23.

Next, the operation will be explained. FIG. 3 shows the voltage at voltage V in the above actual mVA circuit. FIG. 3 is a characteristic diagram showing potential changes in the potentials V23, V33, and VS2 of each node 23, 33, and 53 when 0 is raised from O■. Potential V of node 23
23 is a power supply potential. . The potential is lowered by the forward voltage VF at the base-emitter junction of the NPN transistor 21. Therefore, this potential V23 is about wig V. It changes by moving parallel to the rise of 0. On the other hand, the potential V33 of the node 33 is set to R1, the value of the resistor 31, and the value of the resistor 32 to R1.
If the value of is R2, then (R2/ (R1+R2))XV
It is given by oo. Therefore, as the power supply potential VDD increases, the potential V33 changes at a certain rate with respect to DO. Here, as shown in FIG. 3, depending on how R1 and R2 are selected, the potential V23 of the node 23 and the potential V23 of the node 33 are
33 can be freely set. In this example, V. 0 is approximately 346V. The differential amplifier circuit 40 has the potential V23 of the node 23 and the node 33.
The potential V33 of the node 23 is compared, and when the potential V23 of the node 23 is lower, the L level is output, and when the potential V23 of the node 23 is higher, the H level is output. Therefore, C.M.O.
As shown in FIG. 3, the potential V53 of the output node 53 of the S inverter 50 changes from H level to L level when Voo is approximately 3.6V. As a result, in this embodiment circuit, the detection voltage of the power supply voltage IIVoo is approximately 3.6
When VOO falls below this value, the potential V53 of node 53 changes from L level to H level, and a drop in power is detected.

By the way, in this embodiment circuit, the detection N of the power supply voltage VOO is
The occurrence of pressure variations is significantly suppressed compared to conventional circuits. In the conventional circuit, the detection voltage is greatly affected by variations in the threshold mi voltage vth of the MOS) transistor. Incidentally, the maximum variation in yth between lots is 600 mVN degrees.

However, in the above embodiment, the base 0! The forward voltage VF of the PN junction element is used as the voltage, and the variation in the value of VF is at most about 10 mV between lots, which is about 1150 or less than the variation in vth. Therefore, a conventional correction means is not necessary.

Furthermore, the above-mentioned PN junction element can be easily put to practical use by a normal C to 108 process, and the whole can be made into one chip. This eliminates the need for lot management in the manufacturing process, simplifies the set assembly process, and reduces costs by eliminating the need for external parts.
Overall, it is possible to significantly reduce the loss by 1~.

It goes without saying that the present invention is not limited to the above embodiments, and that various modifications are possible.

For example, in the above embodiment, a case has been described in which a PN junction element using an NPN transistor using a P well region is used as the PN junction element, but a PN junction element using a PNP transistor using an N well region may also be used. Of course it's a good thing.

[Effects of the Invention] As explained above, according to the present invention, it is possible to provide a power supply voltage detection circuit that can incorporate everything into an integrated circuit, thereby reducing the manufacturing cost. .

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, and FIG.
The figure is a cross-sectional view showing the structure of a part of the element groove of the above-described practical example circuit, FIG. 3 is a characteristic diagram for explaining the above-mentioned embodiment, FIG. 4 is a circuit diagram of a conventional circuit, and FIG. It is a characteristic diagram of a circuit. 10... Bias circuit, 20... Potential shift circuit,
21... Bipolar NPN transistor, 30
...Potential divider circuit, 3L32...Resistor, 40...
Differential amplifier circuit, 46... Differential amplifier section, 49... Inverting amplifier section, 50... c: Mos inverter, 61...
N-type straw plate, 62...P-type well region, 64...N
+ type territory applicant agent patent attorney Takehiko Suzuta Figure 3 Figure 4

Claims (1)

[Claims] The forward voltage of a PN junction element consisting of a first conductivity type well region formed on a semiconductor substrate and a second conductivity type semiconductor region formed on this well region is set as a reference potential, and this reference potential is changed from the power supply voltage. potential shifting means for generating a first potential shifted by the amount of the first potential; potential dividing means for generating a second potential by dividing the power supply voltage by a resistor;
1. A power supply voltage detection circuit comprising: potential comparison means for comparing a potential of the first potential and a second potential.