JPS62266477A - Inspection of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the generation of a VCO frequency AGC drift characteristic deficiency, by determining a differential voltage correlative with a forward current of a gain control diode of a video intermediate frequency (VIF) amplifier using a DC characteristic measuring method. CONSTITUTION:A PLL synchronous detection type semiconductor integrated circuit device 11 for VIF which contains a VIF amplifier built by connecting differential amplification steps 12, 13 and 14 respectively with gain control diodes D11 and D12, D21 and D22, and D31 and D32 is to be inspected. First and second DC voltages different in the level are applied to external terminals 15 and 16 for VIF input and each pair of transistors Q11 and Q12, Q21 and Q22, and Q31 and Q32 at the differential amplification steps 12-14 is turned ON at one end is turned OFF at the other end. With such an arrangement, first and second output voltages corresponding to the DC voltages are measured at external terminals 17 and 18 connected to collector terminals of the transistors Q31 and Q32 at the final differential amplification step 14 to obtain a differential voltage thereof. The VCO frequency drift characteristic of the device 11 is inspected from the correlationship between the VCO frequency drift characteristic thereof 11 and the differential voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for testing a video intermediate frequency (VIP) semiconductor integrated circuit device using a phase-locked loop (PLL) synchronous detection method, and in particular to a method for testing a video intermediate frequency (VIP) semiconductor integrated circuit device using a phase-locked loop (PLL) synchronous detection method. This relates to an inspection method that allows frequency AGC drift characteristics to be checked by probe inspection.

2. Description of the Related Art In recent years, semiconductor integrated circuit devices employing a PLL synchronous detection method have begun to be used as VIP signal detectors for home television receivers. This PLL synchronous detection method reproduces a synchronous carrier wave using a built-in VCO. The PLL synchronous detection method will be explained below with reference to FIG.

In FIG. 3, a television signal received by an antenna 1 is selected by a tuner 2, frequency-converted to VIP, and then transmitted to a semiconductor integrated circuit device 3 for VIP signal detection. . VI input from the VIF input external terminal 4 of the integrated circuit device 3
After the P signal is amplified by the VIP amplifier 5, it is sent to a VIF signal detector (multiplier) 6 and a phase comparator (multiplier) 7, respectively. In the phase comparator 7, the phase of the synchronous carrier wave, which is the output signal of the VCO 9, is compared with the signal whose phase is shifted by 90" by the phase shifter 10. If the phase is shifted, an error voltage corresponding to the magnitude of the shift is phase-compared. is generated from the filter 7 and inputted to the low-pass filter 8.Then, the low-pass filter 8
A signal for controlling the VCO 9 is outputted to further reduce the phase shift, thereby controlling the total carrier frequency of the VCO 9. In this way, the synchronous carrier wave, which has the same frequency and a constant phase relationship as the input VIF signal, can be reproduced at a constant and stable level without being affected by the level of the input VIP signal. It is possible to obtain a high quality detection signal even during modulation.

The VIF signal detector of this PLL synchronous detection method has V
The free-running excavation frequency of the VCO fluctuates in response to changes in IPAGC voltage and temperature. This will be explained below.

Since the output signal of the VCO is a high frequency called VIP, a part of the output signal propagates to the VIF input external terminal 4 of the integrated circuit device 3 due to radiation, parasitic capacitance of various parts of the integrated circuit device, etc. , and is input together with the VIF signal from there. In other words, it has returned to the integrated circuit device 3. This feedback component of the vCO output signal is extremely small and usually does not pose a problem, but when the input TV signal from antenna 1 becomes weak and the level of the feedback component of the vCO output signal becomes relatively large, The PLL circuit operates not on the VIF signal but on the feedback component of the VCO output signal. As a result, the integrated circuit bag RA3 does not operate normally as a detector. At this time, since the input TV signal is weak, the AGC voltage is VI
The gain of the F amplifier is changed to be maximum, and the free-running excavation frequency of the VCO 9 is changed (drifted) to a frequency that differs from the number of input waves of the VIP input. The amount of change in the 700 frequency corresponds to the likelihood of the above-mentioned abnormal operation occurring.

Since the abnormal operation described above is a problem in terms of quality assurance of the television receiver in which the integrated circuit device 3 is built-in,
The integrated circuit device 3 in which the abnormal operation may occur needs to be removed as defective in the final inspection process so that it is not shipped as a product. To this end, the VCo frequency AGC drift characteristics of the integrated circuit device 3 are checked in the final inspection process.

Problems to be Solved by the Invention However, when the vCO frequency AGC drift characteristic of the semiconductor integrated circuit device 3 is checked in the final inspection process as described above, the assembly of the integrated circuit device under test is not performed in the final inspection process. Since the process is completed, the manufacturing cost is approximately three times higher than the cost in the wafer state before assembly. For this reason, the monetary loss caused by discarding defective products is greater than that in the wafer state.

The present invention provides a method for testing a semiconductor integrated circuit device with the purpose of reducing monetary losses due to the occurrence of defective VCO frequency AGC drift characteristics.

Means for Solving the Problems In order to solve the above problems, the present invention provides a PLL synchronous detection method incorporating a VIP amplifier configured by cascading a plurality of differential amplification stages each equipped with a gain control diode. A semiconductor integrated circuit device for VIF is used as an element to be tested, and with power applied to the integrated circuit device, first and second DC voltages of different levels are applied to the VIF input external terminal of the integrated circuit device. Then, one of the paired transistors constituting the plurality of differential amplification stages is turned on and the other is turned off, and the external terminal of the integrated circuit device to which the collector terminal of the transistor of the final differential amplification stage is connected is turned on. , measuring first and second output voltages corresponding to the first and second DC voltages to obtain a difference voltage;
Based on the correlation between the 700 frequency drift characteristic of the integrated circuit device and the differential voltage obtained in advance, the
This test is designed to test O frequency AGC drift characteristics.

In this way, the DC characteristics (static characteristics) measurement method provides a differential voltage that is correlated with the forward current of the gain control diode that determines the gain of the VIP amplifier, and this allows the AC characteristics (dynamic characteristics) to be measured. ■Co frequency AGC drift characteristics, which are characteristics), can be checked by probe inspection.

Embodiment FIG. 1 is a circuit diagram showing an embodiment of the method for testing a semiconductor integrated circuit device of the present invention.

In FIG. 1, reference numeral 11 denotes a PLL synchronous detection type VIF semiconductor integrated circuit device, and the circuit shown in the integrated circuit device 11 includes three differential amplification stages 12, 13, and 14.
This is the part of the VIF amplifier with . The VIF amplifier is
It is composed of a plurality of cascade-connected differential amplification stages 12, 13, and 14. The first-stage differential amplifier pair 12 includes transistors Qll, Q10 forming a differential amplifier, and gain control diodes DI1 . DI2 and collector load resistance R11, R+
2, and emitter resistor RI3. RI4, the input impedance of the differential amplifier stage is increased, and the transistor Q11 is
．． Transistors Q +3 and Q14 for forming a bias circuit for Q12, diodes D +3 + D14 for level shifting, and transistor Q1
1. Resistor R+s forming the bias circuit of Q10,
It consists of RIG and R+7. The other differential amplification stages 13 and 14 are also configured as shown in FIG. 1 using the same elements as the first stage. 15 and 16 are external terminals for VIF input of the integrated circuit device 11, and 17 and 18 are the VIF input terminals of the integrated circuit device 11.
The collector (
This is the external terminal to which the output terminal of the V IF amplifier is connected. Further, 19 is a bias power supply for the VIP amplifier, and 20 is a VIFAGC circuit that controls the gain control diode.

Now, when the first DC voltage VIN■ is applied to the external terminal 15 to turn on the transistor Q++ of the first differential amplifier stage 12 and turn off the transistor QI2, the transistor of the next differential amplifier stage 13 turns on. Q21 is turned off, transistor Q22 is turned on, transistor Q31 of the final differential amplifier stage 14 is turned on, transistor Q32 is turned off, and the output voltage of the external terminal 18 to which the collector terminal of transistor Q32 is connected is at the high level. The output voltage VOUT■ becomes 1. Next, a second DC voltage V having a different level from the first DC voltage is applied to the external terminal 15.
When IN■ is applied to turn off the Qth transistor of the first differential amplifier stage and turn on the transistor Q12, the transistor Q31 of the final differential amplifier stage turns off and the transistor Q32 turns on. The output voltage of the terminal 18 becomes a low level second output voltage V OUT■.

Here, the bias power supply voltage is VCC, the forward current of the gain control diode D32 is I D32, the transistor Q32. If the base-emitter voltage of Q34 and the forward voltage of diode D34 are VD, and the base current of transistor Q32 is ignored, the first output voltage VOUT■ and the second output voltage VQUT■ are each expressed as VOUT(D=VCCR32XQ @A==vC(---
---(1), and by calculating the differential voltage ΔVOUT from equations (1) and (2), the following equation (3) is obtained.

ΔV 0IJT :V 0LITΦ-V OUT■(3
), since Vcc, VD, R32 and R34 are considered to be almost constant values, the differential voltage ΔV OUT is the forward current ID3 of the gain control diode D32.
It can be seen that it is a linear function of 2. That is, the differential voltage Δ
There is a correlation between VOUT and the forward current 1032 of the gain control diode D32.

The VCO frequency AGC drift characteristic is a 700° frequency change in response to a change in AGC voltage where the gain of the VIP amplifier is minimum and maximum, so find the difference voltage ΔVOUT at the AGC voltage where the gain of the VIP amplifier is maximum, and When the relationship between the vCO frequency AGC drift characteristics is experimentally determined, there is a good correlation as shown in FIG. The reason for this is thought to be as follows.

Since the forward current of the gain control diode determines the gain of each differential amplifier stage and therefore of the entire VIP amplifier, this forward current naturally has a correlation with the gain of the VfF amplifier, and the gain of the VIP' amplifier is If it changes, the phase difference between the input signals will also change. The measurement of VC○ frequency AGC drift characteristics is carried out without applying VIF signal, so the input signals of the phase comparator are both output signals of vCO, and one passes through only a 90° phase shifter and then the phase is compared. The other is the signal that is applied to the phase comparator after passing from the VIP input external terminal and returning through the VIF amplifier. Therefore, when measuring the VCO frequency AGC drift characteristic, the PLL circuit functions so that the phase difference between these two signals becomes O. Therefore, if the gain of the VIP amplifier changes, and as a result, the phase difference between the input signal and the output signal of the above V[F amplifier changes, then in order to make the phase difference between the two signals applied to the phase comparator O, VC
This means that the oscillation frequency of O needs to change.

In other words, the differential voltage Δvout has a correlation with the forward current of the gain control diode, the forward current of the gain control diode determines the gain of the VIP amplifier, and the gain of the VIF amplifier is determined by the phase difference between the person and the output amount. It is related to the VC◯ frequency AGC drift characteristic via the gain versus gain characteristic. Therefore, since the differential voltage Δvou'r has a correlation with the VCO frequency AGC drift characteristic, the VCO frequency AGC drift characteristic, which is an AC characteristic, can be checked in a probe test (inspection of DC characteristics).

Effects of the Invention As described above, according to the present invention, it is possible to check the VCO frequency AGC drift characteristic, which is an AC characteristic, by probe inspection, so it is possible to reduce the occurrence of defects in the above characteristics in the final inspection process. Therefore, it is possible to reduce monetary losses due to the occurrence of defects, and the industrial value is high.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of the main part of a semiconductor integrated circuit device used in an embodiment of the present invention, and Fig. 2 shows the correlation between the vCo frequency AGC drift characteristic and the DC characteristic obtained by the measurement method of the present invention. 3 are block diagrams for explaining a general PLL synchronous detection method. 11... Semiconductor integrated circuit device for VIF using PLL synchronous detection method, 12, 13.14... Differential amplification stage, 15.16... External terminal for VIF input, 1
7.18...External terminal, 19...Bias power supply, 20...VIFAGC circuit. Name of agent: Patent attorney Toshio Nakao and one other person VCO Kite Su 1 AGc Drift

Claims (1)

[Claims] A pair of transistors constituting a differential amplifier, a load resistor connected between the collector of each of these transistors and a bias power supply, an emitter resistor connected between each emitter of the transistor and a reference potential, and It has a plurality of differential amplification stages each including a pair of diodes connected in series with the anode side common between the emitters of the transistors and an AGC circuit connected to the anode of the pair of diodes. A semiconductor integrated circuit for video intermediate frequency using a phase-locked loop synchronous detection method, which incorporates a video intermediate frequency amplifier configured by connecting the collector output terminals of a pair of transistors to the bases of a pair of transistors in the next differential amplification stage. With an apparatus as an element to be tested, and with power applied to the integrated circuit device, first and second DC voltages of mutually different levels are applied to the external terminal for video intermediate frequency input of the integrated circuit device. One of the transistor pairs constituting the plurality of differential amplification stages is turned on and the other one is turned off, and the above-mentioned A method for testing a semiconductor integrated circuit device, comprising a step of measuring first and second output voltages corresponding to first and second DC voltages, respectively, and obtaining a differential voltage therebetween.