JPS62263695A - Method of interlayer wiring of laminated board - Google Patents
Method of interlayer wiring of laminated boardInfo
- Publication number
- JPS62263695A JPS62263695A JP10740286A JP10740286A JPS62263695A JP S62263695 A JPS62263695 A JP S62263695A JP 10740286 A JP10740286 A JP 10740286A JP 10740286 A JP10740286 A JP 10740286A JP S62263695 A JPS62263695 A JP S62263695A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- film layer
- metal
- ceramic thin
- ceramic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 17
- 239000011229 interlayer Substances 0.000 title claims description 8
- 239000010409 thin film Substances 0.000 claims description 68
- 239000010410 layer Substances 0.000 claims description 62
- 239000000919 ceramic Substances 0.000 claims description 45
- 239000002184 metal Substances 0.000 claims description 40
- 229910052751 metal Inorganic materials 0.000 claims description 40
- 239000000758 substrate Substances 0.000 claims description 14
- 229910045601 alloy Inorganic materials 0.000 claims description 10
- 239000000956 alloy Substances 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 4
- 238000003475 lamination Methods 0.000 claims 1
- 150000002500 ions Chemical class 0.000 description 12
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000001771 vacuum deposition Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910052724 xenon Inorganic materials 0.000 description 1
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、例えばＩＣ１半導体素子等の電子デバイス
実装用のパッケージや各種基板等に用いられるいわゆる
薄膜タイプの積層基板を作製する際における眉間配線方
法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to glabella wiring in the production of so-called thin film type laminated substrates used for packages for mounting electronic devices such as IC1 semiconductor elements, various substrates, etc. Regarding the method.
上記のような用途に用いられるものであって、配線用の
金属薄膜層と電気絶縁性を有するセラミック薄膜層とを
密着性良く積層したいわゆる薄膜タイプの積層基板が同
一出願人によって別途提案されている。A so-called thin-film type multilayer substrate, which is used for the above-mentioned applications and has a metal thin film layer for wiring and a ceramic thin film layer having electrical insulation properties laminated with good adhesion, has been separately proposed by the same applicant. There is.
その−例を第２図を参照して簡単に説明する。An example thereof will be briefly explained with reference to FIG.
この積層基板２は、真空中において、基体４上に、真空
蒸着とイオン照射の併用によって電気絶縁性を有するセ
ラミック薄膜層６ａを被着させ、その上に真空蒸着とイ
オン照射の併用によって配線用の金属薄膜層８ａを被着
させ、以降適宜これらの工程を繰り返して、基体４上に
セラミック薄膜層６ａ、６ｂ・・・と金属薄膜層８ａ、
８ｂ・・・を交互に積層したものである。この場合、各
界面付近には、イオンの押し込み（ノックオン）作用に
より、その両側の構成物質を含んで成る混合層がそれぞ
れ形成されるので、セラミック薄膜層６ａ。This laminated substrate 2 is produced by depositing an electrically insulating ceramic thin film layer 6a on a base 4 in vacuum using a combination of vacuum deposition and ion irradiation, and then applying a combination of vacuum deposition and ion irradiation onto the ceramic thin film layer 6a for wiring. The metal thin film layer 8a is deposited, and thereafter these steps are repeated as appropriate to form the ceramic thin film layers 6a, 6b, . . . and the metal thin film layers 8a,
8b... are laminated alternately. In this case, a mixed layer containing the constituent materials on both sides is formed near each interface due to the knock-on action of ions, so that the ceramic thin film layer 6a.
６ｂ・・・、金属薄膜層８ａ、８ｂ・・・の密着性の非
常に良いものが得られる。6b..., metal thin film layers 8a, 8b... can be obtained with very good adhesion.
基体４としては、熱伝導性等に優れたものが好ましく、
例えばＡＩ 、Ｃｕ 、各種合金等の金属の場合もある
し、あるいは例えばＡＩＮ、Ｂｅ０１Ａｈａ、等のセラ
ミックの場合もある。セラミックの場合は、基体４上に
積層するセラミック薄膜Ｎ ６ ａ、６ｂ・・、と金属
薄膜層８ａ、８ｂ・・・とは順序が図示とは逆になって
も良い。The base 4 is preferably one with excellent thermal conductivity, etc.
For example, it may be a metal such as AI, Cu, or various alloys, or it may be a ceramic such as AIN, Be01Aha, etc. In the case of ceramic, the ceramic thin films N 6 a, 6b, . . . and the metal thin film layers 8a, 8b, .
セラミック薄膜層６ａ、６ｂ・・・の種類としては、熱
伝導性、電気絶縁性等に優れ誘電率が小さいものが好ま
しく、例えばＢＮ、ＢＰ、ＡＩＮ。As for the type of ceramic thin film layers 6a, 6b..., those having excellent thermal conductivity, electrical insulation, etc. and low dielectric constant are preferable, such as BN, BP, and AIN.
Ｓ ｉｉ’Ｎ ａ 、ダイヤモンド等から選ばれる。Selected from S ii’N a , diamond, etc.
金属薄膜層８ａ、８ｂ・・・の種類としては、導電性等
に優れたものが好ましく、例えばＷ、、 Ｍ。The metal thin film layers 8a, 8b... are preferably made of those having excellent conductivity, such as W, M, etc.
、Ｃｕ ％ ＡＩ−、Ａｇ等から選ばれる。また各金属
、薄膜層８ａ、８ｂ・・・は、必要に応じて、マスクを
使用する等して所定の電気回路にパターン化される。, Cu % AI-, Ag, etc. Further, each metal and thin film layer 8a, 8b, . . . is patterned into a predetermined electric circuit using a mask or the like, if necessary.
〔発明の目的〕
例えば上記積層基ｖｉ２のようないわゆる薄膜タイプの
積層基板の、各金属薄膜層の層間配線をする方法として
は、例えばセラミック薄膜層にプラズマエツチング処理
またはマイクロドリル等でスルーホールを形成した後に
回路パターンのプリント処理あるいは金属薄膜層の被着
およびメタライズ処理等の公知の手段が採り得るけれど
も、加工に手間がかかる、正確な加工が難しい等の問題
があり改良の余地がある。[Object of the Invention] For example, as a method for wiring between the metal thin film layers of a so-called thin film type multilayer board such as the above-mentioned multilayer board VI2, for example, through-holes are formed in the ceramic thin film layer by plasma etching or micro drilling. After formation, known means such as printing a circuit pattern or applying a metal thin film layer and metallizing treatment can be used, but there are problems such as time-consuming processing and difficulty in accurate processing, and there is still room for improvement.
そこでこの発明は、上記のような薄膜タイプの積層基板
の筒車で正確な眉間配線方法を提供することを目的とす
る。Therefore, an object of the present invention is to provide an accurate glabella wiring method using the hour wheel of the thin film type laminated substrate as described above.
この発明の眉間配線方法は、金属薄膜層と電気絶縁性を
有するセラミック薄膜層とを積層した積層基板を作製す
る際における層間配線方法であって、真空中において、
セラミック薄膜層上にマスクを介して金属を蒸着させる
第１の工程と、蒸着金属を加熱処理によってセラミック
薄膜層中へ拡散させて当該セラミック薄膜層中にその両
面間を導通させる合金部を形成する第２の工程とを備え
ることを特徴とする。The eyebrow wiring method of the present invention is an interlayer wiring method for producing a laminated substrate in which a metal thin film layer and an electrically insulating ceramic thin film layer are laminated.
A first step of vapor depositing metal onto the ceramic thin film layer through a mask, and diffusing the vapor deposited metal into the ceramic thin film layer by heat treatment to form an alloy portion in the ceramic thin film layer that conducts between both surfaces thereof. The method is characterized by comprising a second step.
第１の工程によってセラミック薄膜層上に所定パターン
の金属が蒸着され、第２の工程によって当該蒸着金属が
拡散されてセラミック薄膜層中にその両面間を導通させ
る、即ち上下の金属薄膜層間を配線する所定パターンの
合金部が形成される。In the first step, a predetermined pattern of metal is deposited on the ceramic thin film layer, and in the second step, the deposited metal is diffused into the ceramic thin film layer to provide conduction between both sides, that is, to create a wiring between the upper and lower metal thin film layers. A predetermined pattern of alloy parts is formed.
第１図は、実施例に係る層間配線方法を示す工程図であ
る。この例は、第２図に示したような積層基板２の金属
薄膜層８ａと８ｂ間に導通部を形成する場合を示す。FIG. 1 is a process diagram showing an interlayer wiring method according to an embodiment. This example shows a case where a conductive portion is formed between metal thin film layers 8a and 8b of the laminated substrate 2 as shown in FIG.
まず金属薄膜層８ａ上にセラミック薄膜層６ｂを被着さ
せたものを用意しく第１図（Ａ）） 、当該セラミック
薄膜Ｊｉ６ｂ上に所定のパターンをしたマスク１０を装
着しく同図（Ｂ）） 、これを真空容器（図示省略）内
に収納する。そして真空中において、蒸発源（図示省略
）からの金属（金属蒸気）１６を、マスク１０を介して
セラミック薄膜層６ｂ上に蒸着させる（同図（Ｄ））。First, a ceramic thin film layer 6b is prepared on a metal thin film layer 8a (FIG. 1(A)), and a mask 10 having a predetermined pattern is attached to the ceramic thin film Ji6b (FIG. 1(B)). , and this is housed in a vacuum container (not shown). Then, in a vacuum, metal (metal vapor) 16 from an evaporation source (not shown) is evaporated onto the ceramic thin film layer 6b through the mask 10 ((D) in the same figure).
上記の場合、マスク１０のパターンは、必要とする回路
パターンに応じて定められる。また当該マスク１０の厚
みは、セラミック薄膜層６ｂ上に蒸着させる金属１６の
最大厚みに対応し、セラミック薄膜層６ｂの厚みと同程
度かそれ以上とするのが好ましい。これは、後述する工
程によって当該金属１６をセラミック薄膜１６ｂ中へ拡
散させた場合にセラミック薄膜層６ｂの両面間を確実に
導通させるためである。ちなみに、セラミック薄膜層６
ｂ等の厚みは、例えば半導体用であれば高々数千久程度
で十分である。In the above case, the pattern of the mask 10 is determined depending on the required circuit pattern. Further, the thickness of the mask 10 corresponds to the maximum thickness of the metal 16 to be deposited on the ceramic thin film layer 6b, and is preferably equal to or greater than the thickness of the ceramic thin film layer 6b. This is to ensure electrical continuity between both surfaces of the ceramic thin film layer 6b when the metal 16 is diffused into the ceramic thin film 16b in a process described later. By the way, ceramic thin film layer 6
For example, if the thickness is for semiconductors, it is sufficient to have a thickness of several thousand years at most.
一方金属１６としては、セラミック薄膜層６ｂと合金化
し易く、しかも導通抵抗が小さく不純物ができないもの
を選定するのが好ましく、例えば金（Ａｕ ）が選ばれ
る。また見方を変えれば、後述する合金部２０を形成す
るセラミック薄膜層（例えば６ｂ）の種類としては、Ａ
ｕ等と合金化し易いもの、例えばＡ Ｉ Ｎ 、 Ｓ
ｉ ３ Ｎ ４等を選定しておくのが好ましい。On the other hand, as the metal 16, it is preferable to select a metal that is easily alloyed with the ceramic thin film layer 6b, has low conduction resistance, and does not form impurities; for example, gold (Au) is selected. Looking at it from a different perspective, the type of ceramic thin film layer (for example, 6b) that forms the alloy part 20, which will be described later, is A.
Things that are easily alloyed with u, etc., such as A I N, S
It is preferable to select i 3 N 4 or the like.
そして上記蒸着と同時にまたは蒸着後、蒸着金属１６等
をヒータ、赤外線ランプ等の加熱手段（図示省略）で例
えば２００〜６ｏｏ℃程度に加熱して、当該蒸着金属１
６のセラミック薄膜層６ｂ中への拡散を図り、セラミッ
ク薄膜層６ｂ中にその両面間を導通させる合金部（即ち
金属１６とセラミック薄膜層６ｂとの合金部）２０を形
成する（同図（Ｅ））。これによって、上下の金属薄膜
層間を配線する所定パターンの導通部が形成される。Simultaneously with the above vapor deposition or after the vapor deposition, the vapor deposited metal 16 and the like are heated to, for example, about 200 to 60°C using a heating means (not shown) such as a heater or an infrared lamp.
6 is diffused into the ceramic thin film layer 6b to form an alloy portion 20 in the ceramic thin film layer 6b (i.e., an alloy portion of the metal 16 and the ceramic thin film layer 6b) that conducts between both surfaces of the ceramic thin film layer 6b (see (E) in the same figure). )). As a result, a predetermined pattern of conductive portions for wiring between the upper and lower metal thin film layers is formed.
尚、セラミック薄膜層６ｂ上にマスク１０を装着した後
であって金属１６の蒸着を行う前に（即ち同図（Ｄ）の
前に）、当該マスク１０を介して、セラミック薄膜層６
ｂの金属１６を蒸着させる部分に、図示しないイオン源
からの例えばアルゴン、キセノン等の不活性ガスイオン
１２を注入してそこにイオン注入によるダメージ部１４
を形成しても良い（同図（Ｃ））。そのようにすれば、
蒸着金属１６のセラミック薄膜層６ｂ中への拡散率が向
上し、またその部分の合金化を一層促進することができ
る。Note that after the mask 10 is attached to the ceramic thin film layer 6b and before the metal 16 is vapor-deposited (that is, before the step (D) in the figure), the ceramic thin film layer 6 is
Inert gas ions 12 such as argon or xenon from an ion source (not shown) are injected into the portion b where the metal 16 is to be deposited to form a damaged portion 14 due to the ion implantation.
((C) in the same figure). If you do that,
The diffusion rate of the vapor-deposited metal 16 into the ceramic thin film layer 6b is improved, and alloying of that portion can be further promoted.
その場合、注入イオン１２の加速エネルギーは、セラミ
ック薄膜層６ｂの厚みと注入イオン１２の飛程（平均射
影飛程）がほぼ等しくなるような値を選ぶのが好ましい
。そのようにすれば、主にセラミック薄膜層６ｂ内に効
果的にダメージ部１４を形成することができる。イオン
注入のためのイオン源は、一度に大面積の処理ができる
パケット型イオン源を用いるのが好ましい。なおこの時
、注入イオン１２によるボリュームがダメージ部１４内
に形成されることが予想されるため、注入と同時にまた
は注入後、例えば２００〜６００″Ｃ程度の加熱処理を
行っても良い。In that case, the acceleration energy of the implanted ions 12 is preferably selected such that the thickness of the ceramic thin film layer 6b and the range (average projected range) of the implanted ions 12 are approximately equal. In this way, the damaged portion 14 can be effectively formed mainly within the ceramic thin film layer 6b. As the ion source for ion implantation, it is preferable to use a packet type ion source that can process a large area at one time. Note that at this time, since it is expected that a volume due to the implanted ions 12 will be formed in the damaged portion 14, a heat treatment at, for example, about 200 to 600''C may be performed at the same time as the implantation or after the implantation.
上記のようにしてセラミック薄膜層６ｂ中に合金部２０
を形成した後は、マスク１０を取り外してセラミック薄
膜層６ｂ上に次の金属薄膜層８ｂを被着させれば良く
（同図（Ｆ）） 、それによって上下の金属薄膜層８ａ
、８ｂが合金部２０によって所定のパターンで導通する
。以降は必要に応じて、セラミック薄膜層に対する上記
のような工程等を繰り返せば良い。As described above, the alloy portion 20 is formed in the ceramic thin film layer 6b.
After forming, it is sufficient to remove the mask 10 and deposit the next metal thin film layer 8b on the ceramic thin film layer 6b.
((F) in the same figure), thereby the upper and lower metal thin film layers 8a
, 8b are electrically connected in a predetermined pattern by the alloy portion 20. Thereafter, the above steps for the ceramic thin film layer may be repeated as necessary.
従って上記のような方法によれば、セラミック薄膜層に
スルーホール等を形成するような従来技術と違って、金
属薄膜層間の眉間配線を簡単にかつ正確に行うことがで
きる。また上記のような処理は、例えば第２図に示した
ような積層基板２を製造する際に用いる蒸発源やイオン
源等を流用することもでき、そのようにすれば二層簡単
に層間配線を行うことができる。Therefore, according to the method described above, unlike the conventional technique in which through holes or the like are formed in the ceramic thin film layer, the glabella wiring between the metal thin film layers can be easily and accurately performed. In addition, for the above-mentioned processing, it is also possible to use the evaporation source, ion source, etc. used when manufacturing the laminated substrate 2 as shown in FIG. It can be performed.
尚、以上においては第２図に示したような積層基板２の
層間配線を行う場合を例に説明したけれども、この発明
は必ずしもそのようなものに限定されるものではなく、
金属薄膜層とセラミック薄膜層を積層した積層基板を作
製する際における層間配線方法に広く適用することがで
きるのは勿論である。Incidentally, although the above description has been made by taking as an example the case where interlayer wiring of the multilayer substrate 2 as shown in FIG. 2 is performed, the present invention is not necessarily limited to such a case.
It goes without saying that the present invention can be widely applied to interlayer wiring methods when manufacturing a laminated substrate in which a metal thin film layer and a ceramic thin film layer are laminated.
以上のようにこの発明によれば、金属薄膜層間の眉間配
線を簡単にかつ正確に行うことができる。As described above, according to the present invention, glabellar wiring between metal thin film layers can be easily and accurately performed.
第１図は、実施例に係る層間配線方法を示す工程図であ
る。第２図は、積層基板の一例を示す拡大部分断面図で
ある。
２・・・積層基板、４・・・基体、６ａ、６ｂ・・・セ
ラミック薄膜層、３ａ、８ｂ・・・金属薄膜層、１０・
・・マスク、１２・・・イオン、１４・・・ダメージ部
、１６・・・金属、２０・・・合金部。FIG. 1 is a process diagram showing an interlayer wiring method according to an embodiment. FIG. 2 is an enlarged partial cross-sectional view showing an example of a laminated substrate. 2... Laminated substrate, 4... Substrate, 6a, 6b... Ceramic thin film layer, 3a, 8b... Metal thin film layer, 10.
...Mask, 12...Ion, 14...Damage part, 16...Metal, 20...Alloy part.
Claims (1)
層とを積層した積層基板を作製する際における層間配線
方法であって、真空中において、セラミック薄膜層上に
マスクを介して金属を蒸着させる第１の工程と、蒸着金
属を加熱処理によってセラミック薄膜層中へ拡散させて
当該セラミック薄膜層中にその両面間を導通させる合金
部を形成する第２の工程とを備えることを特徴とする積
層基板の層間配線方法。(1) An interlayer wiring method used when manufacturing a laminated substrate in which a metal thin film layer and an electrically insulating ceramic thin film layer are laminated, in which metal is vapor-deposited on the ceramic thin film layer through a mask in a vacuum. A lamination process characterized by comprising a first step and a second step of diffusing vapor deposited metal into the ceramic thin film layer by heat treatment to form an alloy portion in the ceramic thin film layer that provides electrical conduction between both surfaces thereof. Board interlayer wiring method.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10740286A JPS62263695A (en) | 1986-05-09 | 1986-05-09 | Method of interlayer wiring of laminated board |
| US07/048,357 US4831212A (en) | 1986-05-09 | 1987-05-11 | Package for packing semiconductor devices and process for producing the same |
| US07/168,056 US4875284A (en) | 1986-05-09 | 1988-03-14 | Process for producing a package for packing semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10740286A JPS62263695A (en) | 1986-05-09 | 1986-05-09 | Method of interlayer wiring of laminated board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62263695A true JPS62263695A (en) | 1987-11-16 |
Family
ID=14458236
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10740286A Pending JPS62263695A (en) | 1986-05-09 | 1986-05-09 | Method of interlayer wiring of laminated board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62263695A (en) |
-
1986
- 1986-05-09 JP JP10740286A patent/JPS62263695A/en active Pending
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