JPS62263598A - Disaster prevention monitor/control equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field] This invention relates to disaster prevention monitoring and control equipment,
In particular, multiple CPs used in the disaster prevention monitoring and control equipment
This relates to a mutual monitoring system for processors.

[Prior art and problems] Some disaster prevention equipment includes a repeater, a fire sensor that outputs an analog value depending on the degree of the fire phenomenon, a fire detector that outputs an on/off signal to indicate whether a fire is occurring or not. Multiple terminal devices such as fire prevention/smoke prevention equipment, fire extinguishing equipment, and anti-theft equipment are connected to one receiver, and the receiver monitors these terminal devices by performing polling, etc. It reads terminal information, distinguishes it, displays it, or controls the terminal device. In such disaster prevention equipment, there is one in which a receiver or the like is provided with a plurality of processors, that is, CPUs, in order to perform the polling method (or even when using other methods).

In disaster prevention equipment such as this, where the receiver has several CPUs, each CPU has different roles, such as transmission, control, and display, and if an abnormality occurs in even one of the CPUs, normal operation may be interrupted. can't do it.

[Summary of the Invention] The purpose of the present invention is to enable the plurality of CPUs to mutually monitor each other in a facility provided with a plurality of CPUs as described above, and to determine whether or not an abnormality has occurred in the other CPUs. .

Therefore, in the present invention, each of the plurality of CPUs housed in the same device has a separate CPU connected to the corresponding CPU.
As many timer means as there are PUs are connected. Each timer means transmits a signal from another CPU connected to the corresponding CPU to which this timer means is connected to the corresponding CPU.
When U receives the signal, the time counting operation of the timer means is reset by the corresponding CPU, returns to the initial value, and starts the time counting operation again, and this operation is repeated.

If the corresponding CPU does not input a signal from another CPU connected to the corresponding CPU for the set time, the corresponding CPU
Since the time counting operation of the timer means is not reset by U, the timer means outputs a signal indicating this after the set time elapses. This output signal from the timer means causes the CPU in question to send a signal request interrupt signal to another CPU [J, and if no response is received from the other CPU, the CPU in question indicates that the other CPU is abnormal. Outputs a signal indicating that.

[Example 1] Hereinafter, an example of the present invention will be described based on the drawings. FIG. 1 shows a receiver R to which a plurality of terminal devices are connected. A first processor C in the receiver R of FIG.
The PUI includes a transmitter/receiver circuit SRC and a serial/parallel converter circuit DP.
Terminal devices such as a repeater and a fire sensor (not shown) are connected via the TC. As is well known, abnormality detectors such as fire alarms and controlled equipment such as smoke prevention equipment are connected to the repeater. The first processor CPU 1 polls these repeaters and terminal devices such as fire alarms,
Read the monitoring information from the called terminal device and determine the occurrence of a fire (for example, the area where the fire occurred), or
A control command from a second processor CPU2, which will be described later, is sent to a terminal device.

The second processor CPU2 is the first processor CPU
The receiver determines whether or not control of the controlled equipment is necessary based on various information such as fire discrimination information received from I, and if necessary, outputs a control command to the first processor CPUI, or sends it to the operation panel by the operator. OP to third processor C
A control command input via PU3 is relayed to the first processor CPU1, and further to the first processor C
It performs functions such as relaying necessary information from the PUI, for example, regarding the area where a fire occurred, etc., to the third processor CPU3 for display etc. Also, among the fire discrimination information from the first processor CPUI, information that needs to be recorded is transferred to the printer.
It also performs the function of outputting to etc.

The third 10-set CPU 3 is a second processor CPU.
The display information from 2 controls the lighting of the display panel DP and the display on the CRT (cathode ray tube for display), and furthermore, input commands from the operation panel OP are sent to the CPU.
It also performs output to 2.

TM12 to TM32 are counters or timers.

The timer TM12 is connected to the first processor CPU1 and counts the time until the first processor cput receives a signal from the second processor CPU2.

Similarly, the timer TM21 is connected to the second processor CPU2 and counts the time until the second processor CPU2 receives a signal from the first processor CPUI.

The timer TM23 is connected to the second processor CPU2 and counts the time until the second processor CPU2 receives a signal from the third processor CPU3.

Finally, the timer TM32 is connected to the third processor CPU3 and counts the time until the third processor CPU3 receives the signal from the second processor CPU2.

LT12 to LT32 are latches formed of, for example, R-S flip-flops.

The latch LT12 is configured so that the first processor CPU 1
It is set by the first processor CPU1 when an abnormality is determined in the first processor CPU2, and outputs a signal to the display panel DP to display the details of the abnormality.

The latch LT21 is set by the second processor CPU2 when the second processor CPU2 determines that the first processor CPUI is abnormal, and outputs a signal to the display panel DP to display the contents of the abnormality.

The latch L723 is set by the second processor CPU2 when the second processor CPU2 determines that the third processor CPU3 is abnormal, and outputs a signal to the display panel DP to display the contents of the abnormality.

Finally, the latch LT32 is set by the third processor CPU3 when the third processor CPU3 determines that there is an abnormality in the second processor CPU2, and outputs a signal to the display panel DP to display the contents of the abnormality. .

The latches LT12 to LT32 are also connected to the operation panel OP so as to receive a reset signal when the set state is released.

The operation panel oP is equipped with various test switches, control switches, numeric keys, reset switches for latches LT12 to LT32, etc., and the display panel DP is equipped with fire lights, fire area indicator lights, and test/control results. There are provided an indicator light and a failure indicator light that lights up depending on the output of the latches LT12 to LT32.

The operation of the receiver R shown in FIG. 1, particularly the parts related to the present invention, will be explained using FIG. 2.

FIG. 2 is a flowchart showing the operation of the second processor CPU2 to monitor the first and third processors CPUI and CPU3.
The monitoring operation of PU1 is monitored by the third processor CPU3 on the right side.
The monitoring operations are shown respectively.

Under normal operating conditions, the second processor CPU2
and third processors CPUI and CPU3 through interfaces I/F12 and I/F21, and interfaces I/F22 and I/F31, respectively, to information such as the above-mentioned determination information for polling, control information, display information, etc. They constantly exchange information, usually at least once every second, but in some cases information may not be exchanged for a long period of time.

If information is being exchanged, it can be determined that the CPU is operating normally, but if information is not being exchanged for a long period of time, it can be determined whether the CPU is abnormal or not. I can't. CP within this period
If an abnormality occurs in the U itself and you are not aware of it, even if a fire occurs, due to the nature of the disaster prevention equipment, no warning will be given, which could lead to a serious accident.

Therefore, if this information is not exchanged for a predetermined period of time or more, it is preferable to check whether the processor is malfunctioning.

In the first block 100 following the initial setting shown in FIG. 2, it is determined whether or not information has been exchanged within a predetermined period of time, for example, one second, and if no information has been exchanged, the timer TM21 is incremented by +1. (block 101).

In block 102, the timer time accumulated by timer TM21 is compared with the first set time Tl (for example, 3 seconds), and if the timer time is smaller than T1, the CPU is considered normal, and the CPU 3 starts from block 107. Let's move on to the inspection.

If the timer time accumulated by the timer T M 21 is equal to T1, the CPU 2 transmits the signal to the CPU 1 via the line L1 in FIG.
Block 103)
. If CPU1 is normal and responds to this request interrupt signal, CPU2 can receive the signal from CPU1.
21 (block 106) and restarts the timer operation from the beginning. If the CPUI is abnormal and does not respond to the request interrupt signal, the timer time will be greater than T1 (block 102), so the 2 is compared with the set time T'2 (for example, 5 seconds), and if the timer time is greater than T2, the CPU 2 latches LT.
Set 21. By setting the latch LT21, a message indicating that the CPUI is abnormal is displayed on the display panel, and the timer TM21 is reset. This state is maintained until the operator next operates the operation panel to release the latch.

A similar operation for the CPU 2 to test the CPU 3 is also performed on the right side of FIG. That is, in blocks 107 and 108, if there is no signal from the CPU 3, the timer TM23 is activated every predetermined period of time, for example, every second.
is incremented by +1, and in block 109 timer TM2
3'f! When the I calculation time becomes equal to the first set time T1, a signal request interrupt signal is sent from the CPU2 to the CPU3 via the line L2, and if the CPU3 is abnormal and does not respond to the interrupt signal, Moreover, if the timer accumulated time of timer TM23 becomes larger than the second set time T2 in the pro-clock 111, the latch LT2
3 is set and CPU3 is set on the CRT or display panel DP.
A display or alarm is issued to the effect that there is an abnormality, and a printout is printed out on the printer P when necessary.

As described above, the operation according to the present invention is performed by the second processor CP (J
Although only the test operation of No. 2 has been explained, the explanation is omitted because the test operation is exactly the same in the case of the first processor CPUI and the second processor CPU2. That is,
The first processor CPtJ1 uses a timer TM12 to test only the second processor CPU2, and the third processor CPU3 uses a timer TM32 to test only the second processor CPU2. In this case, either the left or right side of FIG. 2 may be substituted for the operation flowchart.

Although one embodiment of the present invention has been described as including a plurality of CPUs in the entire system, this
The present invention is not limited to this, and can also be applied to a case where the -mc system is divided into a plurality of subsystems and these subsystems mutually monitor each other.

[Effects of the Invention] According to the present invention, since the system itself is configured to be monitored by mutually inspecting a plurality of subsystems within the system, it is possible to constantly monitor abnormalities in the system itself. This is particularly effective when this system is used for equipment such as disaster prevention equipment where even the slightest oversight is unacceptable.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram showing a receiver in a disaster prevention monitoring and control facility according to an embodiment of the present invention, and FIG. 2 is a flowchart for explaining the operation of FIG. 1. In the figure, R is a receiver, CPtJl, CPU2 and CPU3 are first, second and third processors, respectively, and TM12 to
TM32 is a timer, LT12 to LT32 are latches, op
is an operation panel, and DP is a display panel.

Claims (2)

[Claims] (1) In disaster prevention monitoring and control equipment that polls each of a plurality of terminal devices from a receiver, reads, discriminates, and displays terminal information from the terminal device, or controls the terminal device, the plurality of receivers are used. Disaster prevention monitoring and control equipment is divided into subsystems, and each subsystem mutually monitors each other. (2) The subsystem is composed of at least two subsystems, and when one subsystem does not receive a signal from the other subsystem within a predetermined time, it sends a signal to the other subsystem. 2. The disaster prevention monitoring and control equipment according to claim 1, wherein when a request is made and the other subsystem does not respond to the request, it is determined that the other subsystem is abnormal.