JPH0659989U - Fire receiver - Google Patents

Abstract

(57) [Summary] [Purpose] Each of the plurality of subsystems sharing the function of the fire receiver determines whether or not the other subsystems exchanging signals are operating normally. [Structure] Transmission subsystem SS1 having CPU1
And a control subsystem SS2 that issues a control command when it is determined from the determination information of the CPU1 that a controlled device among the plurality of terminal devices needs to be controlled, and the display information from the CPU1 is displayed on the display panel DP or the display cathode ray tube CRT The display subsystem SS3 to be displayed on the panel, the panel OP operated by the operator, and C in each subsystem.
The PU is provided with timers TM12 to TM32 connected by the number of other CPUs connected to the CPU.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a fire receiver, and more particularly, it includes a plurality of subsystems that share the functions of the fire receiver, each of which has a CPU or a processor and exchanges signals with other subsystems. It relates to a fire receiver that determines if the system is working properly.

[0002]

[Prior art]

 In some types of disaster prevention equipment, a repeater, a fire sensor that outputs an analog amount of fire signal according to the degree of fire, a fire detector that outputs an on / off signal indicating whether a fire has occurred, a fire prevention Connect multiple terminal devices such as smoke prevention devices, fire extinguishing devices, and anti-theft devices to one receiver, and the receiver performs boring etc. to monitor these terminal devices and sends the monitoring information from the terminal devices. Reads and displays the results, or controls terminal devices. In such a disaster prevention facility, there are some which are provided with a plurality of CPUs in a receiver or the like in order to perform bowling (or in other methods).

[0003]

[Problems to be solved by the device]

 In such a disaster prevention facility having several CPUs in the receiver, each CPU has a role of, for example, a transmission relationship, a control relationship, and a display relationship. There was a problem that could not be done.

The present invention comprises a plurality of subsystems that share the functions of the fire receiver and are electrically connected to each other, each of which has a CPU and exchanges signals with other subsystems. The purpose is to determine if the system is working properly.

[0005]

The present invention has been made to solve such a problem, and includes a transmission subsystem SS1 which is connected to a plurality of terminal devices and reads the monitoring information to make a determination. A control subsystem SS2 which is connected to the transmission subsystem SS1 and determines from the discrimination information whether or not the controlled equipment of the terminal equipment needs to be controlled, and generates a control command if necessary. The display subsystem SS3 connected to the control subsystem SS2 to display the display information from the transmission subsystem SS1 on the display panel DP or the cathode ray tube CRT for display is operated by the operator. An operation panel OP for inputting control commands to the display subsystem SS3, and each subsystem connected to the subsystem The Ru der that a number fraction only connected timer TM12~TM32 other subsystems.

[0006]

[Action]

 For this reason, in this invention, a timer is connected to each of the plurality of CPUs housed in the fire receiver and electrically connected to each other as many as the number of other CPUs connected to the CPU. When each CPU receives a signal from another CPU connected to the CPU to which the timer is connected, the CPU resets the time counting operation of the timer and resets the initial value. Return to and repeat the time counting operation, and repeat this operation. If a signal from another CPU connected to the relevant CPU is not input to the relevant CPU during the set time, the time counting operation of the timer by that CPU is not reset. Outputs a signal to that effect. When this CPU outputs the signal request interrupt signal to the other CPU by this output signal from the timer and the response from the other CPU is not obtained, the CPU determines the other CPU. A signal indicating that the CPU is abnormal is output.

[0007]

【Example】

 An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram showing a fire receiver R to which a plurality of terminal devices are connected. This fire receiver R comprises a plurality of subsystems, for example, three subsystems SS1 to SS3, which share the functions thereof. The subsystem SS1 has a first processor CPU1, and the first processor CPU1 is provided with a relay device (not shown) via the transmission / reception circuit SRC or via the transmission / reception circuit SRC and the serial / parallel conversion circuit DPTC. Terminal devices such as fire sensors are connected. As is well known, anomaly detectors such as fire detectors and controlled devices such as smoke prevention devices are connected to the repeater. The first processor CPU1 polls these repeaters and terminal devices such as a fire sensor, reads the monitoring information from the called terminal device, and determines the occurrence of a fire (for example, a fire occurrence area), or Sends a control command from the second processor CPU2 in the subsystem SS2 described later to the terminal device.

The second processor CPU2 determines whether or not control of the controlled device is necessary from various information such as fire determination information regarding the fire occurrence area and the like received from the first processor CPU1, and controls if necessary. Outputs a command to the first processor CPU1 or relays a control command input by the operator from the operation panel OP via the third processor CPU3 in the subsystem SS3 to the first processor CPU1; Further, it performs functions such as relaying necessary information from the first processor CPU1 to the third processor CPU3 for display and the like. Further, it also has a function of outputting to the printer P or the like the information that needs to be recorded among the fire discrimination information from the first processor CPU1.

The third processor CPU3 performs lighting control of the display panel DP, display control to a CRT (cathode ray tube for display), etc. according to the display information from the second processor CPU2, and further the operation panel OP. It also outputs the input command from the second processor CPU2.

TM12 to TM32 are counters or timers. The timer TM12 is connected to the first processor CPU1, counts the time until the first processor CPU1 receives a signal from the second processor CPU2, and does not receive the signal within a predetermined time. In that case, the first processor CPU1 outputs a signal to that effect. Similarly, the timer TM21 is connected to the second processor CPU2, counts the time until the second processor CPU2 receives the signal from the first processor CPU1, and also sends the signal to the second processor CPU2. Output. The timer TM23 is connected to the second processor CPU2, counts the time until the second processor CPU2 receives the signal from the third processor CPU3, and sends the signal to the second processor CPU2. Output. Finally, the timer TM32 is connected to the third processor CPU3, counts the time until the third processor CPU3 receives the signal from the second processor CPU2, and sends the signal to the third processor CPU3. Output.

The LT12 to LT32 are latches formed of, for example, RS flip-flops. The latch LT12 is set by the first processor CPU1 when the first processor CPU1 determines the abnormality of the second processor CPU2, and outputs a signal to the display panel DP for displaying the abnormality content. The latch LT21 is set by the second processor CPU2 when the second processor CPU2 determines the abnormality of the first processor CPU1 and outputs a signal to the display panel DP for displaying the abnormality content. The latch LT23 is set by the second processor CPU2 when the second processor CPU2 determines the abnormality of the third processor CPU3, and outputs a signal to the display panel DP for displaying the abnormality content. Finally, the latch LT32 is set by the third processor CPU3 when the third processor CPU3 determines the abnormality of the second processor CPU2, and outputs a signal to the display panel DP to display the content of the abnormality. The latches LT12 to LT32 are also connected to the operation panel OP so as to receive a reset signal when the set state is released.

The operation panel OP is provided with various kinds of test switches, control switches, numeric keypads, and reset switches for latches LT12 to LT32 drunk, and the display panel DP has a fire lamp and a fire area indicator lamp. A test / control result display lamp, a failure display lamp that is turned on by the outputs of the latches LT12 to LT32, and the like are provided.

The operation of the fire receiver R of FIG. 1, particularly the portion related to the present invention, will be described with reference to FIG. FIG. 2 is a flowchart showing the operation of the second processor CPU2 for monitoring the first and third processors CPU1 and CPU3. The left side of the figure shows the monitoring operation of the first processor CPU1 and the right side shows the third operation. The respective monitoring operations of the processor CPU3 are shown. In a normal operating state, the second processor CPU2 is connected to the first and third processors CPU1 and CPU3 via the interfaces I / F12 and I / F21 and the interfaces I / F22 and I / F31, respectively, and the above-described polling is performed. For this reason, information such as discrimination information, control information, and display information is constantly exchanged, and the frequency is usually at least once a second, for example, but in some cases, information may be transmitted over a long period of time. Sometimes there is no interaction. When the information is exchanged, it can be determined that the CPUs are operating normally, but when the information is not exchanged for a long period of time, it is determined whether the CPU is abnormal. I can't. If an abnormality occurs in the CPU itself during this period and you are not aware of it, even if a fire occurs due to the nature of the disaster prevention equipment, it will not warn you and may cause a serious accident. Therefore, when this information is not exchanged for a predetermined time or longer, it is preferable to inspect whether the processor is out of order.

In the first block 100 following the initial setting in FIG. 2, it is judged whether or not information is exchanged for a predetermined time (for example, within 1 second), and if the information is not exchanged. In block 101, the timer TM21 is incremented by +1. In block 102, the timer time loaded by the timer TM21 is compared with the first set time T1 (for example, 3 seconds), and if the timer time is smaller than T1, the first processor CPU1 is regarded as normal, The process proceeds to the inspection of the third processor CPU3 starting from block 107. If the timer time accumulated by the timer TM21 is equal to T1, the second processor CPU2 sends a signal request interruption signal to the first processor CPU1 via the line L1 in block 103 in block 103. If the first processor CPU1 is normal and responds to this signal request interrupt signal, the second processor CPU2 will be able to receive the signal from the first processor CPU1 (see block 100). ), The timer TM21 is reset by the block 106, and the counting of the timer operation is restarted from the beginning. When the first processor CPU1 is abnormal and does not respond to the signal request interrupt signal, the timer time becomes longer than T1 (block 102), so the block 104 sets the second set time T2 (for example, 5 seconds). The second processor CPU2 sets the latch LT21 at block 105 if the timer time is greater than T2. By setting the latch LT21, a message indicating that the first processor CPU1 is abnormal is displayed on the display panel DP, and the processor 106 resets the timer TM21. This state is maintained until the operator next operates the operation panel OP to release the latch.

In the right part of FIG. 2, the same operation for the second processor CPU2 to check the third processor CPU3 is performed. That is, in blocks 107 and 108, when there is no signal from the third processor CPU3, the timer TM23 is incremented by +1 every predetermined time (for example, within 1 second), and the timer TM23 is integrated in the block 109. If the timer time has become equal to the first set time T1, in block 110 a signal request interrupt signal is sent from the second processor CPU2 to the third processor CPU3 via line L2, if the third If the processor CPU3 of the CPU is abnormal and does not respond to the signal request interrupt signal, and the integrated timer time of the timer TM23 becomes larger than the second set time T2 in the block 111, the same is determined in the block 112. The latch LT23 is set, and a message indicating that the third processor CPU3 is abnormal is displayed on the CRT or display panel DP. They are, or are alarm, if necessary be printed out to the printer P. Then, in block 113, the timer 23 is reset.

The operation according to the present invention has been described above only with respect to the inspection operation of the second processor CPU2. However, the same inspection operation is performed in the case of the first processor CPU1 and the third processor CPU3, and the description thereof is omitted. did. That is, the first processor CPU1 inspects only the second processor CPU2 with the timer TM12, and the third processor CPU3 inspects only the second processor CPU2 with the timer TM32. In this case, the operation flowchart may be substituted by either the left side or the right side of FIG.

Although one embodiment of the present invention has been described with respect to the whole system including a plurality of CPUs, this is not limited to the CPUs, and the system is generally divided into a plurality of subsystems. It can also be applied when these subsystems monitor each other.

[0018]

[Effect of device]

 As described above, according to the present invention, the system itself is configured to be monitored by mutually inspecting a plurality of subsystems in the system. Therefore, it is possible to constantly monitor the abnormality of the system itself. This is especially effective when the system is used in equipment that cannot be overlooked, such as disaster prevention equipment. In addition, since the present invention uses a signal that normally steadily fluctuates between each subsystem and other subsystems, it is not necessary to interrupt the signal request during the period, and therefore, the other This has the effect that the signal processing of other subsystems is not unnecessarily interrupted in order to confirm whether or not the subsystem is normal.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a fire receiver according to the present invention.

FIG. 2 is a flowchart for explaining the operation of the fire receiver shown in FIG.

[Explanation of symbols]

R Fire receiver SS1-SS3 subsystem CPU1, CPU2, and CPU3 First, second, and third processors TM12-TM32 timers LT12-LT32 are latches OP operation panel DP display panel

Claims (1)

[Scope of utility model registration request] 1. A transmission subsystem SS1 which is connected to a plurality of terminal devices and reads and discriminates monitoring information thereof,
A control subsystem SS2 which is connected to the transmission subsystem SS1 and determines from the discrimination information whether or not the controlled device among the terminal devices needs control, and generates a control command if necessary. This control subsystem SS2
The display information from the transmission subsystem SS1 is connected to the display panel DP or the display cathode ray tube CR.
A display subsystem SS3 to be displayed on the T, an operation panel OP for inputting a control command to the display subsystem SS3 by being operated by an operator, and each subsystem including other subsystems connected to the subsystem. Timers TM12 to TM connected by the number of systems
32, the control command generated by the control subsystem SS2 is transmitted to the controlled device via the transmission subsystem SS1, and the control command input to the display subsystem SS3 is the control command. And transmission subsystem S
Each timer is transmitted to the controlled device via S2 and SS1, and a signal from another subsystem connected to the subsystem to which the timer is connected is input to the subsystem during a set time. Otherwise, the subsystem outputs a signal to that effect, and the subsystem outputs a signal request interrupt signal to the other subsystem by the timer output signal, and if there is no response to this, the other subsystem outputs A fire receiver characterized by outputting a signal indicating an abnormality and displaying the signal on the display panel DP.