JPS62262539A - Subsequent synchronizing system - Google Patents

Abstract

PURPOSE:To avoid the increase in a subsequent synchronizing circuit due to the increase in number of relay lines by providing only one subsequent synchronizing circuit to a multiplexing device and using the control ware so as to select a subsequent clock optionally thereby preventing the clock intermission to a terminal line due to the fault of a relay line. CONSTITUTION:The fault of a relay line 41 is detected by a fault detection circuit 141. Then a relay line interface 21 outputs an interruption signal representing the occurrence of the fault to a control section 11. Thus, the relay line interface 21 outputs an interruption signal for the occurrence of a fault. The control section 11 selects other line having no fault detection report and gives a clock output stop command to a relay line interface 21 through an I/O bus 12. A clock outputted to a signal line 19 supplying a clock to a subsequent period circuit 17 at this point of time is switched into a clock on the signal line 62 of the normal relay line interface 22. Then the phase locked loop circuit of the circuit 17 is operated by using a clock on a new signal line 62 as a reference signal.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a multiplex collection/distribution bag (hereinafter referred to as TDM) which is subordinately synchronized to the clock of a trunk line, and in particular has a common oscillation source and each speed TD that connects multiple lines without deviation
This invention relates to a dependent synchronization method suitable for M.

[Conventional technology]

As is well known, TDMs are installed facing each other via a high-speed relay line, and have the function of multiplexing data from a group of terminal lines and relaying the data over the high-speed line.

In the conventional slave synchronization system in TDM, when there are multiple trunk lines as shown in FIG. 3, each trunk line 41.
42 clocks are associated with terminal line groups 91 and 92, and the clocks extracted by each trunk line interface 21 and 22 are distributed from the slave synchronization circuits 71 and 72 to the associated terminal interfaces 31 and 32. However, when a relay line fails, it becomes impossible to extract the clock, and the supply of clocks to the terminal equipment group 101 and 102 is interrupted.
The terminal device hangs up.

Furthermore, as described in Japanese Patent Application Laid-Open No. 49-21007, there is a method of outputting a clock from a unique fixed frequency oscillator when a clock disconnection in a relay line is detected, but there is a method that outputs a clock from a unique fixed frequency oscillator. clock guarantee is not taken into consideration.

[Problem that the invention seeks to solve]

The above conventional technology does not take into consideration the supply of clock to the terminal line when the clock cannot be extracted from the relay line, or when the clock cannot be supplied temporarily, so that the terminal line is always normally operated or locked. was not done.

An object of the present invention is to enable the TDM to always synchronize with the clock of the trunk line even if any trunk line connected to the TDM fails, and to prevent the logical amount from increasing even if the number of trunk lines increases. The purpose is to provide a synchronization method.

[Means for solving problems]

The above purpose is to provide a TDM with only one dependent synchronization circuit, which is composed of a phase-locked loop circuit that operates in slave synchronization with the clock of the trunk line and supplies the clock to the terminal line, and a control software that uses the clock extracted from the trunk line. This is achieved by providing a circuit for supplying and controlling the slave synchronous circuit according to instructions from the controller, and supplying a clock from any normal relay line to the slave synchronous circuit according to controlware instructions, thereby performing slave synchronization.

[Effect]

Compared to the process of switching a new clock supply using control software, if the time from the reference signal disconnection of the phase-locked loop circuit to complete free running at the natural frequency is made sufficiently large, the clock supplied to the terminal line will always be the same as that of the relay line. Synchronized to the clock. Therefore, there is no need for a clock supply station to the terminal line or a change in the speed of the clock, thereby preventing the terminal device from hanging up.

〔Example〕

An embodiment of the present invention will be described below in detail with reference to the drawings.

In Figure 1, 11 is T by controlware.
A control unit that controls the entire DMIO; 12 is an I10 bus from the control unit 11 to trunk line interfaces 21 and 22;
31 and 132 are I1 that each trunk line interface has.
0 instruction decoding circuit, 141.142 is the failure detection port fl of the relay line, /l 51152 is the clock output instruction signal extracted at each interface from the control unit 11 to the slave synchronization circuit 17 described later, 61.62 is the extracted TDMI consists of signal lines for sending clocks, 161 and 162 are clock output gate circuits, and 17 is a phase-locked loop circuit.
18 is a clock line for supplying the terminal interface, and 19 is a signal line for supplying the selected clock to the slave synchronous circuit 17.

Normally, when starting up TDMIO, the control unit 11 does not detect any faults on the trunk line interface, for example, 21.
The output instruction of the hekrosoku is given through the I10 bus 12, and the I10 decoding circuit 1 of the trunk line interface 21
31 controls the output instruction signal 151, and the gate circuit 161
open. The clock on the signal line 61 extracted by the trunk line interface 21 is given to the slave synchronization circuit 17 through the signal line 19 which supplies the clock to the slave synchronization circuit 17. By the way, the slave synchronization circuit 17 consists of a phase-locked loop circuit that performs slave synchronization with reference to the signal on the signal line 19 and generates a high-frequency clock, and a frequency divider circuit that divides the high-frequency clock into a required frequency. It is configured. The slave-synchronized clock is supplied to the terminal interface group 31. through the clock supply a18 to the terminal interface.
32 and output to terminal lines 91.92.

When a fault occurs in the trunk line 41, the fault is detected by the fault detection circuit 141. Trunk line interface 21
immediately issues an interrupt signal to the control unit 11 indicating that a failure has occurred. When the control unit 11 receives this interrupt, it selects another normal trunk line, that is, a line that has not reported failure detection, issues a clock output stop command to the trunk line interface 21 through the I10 bus 12, and A command for instructing clock output is issued to 22. At this point, the clock output to the signal line 19 supplying the clock to the slave synchronization circuit 17 is the signal %9 from the clock on the signal line 61.
Switching to the clock on i62, the phase-locked loop circuit of the slave synchronization circuit 17 operates using the clock on 3', '1BG2 as a reference signal.

As shown in Fig. 2, if the time required for the phase-locked loop circuit to stop receiving a reference signal and stabilize in free-running mode is set as a time constant on the order of seconds, it will be possible to detect the occurrence/detection of a fault in the trunk line interface 21. The clock output switching time t□ to the interface 22 by the control software is several milliseconds.

The recovery time t of the phase lock loop circuit with the new clock is about the same as t□. During this time, the change in the clock of the phase-locked loop circuit is suppressed to about 1 percent.

Therefore, the processing during this period is preferentially performed in a short time by the controlware of the control unit 11, and if the time constant for synchronization stabilization of the phase-locked loop circuit is set large, the clock is sent to the terminal interface via the clock supply line 18. There is no change in the speed of the clock, and the clocks output to the terminal lines 91 and 92 can be supplied without change.

Furthermore, as a matter of course, even if a failure occurs in a relay line that does not output a clock to the signal line 19 as a reference signal, the clock can continue to be supplied without any problem.

As described above, with this method, it is possible to eliminate the change in the speed of the clock supplied to the terminal line due to clock switching in the event of a failure of any trunk line, and even if the number of trunk lines increases, the circuit for slave synchronization can be maintained. There is no need to increase it.

〔Effect of the invention〕

According to the present invention, in a multiplexing device in which a plurality of relay lines with no speed deviation are connected and slave synchronized to the clock thereof, only one slave synchronization circuit is provided in the device, and a slave clock is arbitrarily selected by control software. Therefore, it is possible to prevent the clock from being cut off to the terminal line due to a relay line failure, and there is an effect of eliminating an increase in the number of dependent synchronous circuits due to an increase in the number of relay lines.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a slave synchronization method using the present invention, FIG. 2 is a time chart showing changes in the terminal line clock when the present invention is used, and FIG. 3 shows a conventional slave synchronization method. It is a block diagram. 10... Multiplex distribution device (TDM), 11... (control unit), 17... dependent synchronous circuit, 18... (clock supply line), 21.22... relay line interface, 31 .32...Terminal interface, 141, 142
...fault detection circuit

Claims (1)

[Claims] 1. In a multiplex concentrator/distribution device in which a plurality of relay lines having the same clock oscillation source are connected and supply a clock to a terminal side line in subordinate synchronization with the clock, only one is provided in the device and the clock of the relay line is synchronized with the clock. a circuit that outputs a clock in slave synchronization with the relay line; means for detecting that a failure has occurred in the relay line; and the relay line receiving a failure detection signal from the failure detection means and inputting it to the slave synchronization circuit. and control means for switching the clock of the relay line to the clock of another normal relay line.